WO2005017959A3 - Integrated circuit with test pad structure and method of testing - Google Patents
Integrated circuit with test pad structure and method of testing Download PDFInfo
- Publication number
- WO2005017959A3 WO2005017959A3 PCT/US2004/022509 US2004022509W WO2005017959A3 WO 2005017959 A3 WO2005017959 A3 WO 2005017959A3 US 2004022509 W US2004022509 W US 2004022509W WO 2005017959 A3 WO2005017959 A3 WO 2005017959A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- module
- bond pads
- test
- pads
- testing
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
- G01R31/31715—Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3187—Built-in tests
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
Abstract
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04778153A EP1664808A2 (en) | 2003-08-05 | 2004-07-15 | Integrated circuit with test pad structure and method of testing |
KR1020067002403A KR101048576B1 (en) | 2003-08-05 | 2004-07-15 | Integrated circuits, test apparatus and methods, and integrated circuit fabrication methods |
JP2006522572A JP4837560B2 (en) | 2003-08-05 | 2004-07-15 | Integrated circuit having inspection pad structure and manufacturing method thereof |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/634,484 | 2003-08-05 | ||
US10/634,484 US6937047B2 (en) | 2003-08-05 | 2003-08-05 | Integrated circuit with test pad structure and method of testing |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2005017959A2 WO2005017959A2 (en) | 2005-02-24 |
WO2005017959A3 true WO2005017959A3 (en) | 2005-09-09 |
Family
ID=34116043
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2004/022509 WO2005017959A2 (en) | 2003-08-05 | 2004-07-15 | Integrated circuit with test pad structure and method of testing |
Country Status (7)
Country | Link |
---|---|
US (1) | US6937047B2 (en) |
EP (1) | EP1664808A2 (en) |
JP (1) | JP4837560B2 (en) |
KR (1) | KR101048576B1 (en) |
CN (1) | CN100514076C (en) |
TW (1) | TWI354346B (en) |
WO (1) | WO2005017959A2 (en) |
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US7692315B2 (en) * | 2002-08-30 | 2010-04-06 | Fujitsu Microelectronics Limited | Semiconductor device and method for manufacturing the same |
JP4426166B2 (en) * | 2002-11-01 | 2010-03-03 | ユー・エム・シー・ジャパン株式会社 | Semiconductor device design method, semiconductor device design program, and semiconductor device |
JPWO2004102653A1 (en) * | 2003-05-15 | 2006-07-13 | 新光電気工業株式会社 | Semiconductor device and interposer |
JP2005209239A (en) * | 2004-01-20 | 2005-08-04 | Nec Electronics Corp | Semiconductor integrated circuit apparatus |
JP4803966B2 (en) * | 2004-03-31 | 2011-10-26 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
DE102006008454B4 (en) * | 2005-02-21 | 2011-12-22 | Samsung Electronics Co., Ltd. | Pad structure, pad layout structure, semiconductor device, and pad layout method |
KR100699838B1 (en) * | 2005-04-13 | 2007-03-27 | 삼성전자주식회사 | A semiconductor device including the ROM interface PAD |
US7489151B2 (en) * | 2005-10-03 | 2009-02-10 | Pdf Solutions, Inc. | Layout for DUT arrays used in semiconductor wafer testing |
US7417449B1 (en) * | 2005-11-15 | 2008-08-26 | Advanced Micro Devices, Inc. | Wafer stage storage structure speed testing |
JP4986114B2 (en) * | 2006-04-17 | 2012-07-25 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit and design method of semiconductor integrated circuit |
US20080252330A1 (en) * | 2007-04-16 | 2008-10-16 | Verigy Corporation | Method and apparatus for singulated die testing |
US7566648B2 (en) * | 2007-04-22 | 2009-07-28 | Freescale Semiconductor Inc. | Method of making solder pad |
US7902852B1 (en) * | 2007-07-10 | 2011-03-08 | Pdf Solutions, Incorporated | High density test structure array to support addressable high accuracy 4-terminal measurements |
KR101318946B1 (en) * | 2007-08-09 | 2013-10-17 | 삼성전자주식회사 | Test device, SRAM test device and semiconductor intergrated circuit device |
US7977962B2 (en) | 2008-07-15 | 2011-07-12 | Micron Technology, Inc. | Apparatus and methods for through substrate via test |
US8779790B2 (en) * | 2009-06-26 | 2014-07-15 | Freescale Semiconductor, Inc. | Probing structure for evaluation of slow slew-rate square wave signals in low power circuits |
CN102023236A (en) * | 2009-09-11 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Test structure and test method |
KR20120002761A (en) * | 2010-07-01 | 2012-01-09 | 삼성전자주식회사 | Method for arranging pads in a semiconductor apparatus, semiconductor memory apparatus using it, and processing system having it |
US11482440B2 (en) * | 2010-12-16 | 2022-10-25 | Monolithic 3D Inc. | 3D semiconductor device and structure with a built-in test circuit for repairing faulty circuits |
KR101198141B1 (en) * | 2010-12-21 | 2012-11-12 | 에스케이하이닉스 주식회사 | Semiconductor memory apparatus |
KR101682751B1 (en) * | 2011-06-30 | 2016-12-05 | 주식회사 아도반테스토 | Methods, apparatus, and systems for contacting semiconductor dies that are electrically coupled to test access interface positioned in scribe lines of a wafer |
TWI483361B (en) * | 2012-03-23 | 2015-05-01 | Chipmos Technologies Inc | Chip packaging substrate and chip packaging structure |
KR102120817B1 (en) * | 2013-10-28 | 2020-06-10 | 삼성디스플레이 주식회사 | Driving integrated circuit pad unit and flat display panel having the same |
US10340203B2 (en) * | 2014-02-07 | 2019-07-02 | United Microelectronics Corp. | Semiconductor structure with through silicon via and method for fabricating and testing the same |
CN104851875B (en) * | 2014-02-18 | 2019-07-23 | 联华电子股份有限公司 | Semiconductor structure with through silicon via and preparation method thereof and test method |
US9373539B2 (en) | 2014-04-07 | 2016-06-21 | Freescale Semiconductor, Inc. | Collapsible probe tower device and method of forming thereof |
KR20160056379A (en) | 2014-11-10 | 2016-05-20 | 삼성전자주식회사 | Chip using triple pad configuration and packaging method thereof |
KR20170042897A (en) * | 2015-10-12 | 2017-04-20 | 에스케이하이닉스 주식회사 | Semiconductor device |
CN105467172B (en) * | 2016-01-01 | 2019-05-21 | 广州兴森快捷电路科技有限公司 | A kind of CAF test board having switching circuit |
US10876988B2 (en) * | 2016-05-13 | 2020-12-29 | Weir Minerals Australia Ltd. | Wear indicating component and method of monitoring wear |
DE102016114146A1 (en) * | 2016-08-01 | 2018-02-01 | Endress+Hauser Flowtec Ag | Test system for checking electronic connections |
BR112019006091A2 (en) * | 2016-09-28 | 2019-06-18 | Smc Corp | position detection switch and method for manufacturing it |
CN107167685B (en) * | 2017-06-27 | 2019-09-06 | 苏州苏纳光电有限公司 | The electrical testing method and system of face-down bonding |
US10495683B2 (en) * | 2018-01-18 | 2019-12-03 | Viavi Solutions Deutschland Gmbh | Power supply stress testing |
US10658364B2 (en) * | 2018-02-28 | 2020-05-19 | Stmicroelectronics S.R.L. | Method for converting a floating gate non-volatile memory cell to a read-only memory cell and circuit structure thereof |
US10969434B2 (en) * | 2019-09-03 | 2021-04-06 | Micron Technology, Inc. | Methods and apparatuses to detect test probe contact at external terminals |
CN111292661B (en) * | 2020-03-30 | 2023-07-21 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
TW202349576A (en) * | 2020-07-31 | 2023-12-16 | 矽創電子股份有限公司 | Flow guiding structure of chip |
KR20220076177A (en) * | 2020-11-30 | 2022-06-08 | 삼성전자주식회사 | Film for package substrate and semiconductor package comprising the same |
CN113782463A (en) * | 2021-08-24 | 2021-12-10 | 芯盟科技有限公司 | Bonding strength testing method |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6008061A (en) * | 1996-10-11 | 1999-12-28 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device having a test pad |
US6214630B1 (en) * | 1999-12-22 | 2001-04-10 | United Microelectronics Corp. | Wafer level integrated circuit structure and method of manufacturing the same |
Family Cites Families (8)
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JPH04111328A (en) * | 1990-08-30 | 1992-04-13 | Nec Ic Microcomput Syst Ltd | Integrated circuit device |
US5399505A (en) | 1993-07-23 | 1995-03-21 | Motorola, Inc. | Method and apparatus for performing wafer level testing of integrated circuit dice |
FR2714528B1 (en) * | 1993-12-27 | 1996-03-15 | Sgs Thomson Microelectronics | Integrated circuit test structure. |
US5554940A (en) | 1994-07-05 | 1996-09-10 | Motorola, Inc. | Bumped semiconductor device and method for probing the same |
KR100269540B1 (en) * | 1998-08-28 | 2000-10-16 | 윤종용 | Method for manufacturing chip scale packages at wafer level |
JP3908908B2 (en) * | 1999-01-22 | 2007-04-25 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit device |
US6844631B2 (en) | 2002-03-13 | 2005-01-18 | Freescale Semiconductor, Inc. | Semiconductor device having a bond pad and method therefor |
US6614091B1 (en) | 2002-03-13 | 2003-09-02 | Motorola, Inc. | Semiconductor device having a wire bond pad and method therefor |
-
2003
- 2003-08-05 US US10/634,484 patent/US6937047B2/en not_active Expired - Lifetime
-
2004
- 2004-07-15 EP EP04778153A patent/EP1664808A2/en not_active Withdrawn
- 2004-07-15 KR KR1020067002403A patent/KR101048576B1/en not_active IP Right Cessation
- 2004-07-15 JP JP2006522572A patent/JP4837560B2/en not_active Expired - Fee Related
- 2004-07-15 CN CNB2004800199113A patent/CN100514076C/en active Active
- 2004-07-15 WO PCT/US2004/022509 patent/WO2005017959A2/en active Application Filing
- 2004-07-21 TW TW093121773A patent/TWI354346B/en not_active IP Right Cessation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6008061A (en) * | 1996-10-11 | 1999-12-28 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device having a test pad |
US6214630B1 (en) * | 1999-12-22 | 2001-04-10 | United Microelectronics Corp. | Wafer level integrated circuit structure and method of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
JP2007501522A (en) | 2007-01-25 |
KR101048576B1 (en) | 2011-07-12 |
EP1664808A2 (en) | 2006-06-07 |
CN100514076C (en) | 2009-07-15 |
KR20070007014A (en) | 2007-01-12 |
TWI354346B (en) | 2011-12-11 |
US6937047B2 (en) | 2005-08-30 |
TW200514187A (en) | 2005-04-16 |
JP4837560B2 (en) | 2011-12-14 |
WO2005017959A2 (en) | 2005-02-24 |
US20050030055A1 (en) | 2005-02-10 |
CN1823277A (en) | 2006-08-23 |
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