WO2005013490A1

WO2005013490A1 - Switch module for a field programmable logic circuit

Info

Publication number: WO2005013490A1
Application number: PCT/IB2004/051317
Authority: WO
Inventors: Rohini Krishnan; Jose D. J. Pineda De Gyvez
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2003-08-05
Filing date: 2004-07-28
Publication date: 2005-02-10

Abstract

A Switch Module for a field programmable logic circuit, such as a field programmable gate array (FPGA), and a set of programmable switches (900) at least one of the switches (900) comprising a dual threshold MOS transistor (900) and means (such as a limiting or augmenting transistor) (100) for increasing the gate voltage at which said transistor (900) can operate. The invention provides an ultra low power Switch Module for use in FPGA's, which works well for nominal supply voltages and optimally for lower supply voltages, thereby making it suitable for low voltage swing applications as well. The resultant Switch Module has been found to have a significantly improved energy-delay product and a significantly reduced leakage in stand-by, when compared to conventional designs, with an almost negligible area overhead.

Description

SWITCH ODULE FOR A FIELD PROGRAMMABLE LOGIC CIRCUIT

This invention relates to a Switch Module and, more particularly, to a Switch Module for a field programmable gate array (FPGA).

A field programmable gate array (FPGA) is an integrated circuit that can be programmed in the field, after manufacture. FPGAs are composed of logic blocks, I/O blocks and programmable routing. Referring to Fig. 1, there is illustrated an island-style FPGA where the logic blocks 100 are surrounded by prefabricated wiring segments 200 on all four sides. A logic block input or output can connect to some or all of the wiring segments 200 in the channel adjacent to it, via a connection block of programmable switches. At every intersection of a horizontal and vertical channel, there is a switch box 300. Henceforth, in this document we refer to both the switch box and connection box by the term switch module. The invention described here is applicable to connection, switch boxes and any set of programmable switches in a FPGA. A switch box is a set of programmable switches which allow some of the wire segments incident on it to be connected to others. By turning on the appropriate switches, short wire segments can be connected together to form longer connections. Switch Modules have been conventionally implemented using either pass transistor switches 400 or tri-state buffer switches 500, as shown in Figs. 2, 3(a) and 3(b). The transistors in the switch box 600 add capacitance and resistance loading to each track in a channel, and hence the Switch Module 600 has a significant effect on the speed of each routable connection an a major impact on the overall power dissipation in a FPGA. Also the short circuit power dissipation in the buffers following the NMOS pass transistor switches is high due to the threshold (Vt) drop across the NMOS transistor resulting in the high Vdd signal at its input being degraded to Vdd - Vt at the output. In the past, research has been focused on various switch block architectures for improving routability and reducing delays caused by the resistance and capacitance of the transistors constituting a Switch Module. For example, US Patent No. 5,600,264 describes a programmable single buffered six-transistor switch box, which acts as a programmable junction between four intersecting lines. The switch box allows any two of the lines to be programmably interconnected to form a signal channel. Alternatively, two sets of the four lines can be programmably interconnected so that two signal channels are formed. One line output of the switch box can be programmably buffered. By buffering the output signal, delay introduced by resistance and capacitance of the transistors constituting the switch box can be reduced. A multiplexer circuit and demultiplexer circuit configuration is used to perform proper routing.

However, there is a need for an improved Switch Module circuit design for low power and high speed applications. In accordance with the present invention, there is provided a Switch Module for a field programmable logic circuit, the Switch Module comprising one or more inputs, one or more outputs, and a set of programmable switches between said one or more inputs and outputs, the Switch Module being characterized in that at least one of said switches comprises a dual threshold MOS transistor and means for increasing the gate voltage at which said transistor can operate. The means for increasing the gate voltage at which the transistor can operate may comprise an augmenting transistor or a limiting transistor. The dual threshold transistor may have a relatively high or moderate threshold voltage. In one embodiment of the invention, one or more buffers are provided at the one or more outputs of the Switch Module.

These one or more buffers may include a sleep transistor, preferably with a relatively high threshold voltage. Thus, the present invention provides an ultra low power Switch Module for use in FPGA's, which works well for nominal supply voltages and optimally for lower supply voltages, thereby making it suitable for low voltage swing applications as well. The resultant Switch Module has been found to have a significantly improved energy-delay product and a significantly reduced leakage in stand-by, when compared to conventional designs, with an almost negligible area overhead. These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. Embodiments of the present invention will now be described by way of examples only and with reference to the accompanying drawings, in which: Fig. 1 is a schematic block diagram illustrating the configuration of an island- style FPGA according to the prior art; Fig. 2 is a schematic diagram illustrating the configuration of a switch box according to the prior art; Figs. 3(a) and 3(b) are schematic circuit diagrams illustrating two switch boxes according to the prior art; Fig. 4 is a schematic circuit diagram illustrating the configuration of a dual threshold MOS transistor; Figs. 5(a) and 5(b) are schematic circuit diagrams illustrating a dual threshold MOS transistor including a limiter device and an augmenting device respectively; and Fig. 6 is a schematic circuit diagram illustrating a Switch Module according to an exemplary embodiment of the present invention.

Using conventional NMOS pass transistor switches, due to the threshold drop while transmitting a logic high signal, there is short circuit dissipation in the buffers that follow. Stand-by leakage is also an issue in today's circuits. When a switch is turned off, the sub-threshold leakage current results in power dissipation. The present invention is intended to solve these problems. Using an appropriate configuration of the Dual Threshold MOS (hereinafter: DTMOS) based switch the best energy-delay product when the switch is on and the lowest leakage when the switch is in stand-by, can be achieved. First, the basic operation of a DTMOS switch will be explained. The threshold voltage of a transistor can be expressed as

Vτ = V_x + K ^V_sb + 2 _j (1)

Vπ - V_x + K j20_f (2)

The terms in these formulae are as follows. V_x is the process related constant threshold voltage term. Vw is the threshold voltage V_T at V_sb = 0V, K is a process parameter equal to

and is also known as the K-factor, N_A is the substrate dope

concentration, V_sb is the source-bulk voltage and 20_/ is the band bending where inversion first occurs. It can be seen from Eqn. 1 that we can vary the threshold voltage by varying the source bulk voltage. When a negative back bias voltage is applied to the bulk wrt the source, in the case of a NMOS transistor, the depletion region of the fictive channel substrate junction increases, and the voltage needed to create inversion also increases. Thus the threshold voltage increases. When the bulk source voltage is positive, the threshold voltage of the NMOS transistor reduces. The DTMOS transistor uses this basic principle. The DTMOS transistor in its basic form has the gate and the body terminals shorted as shown in Fig. 4. During the active mode of operation, when the gate voltage is positive, the body source junction has a forward bias. Since the body source voltage (Vbs) is positive, the threshold voltage reduces during the active mode of operation. When the gate voltage is zero (or the switch is not used), the body source voltage is zero and the DTMOS switch has a threshold equal to Vw shown in equation 2. This gives the DTMOS based switch an advantage over the conventional NMOS switch. During the active mode of operation when the gate voltage of the main transistor is high, its threshold voltage is reduced. This makes the DTMOS based switch faster than the NMOS based switch. It also has a higher current drive due to reduced V_T- In this work, we also tried some variations over this basic concept. For example, we make the main transistor (MT) a high V_T transistor. So during the active mode of operation, the high V_T is reduced due to the body-source forward bias and during stand-by when the body-source voltage is zero, the threshold voltage is equal to the intrinsic high V_T of the MT. This reduces the sub-threshold leakage power dissipation. The disadvantage of using the DTMOS in its basic form is that the gate voltage swing cannot exceed the cut-in voltage of the diode (0.5 V) otherwise a large current would flow through the forward biased body-source and body-drain junctions. The DTMOS with the limiting transistor works as follows. There are two NMOS transistors namely MT (main transistor) and LT (limiting transistor). The gate of the LT is connected to a reference voltage supply (VREF). So the voltage at the body of the MT never exceeds VREF- Vt. For the body source voltage not to exceed 0.5V, VREF should be appropriately chosen. For 0.13μ process, the nominal Vt is around 300mV, so VREF can range from 0.8V to 0.4V. This prevents the body source voltage from exceeding 0.5V at all times. The DTMOS with the augmenting transistor works as follows. The DTMOS with the augmenting switch contains two transistors namely MT (main transistor) and AT (augmenting transistor). When the gate voltage of the MT is high, and the source voltage is high, the voltage at the body of the MT cannot exceed VDD-Vt due to the Vt drop across the MT. So the body source voltage of the MT cannot exceed Vt (0.3V) which is less than the cut-in voltage (>0.5V) of the body source diode junction. So if the MT of the augmenting DTMOS switch is a high Vt transistor, then the body-source voltage is higher than when the MT is a nominal or a low Vt transistor. Thus the threshold voltage of the augmenting DTMOS switch with a high Vt MT is less than that of the same switch with a nominal or a low Vt MT. The current drive of the augmenting DTMOS switch with a high Vt MT is high and the delay is less, but as expected the power consumption is more. This is confirmed in our simulations as well. Thus, it can be seen that the basic DTMOS with the limiting or augmenting transistor enable it to be used for gate voltages higher than 0.5V. As explained above, conventional Switch Modules are made of either pass transistors or tri-state buffers as shown in Figs. 2 and 3. For the Switch Modules made of pass transistors, gate boosting or a restoring logic (positive feed-back) is used to overcome the V_t drop in the NMOS pass transistor. The pass transistors contribute to series resistance, capacitance and increase the delay of the signal. Gate-boosting needs a dedicated process technology. Tri-state buffer switches overcome the limitations of pass transistors but at the cost of a high increase in area. In addition, with shrinking process technologies, stand-by leakage is a major power consumer. Reducing stand-by leakage has not been addressed in the existing designs. The DTMOS-based switch with a limiter, as shown in Fig. 6 requires a reference voltage supply (VREF). If the reference voltage supply is to be avoided, a

DTMOS-based switch with an augmenting transistor may be used. Variations of the above- described embodiment of the invention include the following variations:

DTMOS with augmenting switch and its variations The DTMOS based switch with a limiter needs to have a reference voltage supply (VREF). If the reference voltage supply is to be avoided we can use a DTMOS based switch with an augmenting transistor. Augmenting Switch (A) In this variation, we use a nominal Vt augmented DTMOS with no sleep transistor. The "A" switch consumes more energy than the equivalent switch based on limiting transistor (L). The delay through the "A" switch is more since the augmenting transistor has some delay before the body source junction of the main transistor is forward biased, hence the overall energy consumed is more. The stand-by power dissipation of the "A" switch is also worse than the other switches. Augmenting Switch with High Vt Main Transistor (AHVT) As explained in the operation of the augmenting DTMOS switch, the threshold voltage during the active mode of this switch is lower than the A switch, thus resulting in a higher power consumption and lower delay after the body-source junction is slightly forward biased. Another factor which can contribute to this switch consuming more power is that, in the active mode, due to the high Vt MT, the delay through the MT increases which delays the forward biasing of the body source junction of the MT by the AT. This results in an increase in short circuit power dissipation of the buffer following the AHVT. Augmenting Switch with High Vt Main and Sleep Transistor (ASWHVT) A high Vt transistor in the augmented DTMOS switch with a high Vt sleep transistor is studied in this variation. The sleep transistor in the buffer increases the delay of this switch. The overall active energy consumed by this switch is more the other augmenting based DTMOS switches. But the leakage or stand-by dissipation is less. Augmenting Switch with High Vt Sleep Transistor (ASW)

This variation is similar to the ASWHVT but with a nominal Vt MT. Thus, the delay through this switch is less and the power consumed is also less than the ASWHVT. The overall energy consumed is less than ASWHVT. The power consumed is lesser than ASWHVT because of two reasons. Firstly, the overall threshold is more than the that of the ASWHVT, leading to lesser current drive and lower power consumption. Secondly, the time before which the MT is forward biased is less than the ASWHVT. DTMOS with Limiting Switch and its Variations The DTMOS with a limiting switch and its variations are on the whole faster than their counterparts of the DTMOS with augmenting switch and its variations. For example, the L switch is faster than the A switch, the LHVT is faster than the AHVT, the LSW is faster than the ASW and the LSWHVT is faster than the ASWHVT. The overall power consumed by the simulation set-up (including the buffer) for the DTMOS with limiting switches is lesser than that of the DTMOS with augmenting switches. This could be because the short circuit power dissipation through the buffer is lesser for the former than for the latter because the Vt drop through the former switch is lesser than the latter. The delay is less because the body source junction of the MT is forward biased faster than the augmenting based switches. Another reason why the delay is less is because the body source forward bias (which contributes to the reduction in the threshold voltage of the MT) in the augmenting based switches cannot exceed Vt, but in the limiting switch it is the difference between VDD and the reference voltage supply (VREF) and it is typically more than the threshold voltage Vt. In our case VREF = 0.8V. The limiting transistor (LT) has a dedicated reference supply VREF and the time taken for forward biasing the body-source junction of the MT is independent of the delay through the MT itself which was not the case for augmenting transistor based switches. The limiter transistor based switches have the disadvantage that an extra reference supply is needed. But if this can be afforded, then, the limiting transistor based DTMOS switches have the best energy Figures compared to the other variations in our experiments.

Limiting Switch (L) The L switch has the lowest power-delay product compared to all other switches but suffers from a higher stand-by power dissipation. Limiting Switch with High Vt Main Transistor (LHVT) As expected, the LHVT consumes more power and has a higher delay than the L switch due to the high Vt MT. The overall power-delay product is more than the L. Limiting Switch with High Vt Sleep Transistor (LSW) The LSW switch has a higher energy consumption than the L and LHVT switches but less than the LSWHVT. This is expected since the sleep transistor in the buffer increases the active energy consumption. But the stand-by power dissipation is less than L and LHVT but greater than LSWHVT. Limiting Switch with High Vt Main and Sleep Transistor (LSWHVT) The LSWHVT switch consumes the least power. The power-delay of the setup using this switch is only worse than L, LSW and LHVT. But the stand-by leakage is very less. Conventional NMOS or Complementary Pass Transistor Switches Due to the full Vt drop across an NMOS pass transistor switch, the power consumed is high. The NMOS based switch is quite fast due to reduced node capacitances compared to the other switches which need more than one transistor. The overall power-delay product of the NMOS switch is better than the ASW, AHVT and ASWHVT. But the ASW, AHVT and ASWHVT have a much better stand-by performance than the NMOS based switch. It is also possible to compare the DTMOS based switches and NMOS against a complementary pass transistor switch (shown as COMP in the Figures). It can be seen that the power-delay product of the set-up using the complementary pass transistor switch is only better than ASWHVT. But in stand-by it is worse than the others. The other disadvantage of the complementary switch is the large area that it occupies compared to the other switches. It needs four transistors in total(inclusive of the inverter needed for generating the control signal and its inverse which control the NMOS and PMOS transistor). Also in the DTMOS based switches the limiting or augmenting transistor (LT or AT) can be shared by more than one main transistor (MT). This means that by sharing the LT or AT, the DTMOS based switch needs only one transistor per switch. The complementary switch needs four transistors per switch, two of which can be perhaps shared with others but not the other two thus leading to an area overhead which is especially critical when there are many of these switches in a typical FPGA Power-Delay Product, Stand-by Dissipation, Area Trade-off It can be concluded that some switches are better or not depending on whether power, delay, power-delay, stand-by dissipation is the criterion. We can choose any of the switches based on the requirements that we have. Table 2 below shows the order of preference of the switches based on criterion according to an exemplary embodiment of the invention. For example, in the column entitled "Power", the power consumption of LSWHVT < LSW < LHVT < L ...< COMP, in the column entitled "Delay", the delay through L < LHVT < LSW < NMOS ... < ASWHVT. Similar trends are shown for Power-Delay with L having the least and ASWHVT having the largest Power-Delay product. LSWHVT has the least stand-by leakage and COMP has the highest stand-by leakage.

Table 2: Trade-offs in choosing the switch

It can be seen from the table that the switch based on the limiter with the main transistor high Vt and a sleep transistor in the buffer following the switch, LSWHVT, consumes the least power and the complementary switch, COMP, consumes the maximum power. Similarly, the switch based on the limiting transistor, L has the lowest delay and power-delay product whereas the switch based on the augmenting transistor with the main transistor high Vt and a sleep transistor in the buffer following the switch, ASWHVT has the highest delay and power-delay product. During stand-by the least power dissipation is of the LSWHVT switch and the maximum is of the complementary switch, COMP. This table helps to choose the switch needed depending on the constraints. For example, for high speed operation and for the best power-delay product, the L switch can be chosen. The LSW switch is slower than the L switch and has a slightly worse power-delay product but has lower standby dissipation. The NMOS switch is better in terms of the Power-Delay product than most of the augmenting based DTMOS switches except the A switch but is worse than all the DTMOS switches based on limiting transistors. The area overhead is another important issue to be considered since there are many switches in the programmable interconnect fabric of a FPGA. The complementary pass gate (COMP) has the largest area overhead since in addition to a PMOS and a NMOS, an inverter is needed for generating the control signal (which controls the switch) and its inverse. The NMOS switch has the least area. All the DTMOS switches based on augmenting or limiting transistor need two transistors per switch, but the limiting or augmenting transistor could be shared by more than one switch thus reducing the area overhead. For example, when datapath operations are being performed in a FPGA, the granularity of operation is higher. This involves a bus based communication between logic blocks. In one instance of this, when an eight bit addition is being performed, the eight bits of sum output and the carry signals need to be communicated to another block. This means that nine switches along the way from the source logic block to the destination logic block need to be switched on simultaneously. Only one augmenting or limiting transistor would then be needed for these nine switches. A proposed Switch Module according to an exemplary embodiment of the invention is as shown in Fig. 6, which embodiment is one variation of the various possible implementations intended to overcome some of the limitations of a conventional NMOS- based Switch Module. Each of the NMOS pass transistors is replaced by a DTMOS 900, with a limiter switch 100. In addition the buffers 700 following the switches have a sleep transistor 800 with a high threshold. The gate voltage of this sleep transistor 800 is controlled by the configuration signal. If the switch is not selected, the sleep transistor 800 is off, thus disconnecting the buffer 700 from the ground connection. This prevents leakage in standby. Conclusion It can be seen that the switch based on the limiter with the main transistor high Vt and a sleep transistor in the buffer following the switch, LSWHVT, consumes the least power and the complementary switch, COMP, consumes the maximum power. Similarly, the switch based on the limiting transistor, L has the lowest delay and power-delay product whereas the switch based on the augmenting transistor with the main transistor high Vt and a sleep transistor in the buffer following the switch, ASWHVT has the highest delay and power-delay product. During stand-by the least power dissipation is of the LSWHVT switch and the maximum is of the complementary switch, COMP. Table 2 helps to choose the switch needed depending on the constraints. For example, for high speed operation and for the best power-delay product, the L switch can be chosen. The LSW switch is slower than the L switch and has a slightly worse power-delay product but has lower stand-by dissipation. The NMOS switch is better in terms of the Power-Delay product than most of the augmenting based DTMOS switches except the A switch but is worse than all the DTMOS switches based on limiting transistors. The area overhead is another important issue to be considered since there are many switches in the programmable interconnect fabric of a FPGA. The complementary pass gate(COMP) has the largest area overhead since in addition to a PMOS and a NMOS, an inverter is needed for generating the control signal (which controls the switch) and its inverse. The NMOS switch has the least area. All the DTMOS switches based on augmenting or limiting transistor need two transistors per switch, but the limiting or augmenting transistor could be shared by more than one switch thus reducing the area overhead. For example, when datapath operations are being performed in a FPGA, the granularity of operation is higher. This involves a bus based communication between logic blocks. In one instance of this, when an eight bit addition is being performed, the eight bits of sum output and the carry signals need to be communicated to another block. This means that nine switches along the way from the source logic block to the destination logic block need to be switched on simultaneously. Only one augmenting or limiting transistor would then be needed for these nine switches. A 10-15% improvement per switch in the power-delay product, over the conventional NMOS pass transistor can be achieved, by using the limiter based dual threshold MOS transistor switch (could be L, LSW, LHVT or LSWHVT). Since the interconnect fabric in a FPGA is composed of many thousands of switches, the overall improvement in the power-delay product can be significant if limiter based dual threshold MOS switches are used. By sharing the limiter transistor, the area overhead is kept low (For example, one extra transistor for every 8 transistors). In stand-by, if the LSWHVT or LSW switch is used, a factor of 20 reduction in the leakage power is obtained compared to the NMOS pass transistor switch. For the other two limiter based Dual Threshold MOS switches, namely, L and LHVT, the leakage is comparable to the NMOS pass transistor switch. It should be noted that the above-mentioned embodiment illustrates rather than limits the invention, and that those skilled in the art will be capable of designing many alternative embodiments without departing from the scope of the invention as defined by the appended claims. In the claims, any reference signs placed in parentheses shall not be construed as limiting the claims. The word "comprising" and "comprises", and the like, does not exclude the presence of elements or steps other than those listed in any claim or the specification as a whole. The singular reference of an element does not exclude the plural reference of such elements and vice- versa. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

CLAIMS:

1. A Switch Module (600) for a field programmable logic circuit, the Switch Module (600) comprising one or more inputs, one or more outputs, and a set of programmable switches (900) between said one or more inputs and outputs, the Switch Module (600) being characterized in that at least one of said switches comprises a dual threshold MOS transistor (900) and means (100) for increasing the gate voltage at which said transistor can operate.

2. A Switch Module (600) according to claim 1, wherein the means (100) for increasing the gate voltage at which the transistor (900) can operate comprises an augmenting transistor.

3. A Switch Module (600) according to claim 1, wherein the means for increasing the gate voltage at which the transistor can operate comprises a limiting transistor (100).

4. A Switch Module (600) according to only one of claims 1 to 3, wherein the dual threshold has a relatively high or moderate threshold voltage.

5. A Switch Module (600) according to any one of claims 1 to 4, wherein one or more buffers (700) are provided at the one or more outputs of the Switch Module (600).

6. A Switch Module (600) according to claim 5, wherein the one or more buffers (700) include a sleep transistor (800).

7. A Switch Module (600) according to claim 6, wherein the sleep transistor

(800) has a relatively high threshold voltage.