WO2005013379A2 - Verfahren zur herstellung einer vielzahl von optoelektronischen halbleiterchips und optoelektronischer halbleiterchip - Google Patents
Verfahren zur herstellung einer vielzahl von optoelektronischen halbleiterchips und optoelektronischer halbleiterchip Download PDFInfo
- Publication number
- WO2005013379A2 WO2005013379A2 PCT/DE2004/001593 DE2004001593W WO2005013379A2 WO 2005013379 A2 WO2005013379 A2 WO 2005013379A2 DE 2004001593 W DE2004001593 W DE 2004001593W WO 2005013379 A2 WO2005013379 A2 WO 2005013379A2
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- WIPO (PCT)
- Prior art keywords
- semiconductor
- growth
- layer
- semiconductor layer
- semiconductor layers
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
- H01L21/02642—Mask materials other than SiO2 or SiN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- a large number of optoelectronic semiconductor chips each having a large number of structural elements, each with at least one semiconductor layer.
- Semiconductor layers of the structural elements are grown using selective epitaxy.
- the invention relates to an optoelectronic semiconductor chip produced by this method.
- Such an optoelectronic semiconductor chip and a corresponding method for its production are described, for example, in DE 199 11 717 AI.
- This has a plurality of radiation decoupling elements which, for. B. include an epitaxially grown semiconductor layer sequence with an electromagnetic layer generating active layer. As a result, this component has an improved coupling-out of radiation.
- Each of the radiation decoupling elements has a ring contact on a top surface, the ring contacts being connected to one another by electrically conductive webs. This is a relatively complex way of contacting the radiation decoupling elements in an electrically conductive manner and requires that they have a certain minimum size.
- the object of the present invention is to provide an improved method for producing optoelectronic semiconductor chips of the type mentioned at the outset.
- Another object of the present invention is to provide a semiconductor chip produced by such a method, which has improved properties compared to conventional semiconductor chips.
- the method for producing a multiplicity of optoelectronic semiconductor chips of the type mentioned at the beginning comprises at least the following method steps: providing a chip composite base which has a substrate and a growth surface;
- the chip composite base preferably has at least one semiconductor layer epitaxially grown on the substrate.
- the growth surface is a surface on the side of the epitaxially grown semiconductor layer facing away from the substrate.
- the chip composite base has an epitaxially grown semiconductor layer sequence, which comprises an active zone emitting electromagnetic radiation.
- the growth surface is a surface on the side of the semiconductor layer sequence facing away from the substrate.
- the semiconductor layers of the structural elements subsequently applied to the growth surface form a structuring which, for example, fulfills the purpose of improved coupling out of the electromagnetic radiation generated in the chip composite base.
- the structure elements each have an epitaxially grown semiconductor layer sequence an active zone that emits electromagnetic radiation.
- Preferred materials for the mask material layer have Si0 2 , Si x N y or Al 2 0 3 .
- a layer of electrically conductive contact material is preferably applied to them, which is transparent to electromagnetic radiation emitted by the active zone, so that semiconductor layers of a plurality of structural elements are electrically conductively connected to one another by the contact material.
- electrical contact structures can be formed in a simple manner, through which a small proportion of electromagnetic radiation generated in the component is also absorbed.
- the mask material layer is expediently at least partially removed after the semiconductor layers have been grown.
- a planarization layer is advantageously applied as an alternative or in addition to removing mask material, over the growth surface.
- this can lead to an improved coupling out of light if a material is selected for it whose refractive index is smaller than that of adjacent semiconductor layers.
- the mask material layer and the semiconductor layers are particularly preferably grown by means of organometallic gas phase epitaxy (MOVPE).
- MOVPE organometallic gas phase epitaxy
- the optoelectronic semiconductor chip is distinguished by the fact that it is produced by the method according to the invention or an embodiment thereof.
- Figures la to ld a schematic plan view of a section of a growth surface during various stages of an embodiment of the method
- Figure 2 is a schematic sectional view of a section of a first embodiment of the optoelectronic component
- Figure 3 is a schematic sectional view of a section of a second embodiment of the optoelectronic component.
- the same or equivalent components are each provided with the same reference numerals.
- the components shown and the proportions of the components among one another are not to be regarded as true to scale. Rather, some details of the figures are exaggerated for better understanding.
- FIGS. 1 A detail of a growth surface 3 during the growth of a mask material layer 11 from a mask material 1 is shown in chronological sequence in FIGS.
- the mask material layer 11 is grown in situ in a non-closed layer in such a way that a large number of statistically distributed windows are created. "In situ" means that the growth takes place in the same epitaxial reactor as the growth of semiconductor layers of the component.
- a closed mask material layer can also be grown, in which windows are subsequently formed by means of photolithography and etching.
- the growth surface 3 can be, for example, a surface of a substrate made of n-GaAs, the mask material 1 consists, for example, of Si x N y .
- the growth of the mask material 1 begins at isolated points on the axle surface 3, at which crystallites from the mask material 1 form.
- the crystallites from mask material 1 laterally grow together (see
- the growth conditions being able to be set, for example, in such a way that two-dimensional growth predominates, ie that the crystallites are made core material 1 mainly grow in a plane parallel to the growth surface and only to a lesser extent perpendicular to it.
- the growth conditions predominantly three-dimensional growth of the crystallites can also be achieved, ie growth in which the growth rate in all possible directions of growth is of a similar size or of the same order of magnitude.
- externally adjustable, controllable or changeable parameters such as e.g. Understand pressure, temperature, material flow and duration of growth in the epitaxial reactor.
- the exact values for such parameters in order to achieve a specific growth characteristic can vary widely and depend, for example, on the division and the geometric dimensions of the epitaxial reactor or on the material to be grown.
- the growth conditions not only the shape or the size of the windows can be varied when the mask material layer is growing, but also the surface density with which the windows are produced on the growth surface can advantageously be set, for example.
- a non-closed Si x N y layer is produced, for example, in a MOVPE reactor by switching on SiH 4 and NH 3 at a suitable reactor temperature, which can typically be in a range between 500 and 1100 ° C. However, the reactor temperature can also be above or below this range.
- a suitable reactor temperature can typically be in a range between 500 and 1100 ° C.
- the reactor temperature can also be above or below this range.
- Such methods are described, for example, in Hageman, PR et al, phys. stat. sol. (a) 188, no. 2 (2001), 659-662, the content of which is hereby described by Back reference is included.
- tetraethyl silicon (Si (C 2 H 5 ) 4 ) or a similar Si-containing compound which is suitable for epitaxy can also be used as the Si source.
- Semiconductor layer sequences 8 are subsequently selectively deposited on regions of the growth surface 3 lying within these windows 2 (see FIG. 2 or 3).
- These can be based on phosphide compound semiconductors, for example, and preferably have materials In n Ga m Ali- n - m P, where O n n l l, O m m l l and n + m ⁇ 1 or have multiple dopants and additional components that essentially do not change the physical properties of the material.
- a semiconductor layer sequence 8 forms a structure element 12.
- semiconductor layers of a plurality of structure elements overlap or that a number of structure elements have at least one common semiconductor layer. This is the case, for example, when semiconductor layer sequences 8 grow so far laterally over the mask material layer that semiconductor layers of adjacent structural elements 12 are partially or completely together. to grow. In such cases, a boundary between two adjacent structural elements runs along a line along which the semiconductor material located on the mask material layer has a minimal thickness.
- the semiconductor layer sequence 8 forming the structure element 12 has an active zone which emits electromagnetic radiation when current is applied.
- a structural element 12 can also have no active zone and e.g. be formed from only one semiconductor layer which has a lens-like shape.
- the active zone can have a conventional pn junction, for example for a luminescence diode.
- a luminescence diode Such structures are known to the person skilled in the art and are therefore not explained in more detail here.
- the windows have differently sized opening areas results in 8 different material compositions for the layers of the semiconductor layer sequences deposited therein. Structures emitting electromagnetic radiation thus result in different emission spectra, so that overall a broader emission spectrum can be achieved with such radiation-emitting components than with conventional components.
- FIG. 2 shows a schematic sectional view of a section of an optoelectronic component produced using the method.
- the chip composite base 5 comprises a substrate 4 and a semiconductor layer or semiconductor layer sequence 6 grown epitaxially on this substrate, the side of which facing away from the substrate 4 forms the growth surface 3.
- On the growth surface 3 is one Mask material layer 11 grown in the shown
- Section of the component has a window into which one
- Semiconductor layer sequence 8 is selectively deposited.
- the maximum thickness of the mask material layer 11 can e.g. is only a few nm and is less than the height of the semiconductor layer sequence 8.
- semiconductor layers of the semiconductor layer sequence 8 are also partially grown above the mask material layer 11 from a height that is greater than the thickness of the mask material layer 11 surrounding them.
- the growth conditions for growing the semiconductor layer sequence 8 are e.g. selected in such a way or varied during the growth that the semiconductor layer sequence 8 is formed with a lens-like shape.
- this shape can also be frustoconical or polyhedral.
- wax-up conditions is to be understood in a similar way to the previously described wax-up of mask material 1.
- the type of semiconductor material to be grown and the type of epitaxial system it also depends heavily on the type of mask material 1 and how exactly the setting of certain values is for parameters such as pressure, temperature, material flow and growth duration affects the growth of semiconductor materials.
- Suitable contact material 7 is, for example, indium tin oxide (ITO) or a metal layer a few atoms thick, for example made of platinum, which, due to its small thickness, is suitable for one of the active zones of the
- a contact material with ITO can additionally have such a thin metal layer which is deposited before the ITO.
- the electrical conductivity of the contact between contact material 7 and semiconductor layer sequence 8 can thereby be improved.
- a bond pad can be applied to the contact material 7 before or after the annealing, via which the semiconductor layer sequence, e.g. can be contacted by means of a bonding wire (not shown).
- the substrate 4 is provided on the rear side, ie on the side facing away from the growth surface, with a contact material and is connected in an electrically conductive manner, then a voltage can be applied to the components still in the bond and their functionality via the bond pad and the rear side contact test (direct probing).
- the semiconductor layer sequence 6 arranged on the substrate 4 can also have an active zone that emits electromagnetic radiation. When a voltage is applied to the component, the current through the mask material layer 11 is restricted to a region of the windows 2, so that a light generation region is essentially restricted to a part of the active zone of the semiconductor layer sequence 6 that lies below a window 2.
- a planarization layer 10 is applied to the growth surface 3 and the semiconductor layer sequence 8, which e.g. can consist of a dielectric whose refractive index is smaller than that of materials of the semiconductor layer sequence 8.
- the planarization layer 10 is subsequently at least partially thinned or removed, so that the outermost layer of the semiconductor layer sequence 8 is exposed.
- electrically conductive contact material 7 is applied and annealed analogously to the exemplary embodiment explained with reference to FIG. 2.
- the chip composite base 5 with the applied material can subsequently be separated into a multiplicity of optoelectronic semiconductor chips. Each of these semiconductor chips comprises a multiplicity of structural elements 12.
- the scope of the invention is not limited by the description of the invention based on the exemplary embodiments.
- the windows in the mask material layer can be made so small that quasi one-dimensional semiconductor component structures are grown in them.
- the invention encompasses every new feature and every combination of features, which includes in particular every combination of features in the patent claims, even if this combination is not explicitly specified in the patent claims.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/566,955 US8017416B2 (en) | 2003-07-31 | 2004-07-22 | Method for the production of a plurality of opto-electronic semiconductor chips and opto-electronic semiconductor chip |
JP2006521387A JP2007500934A (ja) | 2003-07-31 | 2004-07-22 | 複数のオプトエレクトロニクス半導体チップの製造方法およびオプトエレクトロニクス半導体チップ |
EP20040762443 EP1649497B1 (de) | 2003-07-31 | 2004-07-22 | Verfahren zur herstellung einer vielzahl von optoelektronischen halbleiterchips und optoelektronischer halbleiterchip |
KR1020067001846A KR101148632B1 (ko) | 2003-07-31 | 2004-07-22 | 다수의 광전자 반도체 칩을 제조하는 방법 및 광전자반도체 칩 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10335080A DE10335080A1 (de) | 2003-07-31 | 2003-07-31 | Verfahren zur Herstellung einer Vielzahl von optoelektronischen Halbleiterchips und optoelektronischer Halbleiterchip |
DE10335080.2 | 2003-07-31 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2005013379A2 true WO2005013379A2 (de) | 2005-02-10 |
WO2005013379A3 WO2005013379A3 (de) | 2005-03-31 |
Family
ID=34111795
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2004/001593 WO2005013379A2 (de) | 2003-07-31 | 2004-07-22 | Verfahren zur herstellung einer vielzahl von optoelektronischen halbleiterchips und optoelektronischer halbleiterchip |
Country Status (8)
Country | Link |
---|---|
US (1) | US8017416B2 (de) |
EP (1) | EP1649497B1 (de) |
JP (1) | JP2007500934A (de) |
KR (1) | KR101148632B1 (de) |
CN (1) | CN100444322C (de) |
DE (1) | DE10335080A1 (de) |
TW (1) | TWI250667B (de) |
WO (1) | WO2005013379A2 (de) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10335080A1 (de) | 2003-07-31 | 2005-03-03 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung einer Vielzahl von optoelektronischen Halbleiterchips und optoelektronischer Halbleiterchip |
Citations (3)
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EP0472221A2 (de) | 1990-08-24 | 1992-02-26 | Nec Corporation | Verfahren zur Herstellung einer optischen Halbleitervorrichtung |
DE19911717A1 (de) | 1999-03-16 | 2000-09-28 | Osram Opto Semiconductors Gmbh | Monolithisches elektrolumineszierendes Bauelement und Verfahren zu dessen Herstellung |
DE10335080A1 (de) | 2003-07-31 | 2005-03-03 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung einer Vielzahl von optoelektronischen Halbleiterchips und optoelektronischer Halbleiterchip |
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JPH0262090A (ja) * | 1988-08-29 | 1990-03-01 | Matsushita Electric Ind Co Ltd | 光半導体装置の製造方法 |
JPH02237021A (ja) * | 1989-03-09 | 1990-09-19 | Fujitsu Ltd | 半導体装置の製造方法 |
DE69127952T2 (de) * | 1990-11-07 | 1998-03-05 | Canon Kk | III-V Verbindungs-Halbleiter-Vorrichtung, Drucker- und Anzeigevorrichtung unter Verwendung derselben, und Verfahren zur Herstellung dieser Vorrichtung |
JPH05226781A (ja) * | 1992-02-12 | 1993-09-03 | Fujitsu Ltd | 半導体発光素子の製造方法 |
GB2295269A (en) * | 1994-11-14 | 1996-05-22 | Sharp Kk | Resonant cavity laser having oxide spacer region |
US5693962A (en) * | 1995-03-22 | 1997-12-02 | Motorola | Full color organic light emitting diode array |
WO1997011518A1 (en) * | 1995-09-18 | 1997-03-27 | Hitachi, Ltd. | Semiconductor material, method of producing the semiconductor material, and semiconductor device |
DE19535777A1 (de) | 1995-09-26 | 1997-03-27 | Siemens Ag | Optoelektronisches Halbleiter-Bauelement und Verfahren zur Herstellung |
DE19715572A1 (de) * | 1997-04-15 | 1998-10-22 | Telefunken Microelectron | Verfahren zum Herstellen von epitaktischen Schichten eines Verbindungshalbleiters auf einkristallinem Silizium und daraus hergestellte Leuchtdiode |
TW393785B (en) * | 1997-09-19 | 2000-06-11 | Siemens Ag | Method to produce many semiconductor-bodies |
JPH11330548A (ja) * | 1998-05-15 | 1999-11-30 | Showa Denko Kk | Iii−v族窒化物半導体発光素子及びその製造方法 |
US6255198B1 (en) * | 1998-11-24 | 2001-07-03 | North Carolina State University | Methods of fabricating gallium nitride microelectronic layers on silicon layers and gallium nitride microelectronic structures formed thereby |
JP3470623B2 (ja) * | 1998-11-26 | 2003-11-25 | ソニー株式会社 | 窒化物系iii−v族化合物半導体の成長方法、半導体装置の製造方法および半導体装置 |
JP2001284641A (ja) * | 2000-03-31 | 2001-10-12 | Sony Corp | 画像表示素子 |
JP3882539B2 (ja) * | 2000-07-18 | 2007-02-21 | ソニー株式会社 | 半導体発光素子およびその製造方法、並びに画像表示装置 |
WO2002017369A1 (en) | 2000-08-18 | 2002-02-28 | Showa Denko K.K. | Method of fabricating group-iii nitride semiconductor crystal, metho of fabricating gallium nitride-based compound semiconductor, gallium nitride-based compound semiconductor, gallium nitride-based compound semiconductor light-emitting device, and light source using the semiconductor light-emitting device |
JP4724924B2 (ja) * | 2001-02-08 | 2011-07-13 | ソニー株式会社 | 表示装置の製造方法 |
JP2002249400A (ja) * | 2001-02-22 | 2002-09-06 | Mitsubishi Chemicals Corp | 化合物半導体単結晶の製造方法およびその利用 |
JP3690340B2 (ja) * | 2001-03-06 | 2005-08-31 | ソニー株式会社 | 半導体発光素子及びその製造方法 |
JP3697406B2 (ja) * | 2001-09-26 | 2005-09-21 | 株式会社東芝 | 半導体発光装置及びその製造方法 |
EP1436870A2 (de) | 2001-10-09 | 2004-07-14 | Infinera Corporation | Integrierte fotonische sendschaltung und optisches netzwerk damit |
JP2003158296A (ja) * | 2001-11-22 | 2003-05-30 | Sharp Corp | 窒化物半導体発光デバイスチップとその製造方法 |
TW561526B (en) | 2001-12-21 | 2003-11-11 | Aixtron Ag | Method for depositing III-V semiconductor layers on a non-III-V substrate |
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-
2003
- 2003-07-31 DE DE10335080A patent/DE10335080A1/de not_active Withdrawn
-
2004
- 2004-07-22 CN CNB2004800221598A patent/CN100444322C/zh not_active Expired - Fee Related
- 2004-07-22 US US10/566,955 patent/US8017416B2/en not_active Expired - Fee Related
- 2004-07-22 JP JP2006521387A patent/JP2007500934A/ja active Pending
- 2004-07-22 WO PCT/DE2004/001593 patent/WO2005013379A2/de active Application Filing
- 2004-07-22 KR KR1020067001846A patent/KR101148632B1/ko not_active IP Right Cessation
- 2004-07-22 EP EP20040762443 patent/EP1649497B1/de not_active Expired - Fee Related
- 2004-07-28 TW TW093122483A patent/TWI250667B/zh not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0472221A2 (de) | 1990-08-24 | 1992-02-26 | Nec Corporation | Verfahren zur Herstellung einer optischen Halbleitervorrichtung |
DE19911717A1 (de) | 1999-03-16 | 2000-09-28 | Osram Opto Semiconductors Gmbh | Monolithisches elektrolumineszierendes Bauelement und Verfahren zu dessen Herstellung |
DE10335080A1 (de) | 2003-07-31 | 2005-03-03 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung einer Vielzahl von optoelektronischen Halbleiterchips und optoelektronischer Halbleiterchip |
Non-Patent Citations (2)
Title |
---|
HAGEMAN, P. R. ET AL., PHYS. STAT. SOL. (A), vol. 188, no. 2, 2001, pages 659 - 662 |
J. W. YANG ET AL.: "Selective Area deposited blue GaN-InGaN multiple-quantum well light emitting diodes over silicon substrates", APPLIED PHYSICS LETTERS, vol. 76, no. 3, 17 January 2000 (2000-01-17), pages 273 - 275, XP012025677, DOI: doi:10.1063/1.125745 |
Also Published As
Publication number | Publication date |
---|---|
CN1830066A (zh) | 2006-09-06 |
EP1649497B1 (de) | 2015-04-29 |
US8017416B2 (en) | 2011-09-13 |
JP2007500934A (ja) | 2007-01-18 |
EP1649497A2 (de) | 2006-04-26 |
DE10335080A1 (de) | 2005-03-03 |
TW200507304A (en) | 2005-02-16 |
KR20060056350A (ko) | 2006-05-24 |
KR101148632B1 (ko) | 2012-05-23 |
WO2005013379A3 (de) | 2005-03-31 |
US20070034880A1 (en) | 2007-02-15 |
CN100444322C (zh) | 2008-12-17 |
TWI250667B (en) | 2006-03-01 |
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