WO2005013324A3 - Memory access via serial memory interface - Google Patents

Memory access via serial memory interface Download PDF

Info

Publication number
WO2005013324A3
WO2005013324A3 PCT/US2004/023298 US2004023298W WO2005013324A3 WO 2005013324 A3 WO2005013324 A3 WO 2005013324A3 US 2004023298 W US2004023298 W US 2004023298W WO 2005013324 A3 WO2005013324 A3 WO 2005013324A3
Authority
WO
WIPO (PCT)
Prior art keywords
access via
via serial
memory
interface
memory interface
Prior art date
Application number
PCT/US2004/023298
Other languages
French (fr)
Other versions
WO2005013324A2 (en
Inventor
Fulong Zhang
Hal Scholz
Zheng Chen
Original Assignee
Lattice Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lattice Semiconductor Corp filed Critical Lattice Semiconductor Corp
Publication of WO2005013324A2 publication Critical patent/WO2005013324A2/en
Publication of WO2005013324A3 publication Critical patent/WO2005013324A3/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17756—Structural details of configuration resources for partial configuration or partial reconfiguration
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories

Abstract

Systems and methods are disclosed herein to provide access to memory cells within a programmable logic device. For example, in accordance with an embodiment of the present invention, a serial memory interface is associated with each special functional block within a programmable logic device to provide access to configuration memory cells of the special functional block.
PCT/US2004/023298 2003-07-29 2004-07-16 Memory access via serial memory interface WO2005013324A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/629,512 2003-07-29
US10/629,512 US6903574B2 (en) 2003-07-29 2003-07-29 Memory access via serial memory interface

Publications (2)

Publication Number Publication Date
WO2005013324A2 WO2005013324A2 (en) 2005-02-10
WO2005013324A3 true WO2005013324A3 (en) 2005-06-02

Family

ID=34103644

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/023298 WO2005013324A2 (en) 2003-07-29 2004-07-16 Memory access via serial memory interface

Country Status (2)

Country Link
US (1) US6903574B2 (en)
WO (1) WO2005013324A2 (en)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7095247B1 (en) * 2004-03-25 2006-08-22 Lattice Semiconductor Corporation Configuring FPGAs and the like using one or more serial memory devices
DE102004031715B4 (en) * 2004-06-30 2013-05-29 Globalfoundries Inc. Combined on-chip command and response data interface
US7589648B1 (en) 2005-02-10 2009-09-15 Lattice Semiconductor Corporation Data decompression
US7640526B1 (en) * 2005-09-12 2009-12-29 Xilinx, Inc. Modular partial reconfiguration
US7590207B1 (en) * 2005-10-20 2009-09-15 Altera Corporation Modular serial interface in programmable logic device
US7554357B2 (en) * 2006-02-03 2009-06-30 Lattice Semiconductor Corporation Efficient configuration of daisy-chained programmable logic devices
US7378873B1 (en) 2006-06-02 2008-05-27 Lattice Semiconductor Corporation Programmable logic device providing a serial peripheral interface
US7570078B1 (en) 2006-06-02 2009-08-04 Lattice Semiconductor Corporation Programmable logic device providing serial peripheral interfaces
US7495970B1 (en) * 2006-06-02 2009-02-24 Lattice Semiconductor Corporation Flexible memory architectures for programmable logic devices
US7521969B2 (en) * 2006-07-28 2009-04-21 Lattice Semiconductor Corporation Switch sequencing circuit systems and methods
US7456672B1 (en) 2006-09-11 2008-11-25 Lattice Semiconductor Corporation Clock systems and methods
US7511641B1 (en) 2006-09-19 2009-03-31 Lattice Semiconductor Corporation Efficient bitstream compression
US8984249B2 (en) * 2006-12-20 2015-03-17 Novachips Canada Inc. ID generation apparatus and method for serially interconnected devices
US8132040B1 (en) 2007-10-25 2012-03-06 Lattice Semiconductor Corporation Channel-to-channel deskew systems and methods
US7902865B1 (en) 2007-11-15 2011-03-08 Lattice Semiconductor Corporation Compression and decompression of configuration data using repeated data frames
US7890917B1 (en) * 2008-01-14 2011-02-15 Xilinx, Inc. Method and apparatus for providing secure intellectual property cores for a programmable logic device
US8742791B1 (en) * 2009-01-31 2014-06-03 Xilinx, Inc. Method and apparatus for preamble detection for a control signal
US8255733B1 (en) 2009-07-30 2012-08-28 Lattice Semiconductor Corporation Clock delay and skew control systems and methods
US9465903B1 (en) * 2014-11-18 2016-10-11 Xilinx, Inc. Programmable IC design creation using circuit board data

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE37195E1 (en) * 1995-05-02 2001-05-29 Xilinx, Inc. Programmable switch for FPGA input/output signals
US6255848B1 (en) * 1999-04-05 2001-07-03 Xilinx, Inc. Method and structure for reading, modifying and writing selected configuration memory cells of an FPGA
US6675306B1 (en) * 2000-03-10 2004-01-06 Ricoh Company Ltd. Method and apparatus for phase-lock in a field programmable gate array (FPGA)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6535043B2 (en) * 2000-05-26 2003-03-18 Lattice Semiconductor Corp Clock signal selection system, method of generating a clock signal and programmable clock manager including same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE37195E1 (en) * 1995-05-02 2001-05-29 Xilinx, Inc. Programmable switch for FPGA input/output signals
US6255848B1 (en) * 1999-04-05 2001-07-03 Xilinx, Inc. Method and structure for reading, modifying and writing selected configuration memory cells of an FPGA
US6675306B1 (en) * 2000-03-10 2004-01-06 Ricoh Company Ltd. Method and apparatus for phase-lock in a field programmable gate array (FPGA)

Also Published As

Publication number Publication date
WO2005013324A2 (en) 2005-02-10
US6903574B2 (en) 2005-06-07
US20050024085A1 (en) 2005-02-03

Similar Documents

Publication Publication Date Title
WO2005013324A3 (en) Memory access via serial memory interface
AU2003245588A1 (en) Multiple-mode memory and method for forming same
AU2003301094A1 (en) Nanoelectromechanical memory cells and data storage devices
GB2411320B (en) Access control management method, access control management system, and terminal device with access control management function
AU2002338242A1 (en) Memory cell arrays and method for the production thereof
AU2003284727A1 (en) Downlink signal configuring method and device in mobile communication system, and synchronization and cell searching method and device using the same
AU2003263748A8 (en) Nrom memory cell, memory array, related devices and methods
AU2003265853A1 (en) Hedgehog antagonists, methods and uses related thereto
WO2004049175A3 (en) External memory controller node
EP1638266A4 (en) Data communication system, communication device, and communication program thereof
GB0218354D0 (en) Window-based flash memory storage system and management and access methods thereof
AU2003246278A1 (en) Production plan creation system, method, and program
AU2002324971A1 (en) Integrated systems for use with fuel cells, and methods
SG127695A1 (en) Method, adapter card and arrangement for the inst allation of memory modules
AU2003258217A1 (en) Devices, methods and systems for low volume microarray processing
GB2399899B (en) Active memory command engine and method
AU2003293923A1 (en) Fin field effect transistor memory cell, fin field effect transistor memory cell arrangement, and method for the production of a fin field effect transistor memory cell
EP1830240A4 (en) Memory information protecting system, semiconductor memory, and method for protecting memory information
WO2004042359A3 (en) Preformulation analysis and optimization
AU2001285316A1 (en) Methods and systems for integrating marketing, production, and finance
AU2003239449A1 (en) System and method with environment memory for input/output configuration
EP1705740A4 (en) Fuel for fuel cell, fuel cell and application thereof
EP1657636A4 (en) Program generation system, program generation program, and program generation module
AU2003259191A1 (en) Method, system, and program for memory based data transfer
ITBL20020015A1 (en) ELASTICIZED HINGE WITH LOCKED AND OCCULTED PIN, PARTICULARLY FOR GLASSES.

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase