WO2005006372A1 - Noble metal contacts for micro-electromechanical switches - Google Patents
Noble metal contacts for micro-electromechanical switches Download PDFInfo
- Publication number
- WO2005006372A1 WO2005006372A1 PCT/EP2004/050940 EP2004050940W WO2005006372A1 WO 2005006372 A1 WO2005006372 A1 WO 2005006372A1 EP 2004050940 W EP2004050940 W EP 2004050940W WO 2005006372 A1 WO2005006372 A1 WO 2005006372A1
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- WO
- WIPO (PCT)
- Prior art keywords
- electrode
- contact
- switch
- recited
- cavity
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H59/00—Electrostatic relays; Electro-adhesion relays
- H01H59/0009—Electrostatic relays; Electro-adhesion relays making use of micromechanics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H1/00—Contacts
- H01H1/02—Contacts characterised by the material thereof
- H01H1/021—Composite material
- H01H1/023—Composite material having a noble metal as the basic material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H1/00—Contacts
- H01H1/0036—Switches making use of microelectromechanical systems [MEMS]
- H01H2001/0052—Special contact materials used for MEMS
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49204—Contact or terminal manufacturing
Definitions
- MEMS Micro-electromechanical system
- MEMS is an enabling technology for miniaturization and offers the potential to integrate on a single die the majority of the wireless transceiver components, as described by a paper by D.E. Seeger, et al., presented at the SPIE 27th Annual International Symposium on Microlithograph , March 3-8, 2002, Santa Clara, GA- entifed Tabricatton Challenges for Next Generation Devices: M ⁇ MS for RF Wireless Communications *3 .
- a micro-electromechanical system (MEMS) switch is a transceiver passive device that uses electrostatic actuation to create movement of a movable beam or membrane that provides an ohmic contact (i.e. the RF signal is allowed to pass-through) or a change in capacitance by which the flow of signal is interrupted and typically grounded.
- MEMS micro-electromechanical system
- Competing technologies for MEMS switches include p-i-n diodes and
- GaAs FET switches These, typically, have high power consumption rates, MEMS applications", Solid-State Sensor and Actuator Workshop, 246 - 249, (2000).
- Switch failure at hot switching reported to be due to contact resistance increase and contact seizure as described by P.M. Zavracky et al. in the papers “Micromechanical switches fabricated using nickel surface micromachining”, J. MEMS, 6, 3-9, (1997) and “Microswitches and microrelays with a view toward microwave applications", Int. J. RF Microwave Comp. Aid. Eng., 9, 338 - 347, (1999). Therein are reported an increased contact resistance and contact seizure, both of which can be associated with material transfer and arcing/welding.
- the contamination build up caused switch failure is less likely than when exposed to ambient conditions.
- increases in contact resistance and/or contact seizure are both due to adhesion at the metal-metal contact.
- the increase in contact resistance most likely has to do with material transfer caused by surface roughening and results in reduced contact area. In the latter case the two metal surfaces are firmly adhered due to metal-metal bond formation (welding) at the interface.
- the invention described herein is a method of fabrication of a metal-metal switch with long lifetime and with stable and low contact resistance.
- the main thrust for reducing adhesion while gaining adequate contact resistance is:
- the contact metallurgy is selected not only from the group of Au, Pt, Pd as in U.S. Patent No. 5,578,976, but also from Ni, Co, Ru, Rh, Ir, Re, Os and their alloys in such a manner that it can be integrated with copper and insulator structures.
- Hard contact metals have lower contact adhesion.
- hardness of a metal can be changed by alloying.
- Au has low reactivity, but is soft and can result in contacts that adhere strongly. For instance, to avoid this problem, gold can be alloyed. Adding about 0.5% Co to Au increases the gold hardness from about 0.8GPa to about 2.1GPa.
- hard metals such as ruthenium and rhodium are used as switch contacts in this invention.
- Dual layers such as rhodium coated with ruthenium, with increasing melting point are used to prevent contact failure during arcing where high temperatures develop locally at the contacts. Disclosure of Invention
- Figs, la - are schematic diagrams of a cross-section of a first embodiment of the invention illustrating the process steps detailing the formation of a raised noble contact fabricated by blanket noble deposition and chemical mechanical planarization.
- FIGs. 2a-2f are schematic diagrams of a cross-section of a second embodiment of the invention illustrating the process steps detailing the formation of a raised electrode fabricated by selective electroplating of the noble contact.
- Figs. 3a-3e are schematic diagrams of a cross-section of the MEMs switch illustrating a third embodiment of the invention for filling the electrodes of the first metal level with a noble metal using Damascene process.
- Figs.4a-4d are schematic diagrams of a cross-section of the MEMs switch illustrating the process steps for filling the first metal level electrodes with electroplated blanket copper metal and planarization stopping at the TaNTa barrier film.
- Figs. 5a-5f are schematic diagrams of a cross-section of the MEMs showing the formation of the upper contact of the switch.
- Figs. ⁇ a-6e are schematic diagrams showing a cross-section of the MEMs representing the process sequence for creating the upper switch contact using electroplating through a photoresist mask.
- Figs. 7a-7f are schematic diagrams showing cross-sections of the MEMs representing the process sequence to complete the device after the upper switch contact has been formed. Best Mode for Carrying Out the Invention
- a raised noble contact is formed by a blanket noble metal deposition and chemical mechanical planarization.
- a copper Damascene level is first embedded in silicon dioxide.
- the copper electrodes (11, 12, 13, and 14) are capped by a silicon nitride layer (10), typically, 500-1000 A thick.
- Silicon oxide layer (20) having, preferably, a thickness of 1000-2000 A is deposited thereon, is shown in Figure la.
- Etching, preferably by way of photoHthography and RTE (reactive ion etching) forms a contact pattern (15) into the oxide (20) and nitride layers (10) exposing copper (12), as shown in Figure lb.
- a thin barrier layer is deposited by PVD, (physical vapor deposition) or CVD (chemical vapor deposition) such as Ta, TaN, W or dual layers, such as TaTaN, typically 50 - 700 A thick (30, Figure lc).
- a blanket noble metal is deposited by PVD, CVD, or electroplating (40, Figure lc).
- the noble metal is shaped by a chemical-mechanical planarization process (CMP) stopping at the barrier metal Ta, TaN, W (30, Figure Id).
- CMP chemical-mechanical planarization process
- Noble metals that can be shaped by chemical-mechanical planarization include Ru, Rh, Ir, Pt, and Re.
- CMP chemical-mechanical planarization
- the barrier metal (30) is removed in the field area by CMP stopping on silicon dioxide as shown in Figure le.
- Silicon oxide (20) is removed by reactive ion etching stopping on silicon nitride (10) to yield a raised noble metal lower electrode (50, Figure If).
- the raised electrode is formed by selective electroplating the noble contact. Selective electrolytic plating in the presence of a barrier layer has been discussed in U.S. Patent No. 6,368, 484 to Volant et al. and, more specifically, the selective electro-deposition of copper in Damascene features.
- a raised noble metal contact is formed by selective electrodeposition through a mask.
- FIG. 2a shows that the process is initiated by way of a Damascene level that includes lower actuation electrodes (11, 13) and lower radio frequency (RF) signal electrode (12) shown in the middle of the structure, on top of which the raised noble contact is formed. All lower electrodes are capped by silicon nitride (10) and silicon dioxide (20). Referring now to Figure 2b, the silicon dioxide (20) is patterned and etched by RIE leaving the copper of the middle electrode (12) exposed. A set of refractory metal barriers such as Ta, TaN, W (30) and a seed layer are then deposited by PVD or CVD methods. The thin seed layer (35) is then removed in the field area by CMP or ion milling, as shown in Figure 2d.
- RF radio frequency
- a subsequent short chemical etch step is needed to ensure that very thin layers of metal and/ or metal islands are not present on top of TaN Ta (30) in the field area.
- the barrier film with Ta/TaN is used to pass an electric current and is followed by a selective electrodeposition in the recess containing the seed layer (35) of noble metal such as Au, AuNi, AuCo, Pd, PdNi, PdCo, Ru, Rh, Os, Pt, PtTi, Ir (45).
- the selective electrodeposition does not nucleate on the refractory Ta or TaN (30) but will only nucleate on the noble seed layer (35), as shown in Figure 2e.
- the Ta/TaN (30) barrier is removed by CMP in the presence of the noble contact.
- the raised contact (50) is formed by etching (RTE) the silicon oxide layer (20) down to the silicon nitride ( Figure 2f).
- RTE etching
- Figure 2f silicon nitride
- the electrodes of the first metal level are filled with noble metal using a Damascene process.
- Figure 3 shows the process sequence starting with a Si wafer (1), adding a silicon oxide layer (2), patterning the silicon oxide layer (2) to form the lower actuation electrodes (3, 5) and the signal electrode (4), depositing a barrier layer by CVD or PVD methods such as TaN/Ta (6), depositing a noble metal seed layer by CVD or PVD (7) and finally blanket depositing by PVD, CVD or electroplating the noble metal (8) to fill the Damascene structures (3, 4, 5), planarizing the noble metal (8) by CMP to expose the barrier film (7) and finally removing the barrier film (7) from the field area by CMP resulting in lower switch electrodes (11, 12, 13, 14) filled by noble metal.
- the first metal level electrodes (11, 12, 13, and 14) are filled with electroplated blanket copper metal and planarized, stopping at the barrier film TaN Ta (7).
- the copper is recessed by chemical etching in the presence of the barrier layer TaN/Ta (7).
- This layer is then used to selectively electrodeposit a noble metal contact (21, 22, 23, 24) on top of the recessed copper electrodes (11, 12, 13, 14).
- the noble metal on top of copper needs to be not only a diffusion barrier for copper but most importantly an oxygen barrier for copper because subsequent processing steps during the MEMS switch fabrication utilize oxygen plasma to remove the sacrificial material.
- Platinum for instance, is not likely to be an oxygen barrier for copper, as described by D.E. Kotecki, et al., entitled “(Ba, Sr)TiO dielectrics for future stacked-capacitor DRAM” published in IBM J .Res. Dev., 43, No. 3, May 1999, pp. 367-380. Therefore, it cannot be used alone as a contact material on top of copper.
- FIG. 5 describes the formation of the upper contact.
- an organic blanket layer of sacrificial material is deposited.
- Organic material (60) such as SiLK or diamond-like-carbon (DLC)
- DLC diamond-like-carbon
- a thin refractory metal (90) is used to improve adhesion of noble metals for subsequent processing and to act as an additional hardmask for reactive ion etching.
- Metal hardmasks are deposited by PVD, CVD or IMP (ionized metal physical vapor deposition).
- Refractory metals such as Ta, TaN or W can be used, although TaN is preferred over other hardmask materials because of its improved adhesion to silicon dioxide (80).
- Figure 5b shows the formation of a flat recess (100) by lithography, and the refractory metal (i.e., hardmask) (90) patterned and etched by wet etching or REE.
- Recess (100) is formed in the sacrificial organic layer (60) by a plasma process.
- the recess process can be tailored so that the upper contact is shaped in such a way so that it results in optimum contact between the upper and the lower contact.
- One way of generating the upper contact shown in Figure 5b is by creating a flat surface and avoiding roughness when etching the organic layer during recessing.
- the area of the upper contact is designed so that when in contact with the lower contact, it falls within the contact area of the lower contact.
- small area contacts are formed, as shown in Figures 5c and 5d.
- the organic layer is recessed by first etching the metal hardmask layer 90, and dielectric layers 80 and 70 with at least one RIE step. During RTE microtrench ng often occurs and results in uneven etching local to the feature edge.
- the formation of rmcrotienchmg is used, in this application, to provide fangs at the feature edges which protrude into the organic layer. Creating small area points of contact is preferable to generate increased contact pressure for the same applied force.
- the feature is filled with a blanket noble metal layer
- the metal of choice for the upper contact is not necessarily the same as the noble metal of the lower contact but it is selected from the same material set, e.g., Au, AuNi, AuCo, Pd, PdNi, PdCo, Ru, Rh, Re, Os, Pt, PtTi, Ir and their alloys.
- the blanket noble metal layer is typically formed by chemical- mechanical planarization to yield the upper contact (110) but may be selectively electroplated to minimize effects of metal overburden during noble metal CMP.
- the selective electroplating process requires that there be a thin seed layer (101) deposited within the recess and in the field area on top of the hardmask (80).
- the seed layer (101) having a thickness ranging from 100 to 1000 A is then removed from the hardmask area by CMP or ion milling.
- Ruthenium, rhodium and iridium are preferred to form the seed layers for through-mask selective electroplating because there are exists CMP processes that have been developed for these three noble metals.
- Selective electroplating of the noble metal or alloy occurs only within the recess (90) and on top of the seed layer (101).
- the upper contact (110) after selective electroplating is shown in Figure 5f .
- a final embodiment for creating the upper switch contact is to use electroplating through a photoresist mask.
- the process sequence is described in Figure 6a through 6e. Similar to the process described in Figure 5, after formation of the lower switch contact, an organic blanket layer of sacrificial material is deposited.
- the organic material (60) such as SiLK or diamond-like-carbon (DLC) is deposited.
- a thin silicon nitride layer (70) is deposited.
- the nitride layer (70) is patterned and etched creating a recess (90) in the organic sacrificial layer (60).
- a blanket noble metal thin seed layer (71) is deposited on top of the silicon nitride layer (70) to be used to pass electric current during noble metal electrodeposition.
- a photoresist mask (72) is applied on top of the noble seed layer (71), as shown in Figure 6a.
- the upper contact (110) is then formed by selectively electroplating where the photoresist mask has exposed the thin noble metal seed layer, as shown in Figure 6c.
- the photoresist mask (72) is then stripped off ( Figure 6c) and the remaining noble metal seed layer (71) is removed by ion milling or chemical etching ( Figure 6d).
- the organic layer (60) and dielectric layers (70, 80) are then patterned and backfilled with additional dielectric (200) and planarized with CMP as shown in Figure 7a.
- a Dual Damascene copper level is formed in dielectric layers (220, 240 and 200) and capped with silicon nitride (260) as shown in Figure 7b.
- the planar structure is then patterned and REE'ed to open the dielectric stack layers (70, 80, 220, 240 and 260) to expose the organic layer (60).
- Additional organic material 300 is then deposited capped with silicon nitride (320) and patterned by REE to produce the cross section shown in Figure 7C.
- a backfill dielectric (400) is then deposited and planarized and additional dielectric (420) is deposited on the planar surface as shown in Figure 7d. Access vias are now formed in the dielectric layer (420) exposing the organic layer (300) to facilitate device release. The sample is then exposed to an oxygen ash which removes organic layers (300, 60). The device is then sealed by depositing a pinch-off layer (500) and a final series of lithography and RTE are used to form contact (600) for wire bonding or solder ball chip formation. To ascertain improved reliability over extended switch operation, it is preferred that the switch is fully encapsulated in an inert environment with He, N Kr, Ne, or Ar gas.
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04741661A EP1642312B1 (en) | 2003-07-08 | 2004-06-02 | Noble metal contacts for micro-electromechanical switches |
JP2006518191A JP4516960B2 (en) | 2003-07-08 | 2004-06-02 | Switch contact structure of micro electro mechanical system (MEMS) switch |
IL173017A IL173017A0 (en) | 2003-07-08 | 2006-01-08 | Noble metal contacts for micro-electromechanical switches |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US10/604,278 US7202764B2 (en) | 2003-07-08 | 2003-07-08 | Noble metal contacts for micro-electromechanical switches |
US10/604,278 | 2003-07-08 |
Publications (1)
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WO2005006372A1 true WO2005006372A1 (en) | 2005-01-20 |
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Application Number | Title | Priority Date | Filing Date |
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PCT/EP2004/050940 WO2005006372A1 (en) | 2003-07-08 | 2004-06-02 | Noble metal contacts for micro-electromechanical switches |
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US (2) | US7202764B2 (en) |
EP (1) | EP1642312B1 (en) |
JP (1) | JP4516960B2 (en) |
KR (1) | KR100861680B1 (en) |
CN (1) | CN100424804C (en) |
IL (1) | IL173017A0 (en) |
TW (1) | TWI312527B (en) |
WO (1) | WO2005006372A1 (en) |
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- 2004-06-02 JP JP2006518191A patent/JP4516960B2/en not_active Expired - Fee Related
- 2004-06-02 CN CNB2004800192330A patent/CN100424804C/en not_active Expired - Fee Related
- 2004-06-02 KR KR1020067000001A patent/KR100861680B1/en not_active IP Right Cessation
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WO2007041431A1 (en) * | 2005-10-03 | 2007-04-12 | Analog Devices, Inc. | Mems switch contact system |
US7968364B2 (en) | 2005-10-03 | 2011-06-28 | Analog Devices, Inc. | MEMS switch capping and passivation method |
US8194382B2 (en) | 2006-12-22 | 2012-06-05 | Analog Devices, Inc. | Method and apparatus for driving a switch |
JP2012514292A (en) * | 2008-12-24 | 2012-06-21 | インターナショナル・ビジネス・マシーンズ・コーポレーション | HYBRID MEMSRF SWITCH, MANUFACTURING METHOD THEREOF, AND METHOD FOR MANUFACTURING MEMS STRUCTURE |
Also Published As
Publication number | Publication date |
---|---|
TW200514112A (en) | 2005-04-16 |
JP2009514142A (en) | 2009-04-02 |
KR100861680B1 (en) | 2008-10-07 |
EP1642312A1 (en) | 2006-04-05 |
US7202764B2 (en) | 2007-04-10 |
US20060164194A1 (en) | 2006-07-27 |
US7581314B2 (en) | 2009-09-01 |
TWI312527B (en) | 2009-07-21 |
KR20060036438A (en) | 2006-04-28 |
IL173017A0 (en) | 2006-06-11 |
US20050007217A1 (en) | 2005-01-13 |
CN100424804C (en) | 2008-10-08 |
JP4516960B2 (en) | 2010-08-04 |
EP1642312B1 (en) | 2012-11-28 |
CN1816890A (en) | 2006-08-09 |
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