WO2005000733A3 - Circuit integre sur puce de hautes performances - Google Patents
Circuit integre sur puce de hautes performances Download PDFInfo
- Publication number
- WO2005000733A3 WO2005000733A3 PCT/FR2004/001565 FR2004001565W WO2005000733A3 WO 2005000733 A3 WO2005000733 A3 WO 2005000733A3 FR 2004001565 W FR2004001565 W FR 2004001565W WO 2005000733 A3 WO2005000733 A3 WO 2005000733A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- components
- active
- integrated circuit
- substrate
- passive components
- Prior art date
Links
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
- B81C1/00253—Processes for integrating an electronic processing unit with a micromechanical structure not provided for in B81C1/0023 - B81C1/00246
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04767421.3A EP1636130B1 (fr) | 2003-06-24 | 2004-06-23 | Circuit integre sur puce de hautes performances |
US10/561,299 US8048766B2 (en) | 2003-06-24 | 2004-06-23 | Integrated circuit on high performance chip |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR03/07617 | 2003-06-24 | ||
FR0307617A FR2856844B1 (fr) | 2003-06-24 | 2003-06-24 | Circuit integre sur puce de hautes performances |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2005000733A2 WO2005000733A2 (fr) | 2005-01-06 |
WO2005000733A3 true WO2005000733A3 (fr) | 2005-08-25 |
Family
ID=33515360
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/FR2004/001565 WO2005000733A2 (fr) | 2003-06-24 | 2004-06-23 | Circuit integre sur puce de hautes performances |
Country Status (4)
Country | Link |
---|---|
US (1) | US8048766B2 (fr) |
EP (1) | EP1636130B1 (fr) |
FR (1) | FR2856844B1 (fr) |
WO (1) | WO2005000733A2 (fr) |
Families Citing this family (60)
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FR2748851B1 (fr) | 1996-05-15 | 1998-08-07 | Commissariat Energie Atomique | Procede de realisation d'une couche mince de materiau semiconducteur |
FR2773261B1 (fr) | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
FR2848336B1 (fr) | 2002-12-09 | 2005-10-28 | Commissariat Energie Atomique | Procede de realisation d'une structure contrainte destinee a etre dissociee |
US7632738B2 (en) * | 2003-06-24 | 2009-12-15 | Sang-Yun Lee | Wafer bonding method |
FR2861497B1 (fr) | 2003-10-28 | 2006-02-10 | Soitec Silicon On Insulator | Procede de transfert catastrophique d'une couche fine apres co-implantation |
US7307331B2 (en) * | 2004-03-31 | 2007-12-11 | Intel Corporation | Integrated radio front-end module with embedded circuit elements |
US7312505B2 (en) | 2004-03-31 | 2007-12-25 | Intel Corporation | Semiconductor substrate with interconnections and embedded circuit elements |
US7382056B2 (en) | 2004-04-29 | 2008-06-03 | Sychip Inc. | Integrated passive devices |
JP2006196668A (ja) * | 2005-01-13 | 2006-07-27 | Toshiba Corp | 半導体装置及びその製造方法 |
US8217473B2 (en) | 2005-07-29 | 2012-07-10 | Hewlett-Packard Development Company, L.P. | Micro electro-mechanical system packaging and interconnect |
FR2891281B1 (fr) * | 2005-09-28 | 2007-12-28 | Commissariat Energie Atomique | Procede de fabrication d'un element en couches minces. |
FI119729B (fi) * | 2005-11-23 | 2009-02-27 | Vti Technologies Oy | Menetelmä mikroelektromekaanisen komponentin valmistamiseksi ja mikroelektromekaaninen komponentti |
FI119728B (fi) | 2005-11-23 | 2009-02-27 | Vti Technologies Oy | Menetelmä mikroelektromekaanisen komponentin valmistamiseksi ja mikroelektromekaaninen komponentti |
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US8043931B1 (en) * | 2006-09-18 | 2011-10-25 | Gang Zhang | Methods for forming multi-layer silicon structures |
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FR2910179B1 (fr) | 2006-12-19 | 2009-03-13 | Commissariat Energie Atomique | PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART |
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US10680515B2 (en) | 2011-05-05 | 2020-06-09 | Psemi Corporation | Power converters with modular stages |
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JP6024400B2 (ja) | 2012-11-07 | 2016-11-16 | ソニー株式会社 | 半導体装置、半導体装置の製造方法、及びアンテナスイッチモジュール |
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FR3003688B1 (fr) * | 2013-03-22 | 2016-07-01 | Commissariat Energie Atomique | Procede d'assemblage flip chip comportant le pre-enrobage d'elements d'interconnexion |
US9660520B2 (en) | 2013-04-09 | 2017-05-23 | Massachusetts Institute Of Technology | Method and apparatus to provide power conversion with high power factor |
CN104140072B (zh) * | 2013-05-09 | 2016-07-13 | 苏州敏芯微电子技术股份有限公司 | 微机电系统与集成电路的集成芯片及其制造方法 |
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KR102161260B1 (ko) | 2013-11-07 | 2020-09-29 | 삼성전자주식회사 | 관통전극을 갖는 반도체 소자 및 그 제조방법 |
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WO2016004427A1 (fr) | 2014-07-03 | 2016-01-07 | Massachusetts Institute Of Technology | Conversion de correction de facteur de puissance à haute fréquence et à haute densité pour interface de grille d'entrée universelle |
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CN107580749A (zh) | 2015-03-13 | 2018-01-12 | 佩里格林半导体公司 | 用于促进绝热的电容器间电荷传输的具有电感器的dc‑dc变压器 |
TWI636533B (zh) | 2017-09-15 | 2018-09-21 | Industrial Technology Research Institute | 半導體封裝結構 |
US10686367B1 (en) | 2019-03-04 | 2020-06-16 | Psemi Corporation | Apparatus and method for efficient shutdown of adiabatic charge pumps |
CN116207074A (zh) * | 2019-07-29 | 2023-06-02 | 群创光电股份有限公司 | 电子装置 |
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FR2848336B1 (fr) | 2002-12-09 | 2005-10-28 | Commissariat Energie Atomique | Procede de realisation d'une structure contrainte destinee a etre dissociee |
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FR2855910B1 (fr) * | 2003-06-06 | 2005-07-15 | Commissariat Energie Atomique | Procede d'obtention d'une couche tres mince par amincissement par auto-portage provoque |
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FR2925221B1 (fr) | 2007-12-17 | 2010-02-19 | Commissariat Energie Atomique | Procede de transfert d'une couche mince |
FR2947098A1 (fr) | 2009-06-18 | 2010-12-24 | Commissariat Energie Atomique | Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince |
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2003
- 2003-06-24 FR FR0307617A patent/FR2856844B1/fr not_active Expired - Lifetime
-
2004
- 2004-06-23 EP EP04767421.3A patent/EP1636130B1/fr not_active Not-in-force
- 2004-06-23 US US10/561,299 patent/US8048766B2/en not_active Expired - Fee Related
- 2004-06-23 WO PCT/FR2004/001565 patent/WO2005000733A2/fr active Application Filing
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Also Published As
Publication number | Publication date |
---|---|
WO2005000733A2 (fr) | 2005-01-06 |
EP1636130A2 (fr) | 2006-03-22 |
EP1636130B1 (fr) | 2016-05-25 |
FR2856844B1 (fr) | 2006-02-17 |
US20060252229A1 (en) | 2006-11-09 |
FR2856844A1 (fr) | 2004-12-31 |
US8048766B2 (en) | 2011-11-01 |
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