WO2004114166A3 - Integrated circuit development system - Google Patents
Integrated circuit development system Download PDFInfo
- Publication number
- WO2004114166A3 WO2004114166A3 PCT/US2004/019510 US2004019510W WO2004114166A3 WO 2004114166 A3 WO2004114166 A3 WO 2004114166A3 US 2004019510 W US2004019510 W US 2004019510W WO 2004114166 A3 WO2004114166 A3 WO 2004114166A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- hardware
- objects
- software
- integrated circuit
- topology
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Geometry (AREA)
- Evolutionary Computation (AREA)
- Logic Circuits (AREA)
- Communication Control (AREA)
- Information Transfer Systems (AREA)
- Stored Programmes (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006517391A JP2007526539A (en) | 2003-06-18 | 2004-06-18 | Integrated circuit development system |
AU2004250685A AU2004250685A1 (en) | 2003-06-18 | 2004-06-18 | Integrated circuit development system |
EP04755597.4A EP1636725B1 (en) | 2003-06-18 | 2004-06-18 | Circuit register and method therefor |
CA2527970A CA2527970C (en) | 2003-06-18 | 2004-06-18 | Integrated circuit development system |
TW093138894A TWI285825B (en) | 2004-06-18 | 2004-12-15 | Hardware register on a chip, method of implementing a protocol register, machine-accessible medium embodying a data interface protocol or a software object, data pipeline element, data pipeline device, join element, fork element, data interface device... |
IL172142A IL172142A0 (en) | 2003-06-18 | 2005-11-23 | Integrated circuit development system |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US47975903P | 2003-06-18 | 2003-06-18 | |
US60/479,759 | 2003-06-18 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2004114166A2 WO2004114166A2 (en) | 2004-12-29 |
WO2004114166A3 true WO2004114166A3 (en) | 2005-12-29 |
Family
ID=33539216
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2004/019510 WO2004114166A2 (en) | 2003-06-18 | 2004-06-18 | Integrated circuit development system |
Country Status (10)
Country | Link |
---|---|
US (6) | US7139985B2 (en) |
EP (1) | EP1636725B1 (en) |
JP (1) | JP2007526539A (en) |
KR (1) | KR20060063800A (en) |
CN (1) | CN101044485A (en) |
AU (1) | AU2004250685A1 (en) |
CA (1) | CA2527970C (en) |
IL (1) | IL172142A0 (en) |
RU (1) | RU2006100275A (en) |
WO (1) | WO2004114166A2 (en) |
Families Citing this family (46)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002097565A2 (en) * | 2001-05-25 | 2002-12-05 | Annapolis Micro Systems, Inc. | Method and apparatus for modeling dataflow systems and realization to hardware |
US20070169022A1 (en) * | 2003-06-18 | 2007-07-19 | Jones Anthony M | Processor having multiple instruction sources and execution modes |
US20070186076A1 (en) * | 2003-06-18 | 2007-08-09 | Jones Anthony M | Data pipeline transport system |
WO2004114166A2 (en) | 2003-06-18 | 2004-12-29 | Ambric, Inc. | Integrated circuit development system |
US7373631B1 (en) * | 2004-08-11 | 2008-05-13 | Altera Corporation | Methods of producing application-specific integrated circuit equivalents of programmable logic |
US7228509B1 (en) * | 2004-08-20 | 2007-06-05 | Altera Corporation | Design tools for configurable serial communications protocols |
US20060080632A1 (en) * | 2004-09-30 | 2006-04-13 | Mathstar, Inc. | Integrated circuit layout having rectilinear structure of objects |
JP2006155448A (en) * | 2004-12-01 | 2006-06-15 | Matsushita Electric Ind Co Ltd | Data processor and method for designing data processor |
US7523423B1 (en) * | 2004-12-10 | 2009-04-21 | Synopsys, Inc. | Method and apparatus for production of data-flow-graphs by symbolic simulation |
US7434192B2 (en) * | 2004-12-13 | 2008-10-07 | Altera Corporation | Techniques for optimizing design of a hard intellectual property block for data transmission |
US7392489B1 (en) | 2005-01-20 | 2008-06-24 | Altera Corporation | Methods and apparatus for implementing application specific processors |
US7613858B1 (en) * | 2005-01-24 | 2009-11-03 | Altera Corporation | Implementing signal processing cores as application specific processors |
US20070247189A1 (en) * | 2005-01-25 | 2007-10-25 | Mathstar | Field programmable semiconductor object array integrated circuit |
US7546582B2 (en) | 2005-03-30 | 2009-06-09 | International Business Machines Corporation | Managing dynamic configuration data for producer components in a computer infrastructure |
US20070058686A1 (en) * | 2005-08-16 | 2007-03-15 | Federico Capasso | Active optical antenna |
US20070073966A1 (en) * | 2005-09-23 | 2007-03-29 | Corbin John R | Network processor-based storage controller, compute element and method of using same |
TW200725415A (en) * | 2005-12-30 | 2007-07-01 | Tatung Co Ltd | Method for automatically translating high level programming language into hardware description language |
JP2009524134A (en) | 2006-01-18 | 2009-06-25 | ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト | Hardware definition method |
JP4528728B2 (en) * | 2006-01-31 | 2010-08-18 | 株式会社東芝 | Digital circuit automatic design apparatus, automatic design method, and automatic design program |
US7991221B1 (en) * | 2006-03-06 | 2011-08-02 | Kling Daniel H | Data processing system utilizing topological methods to manipulate and categorize n-dimensional datasets |
US8091064B2 (en) * | 2006-04-14 | 2012-01-03 | Panasonic Corporation | Supporting system, design supporting method, and computer-readable recording medium recorded with design supporting program |
US9162091B2 (en) * | 2007-05-09 | 2015-10-20 | Bradley A. Kuhnert | Safety harness |
US20090144595A1 (en) * | 2007-11-30 | 2009-06-04 | Mathstar, Inc. | Built-in self-testing (bist) of field programmable object arrays |
US8726248B2 (en) * | 2008-06-12 | 2014-05-13 | Oracle America, Inc. | Method and apparatus for enregistering memory locations |
US8438251B2 (en) * | 2009-10-09 | 2013-05-07 | Oracle International Corporation | Methods and systems for implementing a virtual storage network |
US8898621B2 (en) * | 2009-10-09 | 2014-11-25 | Oracle International Corporation | Methods and systems for implementing a logical programming model |
US8572004B2 (en) | 2009-12-29 | 2013-10-29 | International Business Machines Corporation | Space solution search |
US8453081B2 (en) | 2010-05-20 | 2013-05-28 | International Business Machines Corporation | Electrical design space exploration |
WO2013050057A1 (en) * | 2011-10-03 | 2013-04-11 | Telefonaktiebolaget L M Ericsson (Publ) | A method for exploiting massive parallelism |
EP2839286B1 (en) * | 2012-04-18 | 2018-02-28 | Siemens Healthcare Diagnostics Inc. | Compounds and methods for preparation of conjugate reagents |
US9389841B2 (en) | 2012-07-18 | 2016-07-12 | Micron Technology, Inc. | Methods and systems for using state vector data in a state machine engine |
DE102012022838A1 (en) | 2012-11-23 | 2014-05-28 | Phoenix Contact Gmbh & Co. Kg | System for providing an individually configured safety relay |
US8799836B1 (en) * | 2013-07-08 | 2014-08-05 | International Business Machines Corporation | Yield optimization for design library elements at library element level or at product level |
US9898310B2 (en) * | 2013-10-16 | 2018-02-20 | International Business Machines Corporation | Symmetrical dimensions in context-oriented programming to optimize software object execution |
US9276575B2 (en) * | 2013-11-18 | 2016-03-01 | Intel Corporation | Low leakage state retention synchronizer |
US8887108B1 (en) * | 2014-05-14 | 2014-11-11 | Fujitsu Limited | Support apparatus, design support method, and recording medium |
CN105515565B (en) * | 2015-12-14 | 2018-07-13 | 天津光电通信技术有限公司 | A kind of method that hardware logic resource multiplex module and multiplexing are realized |
US10545739B2 (en) * | 2016-04-05 | 2020-01-28 | International Business Machines Corporation | LLVM-based system C compiler for architecture synthesis |
JP6739556B2 (en) * | 2016-06-30 | 2020-08-12 | コーニンクレッカ フィリップス エヌ ヴェKoninklijke Philips N.V. | Sealed control panel for medical devices |
US10459843B2 (en) | 2016-12-30 | 2019-10-29 | Texas Instruments Incorporated | Streaming engine with separately selectable element and group duplication |
CN108052018B (en) * | 2017-12-13 | 2020-09-01 | 中国兵器装备集团自动化研究所 | Light-weight processing method for guidance and control assembly and guidance and control assembly |
CN109884517B (en) * | 2019-03-21 | 2021-04-30 | 浪潮商用机器有限公司 | Chip to be tested and test system |
EP3770800A1 (en) * | 2019-07-25 | 2021-01-27 | ABB S.p.A. | A computer-implemented method for reading a digital graphical diagram representing an electric circuit |
CN111238426B (en) * | 2020-02-24 | 2021-06-15 | 重庆市计量质量检测研究院 | Standard device for calibrating measurement error of micro-nano coordinate measurement system |
CN113194097B (en) * | 2021-04-30 | 2022-02-11 | 北京数盾信息科技有限公司 | Data processing method and device for security gateway and security gateway |
CN113031496B (en) * | 2021-05-27 | 2021-09-21 | 之江实验室 | Industrial protocol mapping structure and method based on FPGA |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999039288A2 (en) * | 1998-01-30 | 1999-08-05 | Tera Systems, Inc. | Method and system for creating optimized physical implementations from high-level descriptions of electronic design |
US6308229B1 (en) * | 1998-08-28 | 2001-10-23 | Theseus Logic, Inc. | System for facilitating interfacing between multiple non-synchronous systems utilizing an asynchronous FIFO that uses asynchronous logic |
WO2002080044A2 (en) * | 2001-03-29 | 2002-10-10 | Xilinx, Inc. | Method of constraining non-uniform fpga layouts using a uniform coordinate system |
Family Cites Families (100)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US1445A (en) * | 1839-12-27 | Lattice bkidge | ||
US1296A (en) * | 1839-08-21 | Machine eoe bending tiees | ||
US56084A (en) * | 1866-07-03 | Improved car-spring | ||
US124012A (en) * | 1872-02-27 | Improvement in refrigerating preserving-houses | ||
US229482A (en) * | 1880-06-29 | Manufacture of coffee-pots | ||
US25363A (en) * | 1859-09-06 | George henderson | ||
US3290650A (en) | 1963-05-13 | 1966-12-06 | Rca Corp | Character reader utilizing stroke and cavity detection for recognition of characters |
US4914574A (en) | 1984-08-16 | 1990-04-03 | Mitsubishi Denki Kabushiki Kaisha | Data transmission apparatus having cascaded data processing modules for daisy chain data transfer |
US5283554A (en) * | 1990-02-21 | 1994-02-01 | Analog Devices, Inc. | Mode switching system for a pixel based display unit |
JPH03269728A (en) | 1990-03-20 | 1991-12-02 | Fujitsu Ltd | Instruction execution control system for pipeline computer |
US5867399A (en) | 1990-04-06 | 1999-02-02 | Lsi Logic Corporation | System and method for creating and validating structural description of electronic system from higher-level and behavior-oriented description |
US5872448A (en) | 1991-06-18 | 1999-02-16 | Lightspeed Semiconductor Corporation | Integrated circuit architecture having an array of test cells providing full controlability for automatic circuit verification |
DE69229338T2 (en) * | 1992-06-30 | 1999-12-16 | Discovision Ass | Data pipeline system |
US5835740A (en) | 1992-06-30 | 1998-11-10 | Discovision Associates | Data pipeline system and data encoding method |
US6112017A (en) | 1992-06-30 | 2000-08-29 | Discovision Associates | Pipeline processing machine having a plurality of reconfigurable processing stages interconnected by a two-wire interface bus |
US5404428A (en) * | 1993-12-07 | 1995-04-04 | Sun Microsystems, Inc. | Method and system for updating derived items in a view model which includes multiple coordinate systems |
US5655151A (en) * | 1994-01-28 | 1997-08-05 | Apple Computer, Inc. | DMA controller having a plurality of DMA channels each having multiple register sets storing different information controlling respective data transfer |
JP3269728B2 (en) | 1994-02-25 | 2002-04-02 | 株式会社日立製作所 | Jet pump clamp for measuring tube fixing |
US6044211A (en) | 1994-03-14 | 2000-03-28 | C.A.E. Plus, Inc. | Method for graphically representing a digital device as a behavioral description with data and control flow elements, and for converting the behavioral description to a structural description |
US5602878A (en) * | 1994-09-23 | 1997-02-11 | Intel Corporation | Method of delivering stable data across an asynchronous interface |
US6025853A (en) | 1995-03-24 | 2000-02-15 | 3Dlabs Inc. Ltd. | Integrated graphics subsystem with message-passing architecture |
ATE257611T1 (en) | 1995-10-23 | 2004-01-15 | Imec Inter Uni Micro Electr | DESIGN SYSTEM AND METHODS FOR COMBINED DESIGN OF HARDWARE AND SOFTWARE |
US5870588A (en) | 1995-10-23 | 1999-02-09 | Interuniversitair Micro-Elektronica Centrum(Imec Vzw) | Design environment and a design method for hardware/software co-design |
WO1997035254A1 (en) | 1996-03-19 | 1997-09-25 | Massachusetts Institute Of Technology | Computer system and computer implemented process for representing software system descriptions and for generating executable computer programs and computer system configurations from software system descriptions |
US5745124A (en) | 1996-06-21 | 1998-04-28 | Texas Instruments Incorporated | Method and system for data translation |
US5778059A (en) | 1996-08-30 | 1998-07-07 | Digital Technics, Inc. | Distributed predictive and event-driven processing environment |
US6289488B1 (en) | 1997-02-24 | 2001-09-11 | Lucent Technologies Inc. | Hardware-software co-synthesis of hierarchical heterogeneous distributed embedded systems |
US6606588B1 (en) * | 1997-03-14 | 2003-08-12 | Interuniversitair Micro-Elecktronica Centrum (Imec Vzw) | Design apparatus and a method for generating an implementable description of a digital system |
US6233540B1 (en) | 1997-03-14 | 2001-05-15 | Interuniversitair Micro-Elektronica Centrum | Design environment and a method for generating an implementable description of a digital system |
US6330659B1 (en) | 1997-11-06 | 2001-12-11 | Iready Corporation | Hardware accelerator for an object-oriented programming language |
US6105083A (en) | 1997-06-20 | 2000-08-15 | Avid Technology, Inc. | Apparatus and method for controlling transfer of data between and processing of data by interconnected data processing elements |
FR2766937B1 (en) | 1997-07-31 | 2001-04-27 | Sqware T | PROTOCOL AND SYSTEM FOR BUS LINKING BETWEEN ELEMENTS OF A MICROCONTROLLER |
US6112304A (en) | 1997-08-27 | 2000-08-29 | Zipsoft, Inc. | Distributed computing architecture |
US6167502A (en) | 1997-10-10 | 2000-12-26 | Billions Of Operations Per Second, Inc. | Method and apparatus for manifold array processing |
US6078962A (en) | 1997-10-30 | 2000-06-20 | Lsi Logic Corporation | Bi-directional asynchronous transfer scheme using a single handshake |
IL122299A (en) | 1997-11-25 | 2003-11-23 | Broadcom Corp | Video encoding device |
US6075935A (en) | 1997-12-01 | 2000-06-13 | Improv Systems, Inc. | Method of generating application specific integrated circuits using a programmable hardware architecture |
DE69827589T2 (en) | 1997-12-17 | 2005-11-03 | Elixent Ltd. | Configurable processing assembly and method of using this assembly to build a central processing unit |
US6216223B1 (en) * | 1998-01-12 | 2001-04-10 | Billions Of Operations Per Second, Inc. | Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor |
US6230307B1 (en) * | 1998-01-26 | 2001-05-08 | Xilinx, Inc. | System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects |
US6292925B1 (en) | 1998-03-27 | 2001-09-18 | Xilinx, Inc. | Context-sensitive self implementing modules |
US6092174A (en) | 1998-06-01 | 2000-07-18 | Context, Inc. | Dynamically reconfigurable distributed integrated circuit processor and method |
US6167501A (en) | 1998-06-05 | 2000-12-26 | Billions Of Operations Per Second, Inc. | Methods and apparatus for manarray PE-PE switch control |
DE69942011D1 (en) | 1998-10-10 | 2010-03-25 | Ibm | Program code conversion with reduced translation |
US6467009B1 (en) * | 1998-10-14 | 2002-10-15 | Triscend Corporation | Configurable processor system unit |
US6145073A (en) | 1998-10-16 | 2000-11-07 | Quintessence Architectures, Inc. | Data flow integrated circuit architecture |
US6701515B1 (en) | 1999-05-27 | 2004-03-02 | Tensilica, Inc. | System and method for dynamically designing and evaluating configurable processor instructions |
US6477697B1 (en) * | 1999-02-05 | 2002-11-05 | Tensilica, Inc. | Adding complex instruction extensions defined in a standardized language to a microprocessor design to produce a configurable definition of a target instruction set, and hdl description of circuitry necessary to implement the instruction set, and development and verification tools for the instruction set |
US6477683B1 (en) | 1999-02-05 | 2002-11-05 | Tensilica, Inc. | Automated processor generation system for designing a configurable processor and method for the same |
US6654889B1 (en) * | 1999-02-19 | 2003-11-25 | Xilinx, Inc. | Method and apparatus for protecting proprietary configuration data for programmable logic devices |
US6622233B1 (en) * | 1999-03-31 | 2003-09-16 | Star Bridge Systems, Inc. | Hypercomputer |
US6473769B1 (en) | 1999-03-31 | 2002-10-29 | Microsoft Corporation | Property linking in object-oriented computing environments |
US6298472B1 (en) | 1999-05-07 | 2001-10-02 | Chameleon Systems, Inc. | Behavioral silicon construct architecture and mapping |
GB9918643D0 (en) | 1999-08-06 | 1999-10-13 | Canon Kk | Geometry pipeline for computer graphics |
US6597664B1 (en) * | 1999-08-19 | 2003-07-22 | Massachusetts Institute Of Technology | Digital circuit synthesis system |
US6507947B1 (en) | 1999-08-20 | 2003-01-14 | Hewlett-Packard Company | Programmatic synthesis of processor element arrays |
EP1215569B1 (en) * | 1999-08-30 | 2010-04-28 | IP Flex Inc. | Data processor |
US6598177B1 (en) | 1999-10-01 | 2003-07-22 | Stmicroelectronics Ltd. | Monitoring error conditions in an integrated circuit |
US6763034B1 (en) | 1999-10-01 | 2004-07-13 | Stmicroelectronics, Ltd. | Connection ports for interconnecting modules in an integrated circuit |
US20020129340A1 (en) | 1999-10-28 | 2002-09-12 | Tuttle Douglas D. | Reconfigurable isomorphic software representations |
US6633181B1 (en) * | 1999-12-30 | 2003-10-14 | Stretch, Inc. | Multi-scale programmable array |
US6763327B1 (en) | 2000-02-17 | 2004-07-13 | Tensilica, Inc. | Abstraction of configurable processor functionality for operating systems portability |
US20010025363A1 (en) * | 2000-03-24 | 2001-09-27 | Cary Ussery | Designer configurable multi-processor system |
WO2001082053A2 (en) | 2000-04-26 | 2001-11-01 | The Trustees Of Columbia University In The City Of New York | A low latency fifo circuit for mixed clock systems |
WO2001086372A2 (en) | 2000-05-12 | 2001-11-15 | Xtreamlok Pty. Ltd. | Information security method and system |
ES2289205T3 (en) * | 2000-05-17 | 2008-02-01 | Matsushita Electric Industrial Co., Ltd | HYBRID ARQ METHOD FOR DATA TRANSMISSION IN PACKAGES WITH A CONTROL CHANNEL AND A DATA CHANNEL. |
US6850092B2 (en) * | 2000-06-09 | 2005-02-01 | The Trustees Of Columbia University | Low latency FIFO circuits for mixed asynchronous and synchronous systems |
US6353395B1 (en) * | 2000-08-08 | 2002-03-05 | Brk Brands, Inc. | Interconnectable detector with local alarm indicator |
US6889310B2 (en) * | 2000-08-12 | 2005-05-03 | Mobilygen Corporation | Multithreaded data/context flow processing architecture |
US7080183B1 (en) * | 2000-08-16 | 2006-07-18 | Koninklijke Philips Electronics N.V. | Reprogrammable apparatus supporting the processing of a digital signal stream and method |
DE10052210B4 (en) | 2000-10-20 | 2004-12-23 | Infineon Technologies Ag | Integrated circuit with a synchronous and asynchronous circuit and method for operating such an integrated circuit |
US6507214B1 (en) * | 2000-10-26 | 2003-01-14 | Cypress Semiconductor Corporation | Digital configurable macro architecture |
GB2370381B (en) * | 2000-12-19 | 2003-12-24 | Picochip Designs Ltd | Processor architecture |
GB2370380B (en) | 2000-12-19 | 2003-12-31 | Picochip Designs Ltd | Processor architecture |
US6975628B2 (en) | 2000-12-22 | 2005-12-13 | Intel Corporation | Method for representing and controlling packet data flow through packet forwarding hardware |
US6483343B1 (en) | 2000-12-29 | 2002-11-19 | Quicklogic Corporation | Configurable computational unit embedded in a programmable device |
AU2002243655A1 (en) * | 2001-01-25 | 2002-08-06 | Improv Systems, Inc. | Compiler for multiple processor and distributed memory architectures |
US6857110B1 (en) * | 2001-01-30 | 2005-02-15 | Stretch, Inc. | Design methodology for merging programmable logic into a custom IC |
JP4475835B2 (en) | 2001-03-05 | 2010-06-09 | 富士通株式会社 | Input line interface device and packet communication device |
US7142882B2 (en) | 2001-03-09 | 2006-11-28 | Schmidt Dominik J | Single chip wireless communication integrated circuit |
US20030054774A1 (en) | 2001-03-22 | 2003-03-20 | Quicksilver Technology, Inc. | Method and system for managing hardware resources to implement system acquisition using an adaptive computing architecture |
US6836839B2 (en) | 2001-03-22 | 2004-12-28 | Quicksilver Technology, Inc. | Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements |
US6618434B2 (en) | 2001-05-31 | 2003-09-09 | Quicksilver Technology, Inc. | Adaptive, multimode rake receiver for dynamic search and multipath reception |
US6795882B1 (en) | 2001-06-04 | 2004-09-21 | Advanced Micro Devices, Inc. | High speed asynchronous bus for an integrated circuit |
US6653859B2 (en) * | 2001-06-11 | 2003-11-25 | Lsi Logic Corporation | Heterogeneous integrated circuit with reconfigurable logic cores |
US7657877B2 (en) * | 2001-06-20 | 2010-02-02 | Pact Xpp Technologies Ag | Method for processing data |
GB2381336B (en) * | 2001-08-21 | 2005-09-28 | Silicon Infusion Ltd | Object orientated heterogeneous multi-processor platform |
US6931561B2 (en) * | 2001-10-16 | 2005-08-16 | International Business Machines Corporation | Apparatus and method for asynchronously interfacing high-speed clock domain and low-speed clock domain using a plurality of storage and multiplexer components |
CN1666202A (en) * | 2002-04-25 | 2005-09-07 | Arc国际公司 | Apparatus and method for managing integrated circuit designs |
JP3934493B2 (en) | 2002-06-28 | 2007-06-20 | 富士通株式会社 | Integrated circuit and system development method |
US7471643B2 (en) | 2002-07-01 | 2008-12-30 | Panasonic Corporation | Loosely-biased heterogeneous reconfigurable arrays |
US7065665B2 (en) | 2002-10-02 | 2006-06-20 | International Business Machines Corporation | Interlocked synchronous pipeline clock gating |
US6877150B1 (en) * | 2002-12-04 | 2005-04-05 | Xilinx, Inc. | Method of transforming software language constructs to functional hardware equivalents |
US7400629B2 (en) | 2002-12-19 | 2008-07-15 | International Business Machines Corporation | CAM based system and method for re-sequencing data packets |
US6816562B2 (en) * | 2003-01-07 | 2004-11-09 | Mathstar, Inc. | Silicon object array with unidirectional segmented bus architecture |
US20040193763A1 (en) * | 2003-03-28 | 2004-09-30 | Fujitsu Limited | Inter-bus communication interface device and data security device |
US7000211B2 (en) * | 2003-03-31 | 2006-02-14 | Stretch, Inc. | System and method for efficiently mapping heterogeneous objects onto an array of heterogeneous programmable logic resources |
US7062586B2 (en) | 2003-04-21 | 2006-06-13 | Xilinx, Inc. | Method and apparatus for communication within a programmable logic device using serial transceivers |
US20040252713A1 (en) * | 2003-06-13 | 2004-12-16 | Roger Taylor | Channel status management system for multi-channel LIU |
WO2004114166A2 (en) * | 2003-06-18 | 2004-12-29 | Ambric, Inc. | Integrated circuit development system |
-
2004
- 2004-06-18 WO PCT/US2004/019510 patent/WO2004114166A2/en active Application Filing
- 2004-06-18 JP JP2006517391A patent/JP2007526539A/en active Pending
- 2004-06-18 US US10/871,311 patent/US7139985B2/en active Active
- 2004-06-18 US US10/871,329 patent/US7865637B2/en active Active
- 2004-06-18 KR KR1020057024285A patent/KR20060063800A/en not_active Application Discontinuation
- 2004-06-18 CN CNA200480017196XA patent/CN101044485A/en active Pending
- 2004-06-18 CA CA2527970A patent/CA2527970C/en active Active
- 2004-06-18 US US10/871,347 patent/US7206870B2/en active Active
- 2004-06-18 AU AU2004250685A patent/AU2004250685A1/en not_active Abandoned
- 2004-06-18 RU RU2006100275/09A patent/RU2006100275A/en not_active Application Discontinuation
- 2004-06-18 EP EP04755597.4A patent/EP1636725B1/en active Active
-
2005
- 2005-11-23 IL IL172142A patent/IL172142A0/en unknown
-
2006
- 2006-01-06 US US11/326,701 patent/US7409533B2/en active Active
- 2006-08-21 US US11/466,083 patent/US7406584B2/en active Active
- 2006-08-22 US US11/466,337 patent/US7673275B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999039288A2 (en) * | 1998-01-30 | 1999-08-05 | Tera Systems, Inc. | Method and system for creating optimized physical implementations from high-level descriptions of electronic design |
US6308229B1 (en) * | 1998-08-28 | 2001-10-23 | Theseus Logic, Inc. | System for facilitating interfacing between multiple non-synchronous systems utilizing an asynchronous FIFO that uses asynchronous logic |
WO2002080044A2 (en) * | 2001-03-29 | 2002-10-10 | Xilinx, Inc. | Method of constraining non-uniform fpga layouts using a uniform coordinate system |
Non-Patent Citations (6)
Title |
---|
CARLONI L P ET AL: "A methodology for correct-by-construction latency insensitive design", COMPUTER-AIDED DESIGN, 1999. DIGEST OF TECHNICAL PAPERS. 1999 IEEE/ACM INTERNATIONAL CONFERENCE ON SAN JOSE, CA, USA 7-11 NOV. 1999, PISCATAWAY, NJ, USA,IEEE, US, 7 November 1999 (1999-11-07), pages 309 - 315, XP010363870, ISBN: 0-7803-5832-5 * |
CASU M R ET AL: "Issues in implementing latency insensitive protocols", DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, 2004. PROCEEDINGS FEB. 16-20, 2004, PISCATAWAY, NJ, USA,IEEE, vol. 2, 16 February 2004 (2004-02-16), pages 1390 - 1391, XP010684987, ISBN: 0-7695-2085-5 * |
CHANDRANMENON G P ET AL: "RECONSIDERING FRAGMENTATION AND REASSEMBLY", PROCEEDINGS OF THE 17TH ANNUAL ACM SYMPOSIUM ON PRINCIPLES OF DISTRIBUTED COMPUTING.PODC 1998. PUERTO VALLARTA, MEXICO, JUNE 28 - JULY 2, 1998, ACM SIGACT - SIGMOD SYMPOSIUM ON PRINCIPLES OF DISTRIBUTED COMPUTING, NEW YORK, NY : ACM, US, 28 June 1998 (1998-06-28), pages 21 - 29, XP002921718, ISBN: 0-89791-877-7 * |
CHELCEA T ET AL: "A low-latency FIFO for mixed-clock systems", IEEE COMPUT SOCIETY, 27 April 2000 (2000-04-27), Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era, pages 119 - 126, XP010379677 * |
LU ET.AL.: "Performance Analysis and Efficient Implementation of Latency Insensitive Systems", TECHNICAL REPORT TR-ECE03-06, March 2003 (2003-03-01), SCHOOL OF ELECTRICAL & COMPUTER ENGINEERING, PURDUE UNIVERSITY, XP002337839, Retrieved from the Internet <URL:www.engineering.purdue.edu/ECE/Research/TR/2000pdfs/TR/2003pdfs/TR-ECE-03-06.pdf> [retrieved on 20050722] * |
RUIBING LU ET AL: "Performance optimization of latency insensitive systems through buffer queue sizing of communication channels", IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN. ICCAD 2003. IEEE/ACM DIGEST OF TECHNICAL PAPERS. SAN JOSE, CA, NOV. 9 - 13, 2003, IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN, NEW YORK, NY : ACM, US, 9 November 2003 (2003-11-09), pages 227 - 231, XP010677157, ISBN: 1-58113-762-1 * |
Also Published As
Publication number | Publication date |
---|---|
US20060282813A1 (en) | 2006-12-14 |
AU2004250685A1 (en) | 2004-12-29 |
EP1636725A2 (en) | 2006-03-22 |
CA2527970A1 (en) | 2004-12-29 |
CN101044485A (en) | 2007-09-26 |
EP1636725B1 (en) | 2018-05-16 |
IL172142A0 (en) | 2006-04-10 |
US20050005250A1 (en) | 2005-01-06 |
JP2007526539A (en) | 2007-09-13 |
US7409533B2 (en) | 2008-08-05 |
US7673275B2 (en) | 2010-03-02 |
US7865637B2 (en) | 2011-01-04 |
US7206870B2 (en) | 2007-04-17 |
RU2006100275A (en) | 2006-07-10 |
US20050015733A1 (en) | 2005-01-20 |
US7406584B2 (en) | 2008-07-29 |
KR20060063800A (en) | 2006-06-12 |
US7139985B2 (en) | 2006-11-21 |
US20060282812A1 (en) | 2006-12-14 |
CA2527970C (en) | 2014-07-29 |
WO2004114166A2 (en) | 2004-12-29 |
US20050055657A1 (en) | 2005-03-10 |
US20060117275A1 (en) | 2006-06-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2004114166A3 (en) | Integrated circuit development system | |
WO2008048951A3 (en) | Extensible automation development environment | |
WO2001095133A3 (en) | A method of modelling a maintenance system | |
WO2002095598A3 (en) | Programmable logic device including programmable interface core and central processing unit | |
WO2005010690A3 (en) | Design for manufacturability | |
EP2252951A4 (en) | Automatically creating and modifying furniture layouts in design software | |
WO2007076098A3 (en) | Digital effects analysis in modeling environments | |
WO2007067679A3 (en) | Virtual designer | |
EP1983425A4 (en) | Object relation display program and object relation display method | |
WO2002103503A3 (en) | Computing device with dynamic ornamental appearance | |
WO2003075189A3 (en) | An interconnect-aware methodology for integrated circuit design | |
TW200506607A (en) | Data processing device and mobile device | |
WO2001090881A3 (en) | Asynchronous completion prediction | |
WO2002073355A3 (en) | System for configuration programming | |
WO2001072552A3 (en) | Method and device to design a domain model for control systems in vehicles with respect of the functional requirements | |
WO2001075654A3 (en) | Thematic response to a computer user's context, such as by a wearable personal computer | |
WO2006029882A3 (en) | Method for searching for a similar construction model | |
TW200601099A (en) | Integrated circuit development system | |
WO2004074657A3 (en) | Signal conditioner and user interface | |
WO2006081092A3 (en) | Deterministic microcontroller with configurable input/output interface | |
WO2006118644A3 (en) | Logic threshold acquisition circuits and methods using reversed peak detectors | |
WO2006004705A3 (en) | Dynamic-to-static logic converter | |
WO2003021497A3 (en) | Generating a logic design | |
AU4035800A (en) | Adaptive integrated circuit design simulation transistor modeling and evaluation | |
Brownlie | Where are we now, and what does the future hold? |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 172142 Country of ref document: IL |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2527970 Country of ref document: CA Ref document number: 2004250685 Country of ref document: AU |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2469/KOLNP/2005 Country of ref document: IN |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2004755597 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1020057024285 Country of ref document: KR Ref document number: 2006517391 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2004817196X Country of ref document: CN |
|
ENP | Entry into the national phase |
Ref document number: 2004250685 Country of ref document: AU Date of ref document: 20040618 Kind code of ref document: A |
|
WWP | Wipo information: published in national office |
Ref document number: 2004250685 Country of ref document: AU |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2006100275 Country of ref document: RU |
|
WWP | Wipo information: published in national office |
Ref document number: 2004755597 Country of ref document: EP |