WO2004109773A3 - Method and system for heating a substrate using a plasma - Google Patents

Method and system for heating a substrate using a plasma Download PDF

Info

Publication number
WO2004109773A3
WO2004109773A3 PCT/US2004/014757 US2004014757W WO2004109773A3 WO 2004109773 A3 WO2004109773 A3 WO 2004109773A3 US 2004014757 W US2004014757 W US 2004014757W WO 2004109773 A3 WO2004109773 A3 WO 2004109773A3
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
plasma
heating
temperature
gas
Prior art date
Application number
PCT/US2004/014757
Other languages
French (fr)
Other versions
WO2004109773A2 (en
Inventor
Lee Chen
Hiromitsu Kambara
Nobuhiro Iwama
Original Assignee
Tokyo Electron Ltd
Lee Chen
Hiromitsu Kambara
Nobuhiro Iwama
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd, Lee Chen, Hiromitsu Kambara, Nobuhiro Iwama filed Critical Tokyo Electron Ltd
Priority to JP2006532962A priority Critical patent/JP2007502547A/en
Publication of WO2004109773A2 publication Critical patent/WO2004109773A2/en
Publication of WO2004109773A3 publication Critical patent/WO2004109773A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching

Abstract

A method for heating a substrate between a first process and a second process using a plasma is described. The heating method comprises thermally isolating the substrate on the substrate holder by removing the backside supply of a heat transfer gas and removing the clamping force. Furthermore, an inert gas, such as a Noble gas, is introduced to the plasma processing system and a plasma is ignited. The substrate is exposed to the inert plasma for a period of time sufficient to elevate the temperature of the substrate from a first temperature (i.e., typically less than 100 C) to a second temperature (i.e., typically of order 400 C).
PCT/US2004/014757 2003-05-30 2004-05-11 Method and system for heating a substrate using a plasma WO2004109773A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006532962A JP2007502547A (en) 2003-05-30 2004-05-11 Method and system for etching a HIGH-K dielectric material.

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US47422503P 2003-05-30 2003-05-30
US47422403P 2003-05-30 2003-05-30
US60/474,225 2003-05-30
US60/474,224 2003-05-30

Publications (2)

Publication Number Publication Date
WO2004109773A2 WO2004109773A2 (en) 2004-12-16
WO2004109773A3 true WO2004109773A3 (en) 2005-07-14

Family

ID=33514014

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/US2004/014757 WO2004109773A2 (en) 2003-05-30 2004-05-11 Method and system for heating a substrate using a plasma
PCT/US2004/014610 WO2004109772A2 (en) 2003-05-30 2004-05-11 Method and system for etching a high-k dielectric material

Family Applications After (1)

Application Number Title Priority Date Filing Date
PCT/US2004/014610 WO2004109772A2 (en) 2003-05-30 2004-05-11 Method and system for etching a high-k dielectric material

Country Status (5)

Country Link
US (2) US7709397B2 (en)
EP (1) EP1629529A2 (en)
JP (2) JP4723503B2 (en)
KR (1) KR101037308B1 (en)
WO (2) WO2004109773A2 (en)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7217665B2 (en) 2002-11-20 2007-05-15 Applied Materials, Inc. Method of plasma etching high-K dielectric materials with high selectivity to underlying layers
JP2006501651A (en) * 2002-09-27 2006-01-12 東京エレクトロン株式会社 Method and system for etching high-k dielectric materials
US20050136681A1 (en) * 2003-12-23 2005-06-23 Tokyo Electron Limited Method and apparatus for removing photoresist from a substrate
US20060019451A1 (en) * 2004-07-22 2006-01-26 Jeng-Huey Hwang Method for patterning hfo2-containing dielectric
JP4515956B2 (en) * 2005-05-02 2010-08-04 株式会社日立ハイテクノロジーズ Sample etching method
JP4725232B2 (en) * 2005-08-02 2011-07-13 セイコーエプソン株式会社 Manufacturing method of liquid crystal panel
US7964512B2 (en) * 2005-08-22 2011-06-21 Applied Materials, Inc. Method for etching high dielectric constant materials
US20070056925A1 (en) * 2005-09-09 2007-03-15 Lam Research Corporation Selective etch of films with high dielectric constant with H2 addition
US7780862B2 (en) * 2006-03-21 2010-08-24 Applied Materials, Inc. Device and method for etching flash memory gate stacks comprising high-k dielectric
US8722547B2 (en) 2006-04-20 2014-05-13 Applied Materials, Inc. Etching high K dielectrics with high selectivity to oxide containing layers at elevated temperatures with BC13 based etch chemistries
JP2009021584A (en) * 2007-06-27 2009-01-29 Applied Materials Inc High temperature etching method of high k material gate structure
US7967995B2 (en) * 2008-03-31 2011-06-28 Tokyo Electron Limited Multi-layer/multi-input/multi-output (MLMIMO) models and method for using
KR101566029B1 (en) * 2008-04-10 2015-11-05 램 리써치 코포레이션 Selective etch of high-k dielectric material
US8313661B2 (en) * 2009-11-09 2012-11-20 Tokyo Electron Limited Deep trench liner removal process
JP5434970B2 (en) 2010-07-12 2014-03-05 セントラル硝子株式会社 Dry etchant
US8808562B2 (en) 2011-09-12 2014-08-19 Tokyo Electron Limited Dry metal etching method
US9660182B2 (en) * 2012-04-26 2017-05-23 Tokyo Electron Limited Plasma processing method and plasma processing apparatus
GB201305674D0 (en) * 2013-03-28 2013-05-15 Spts Technologies Ltd Method and apparatus for processing a semiconductor workpiece
JP6211947B2 (en) * 2013-07-31 2017-10-11 東京エレクトロン株式会社 Manufacturing method of semiconductor device
JP6130313B2 (en) * 2014-02-26 2017-05-17 Ｓｐｐテクノロジーズ株式会社 Plasma etching method
JP6604738B2 (en) * 2015-04-10 2019-11-13 東京エレクトロン株式会社 Plasma etching method, pattern forming method, and cleaning method
JP6567487B2 (en) * 2016-11-28 2019-08-28 Ｓｐｐテクノロジーズ株式会社 Plasma etching method
US11189464B2 (en) * 2019-07-17 2021-11-30 Beijing E-town Semiconductor Technology Co., Ltd. Variable mode plasma chamber utilizing tunable plasma potential

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998044543A1 (en) * 1997-03-31 1998-10-08 Lam Research Corporation Method for microwave plasma substrate heating
US6217658B1 (en) * 1997-06-03 2001-04-17 Applied Materials, Inc. Sequencing of the recipe steps for the optimal low-dielectric constant HDP-CVD Processing

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5374576A (en) * 1988-12-21 1994-12-20 Hitachi, Ltd. Method of fabricating stacked capacitor cell memory devices
US5225036A (en) * 1988-03-28 1993-07-06 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US5776356A (en) * 1994-07-27 1998-07-07 Sharp Kabushiki Kaisha Method for etching ferroelectric film
JPH08236503A (en) * 1995-02-27 1996-09-13 Toshiba Corp Selective etching method for aluminum oxide thin film
US5827437A (en) * 1996-05-17 1998-10-27 Lam Research Corporation Multi-step metallization etch
US6322714B1 (en) * 1997-11-12 2001-11-27 Applied Materials Inc. Process for etching silicon-containing material on substrates
DE19856082C1 (en) * 1998-12-04 2000-07-27 Siemens Ag Process for structuring a metal-containing layer
JP2001077059A (en) * 1999-09-07 2001-03-23 Sanyo Electric Co Ltd Processing of metallic oxide film
US6849305B2 (en) * 2000-04-28 2005-02-01 Ekc Technology, Inc. Photolytic conversion process to form patterned amorphous film
US6878402B2 (en) * 2000-12-06 2005-04-12 Novellus Systems, Inc. Method and apparatus for improved temperature control in atomic layer deposition
US6709609B2 (en) * 2000-12-22 2004-03-23 Applied Materials Inc. Plasma heating of a substrate with subsequent high temperature etching
US6740601B2 (en) * 2001-05-11 2004-05-25 Applied Materials Inc. HDP-CVD deposition process for filling high aspect ratio gaps
US6962679B2 (en) * 2001-07-11 2005-11-08 Battelle Memorial Institute Processes and apparatuses for treating halogen-containing gases
JP3990881B2 (en) 2001-07-23 2007-10-17 株式会社日立製作所 Semiconductor manufacturing apparatus and cleaning method thereof
JP2003059906A (en) * 2001-07-31 2003-02-28 Applied Materials Inc Etching method, and method of forming capacitor
US6528328B1 (en) * 2001-12-21 2003-03-04 Texas Instruments Incorporated Methods of preventing reduction of irox during PZT formation by metalorganic chemical vapor deposition or other processing
US6806095B2 (en) * 2002-03-06 2004-10-19 Padmapani C. Nallan Method of plasma etching of high-K dielectric materials with high selectivity to underlying layers
US7217665B2 (en) * 2002-11-20 2007-05-15 Applied Materials, Inc. Method of plasma etching high-K dielectric materials with high selectivity to underlying layers
US6451647B1 (en) * 2002-03-18 2002-09-17 Advanced Micro Devices, Inc. Integrated plasma etch of gate and gate dielectric and low power plasma post gate etch removal of high-K residual
US7357138B2 (en) * 2002-07-18 2008-04-15 Air Products And Chemicals, Inc. Method for etching high dielectric constant materials and for cleaning deposition chambers for high dielectric constant materials
US20040011380A1 (en) * 2002-07-18 2004-01-22 Bing Ji Method for etching high dielectric constant materials and for cleaning deposition chambers for high dielectric constant materials
US6833325B2 (en) * 2002-10-11 2004-12-21 Lam Research Corporation Method for plasma etching performance enhancement
US20050176191A1 (en) * 2003-02-04 2005-08-11 Applied Materials, Inc. Method for fabricating a notched gate structure of a field effect transistor
US6746925B1 (en) * 2003-03-25 2004-06-08 Lsi Logic Corporation High-k dielectric bird's beak optimizations using in-situ O2 plasma oxidation
US20040209468A1 (en) * 2003-04-17 2004-10-21 Applied Materials Inc. Method for fabricating a gate structure of a field effect transistor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998044543A1 (en) * 1997-03-31 1998-10-08 Lam Research Corporation Method for microwave plasma substrate heating
US6217658B1 (en) * 1997-06-03 2001-04-17 Applied Materials, Inc. Sequencing of the recipe steps for the optimal low-dielectric constant HDP-CVD Processing

Also Published As

Publication number Publication date
US20050164511A1 (en) 2005-07-28
JP2007502547A (en) 2007-02-08
US7709397B2 (en) 2010-05-04
KR101037308B1 (en) 2011-05-27
WO2004109773A2 (en) 2004-12-16
EP1629529A2 (en) 2006-03-01
US20050118353A1 (en) 2005-06-02
KR20060028636A (en) 2006-03-30
WO2004109772A2 (en) 2004-12-16
JP2007501533A (en) 2007-01-25
JP4723503B2 (en) 2011-07-13
WO2004109772A3 (en) 2005-04-14

Similar Documents

Publication Publication Date Title
WO2004109773A3 (en) Method and system for heating a substrate using a plasma
WO2004082820A3 (en) Processing system and method for chemically treating a substrate
WO2005006400A3 (en) Substrate support having dynamic temperature control
WO1999054908A8 (en) Crystalline gas distributor for semiconductor plasma etch chamber
WO2004025710A3 (en) Method of heating a substrate in a variable temperature process using a fixed temperature chuck
EP1209251A3 (en) Temperature control system for wafer
AU2003221961A1 (en) Process and system for heating semiconductor substrates in a processing chamber containing a susceptor
AU2001253890A1 (en) Methods and apparatus for thermally processing wafers
WO2003060184A8 (en) Method and apparatus for forming silicon containing films
WO2007021520A3 (en) Substrate support for increasing substrate temperature in plasma reactors
WO2003081646A3 (en) System and method for heating and cooling wafer at accelerated rates
WO2002093623A3 (en) Assembly comprising heat distributing plate and edge support
WO2002056349A3 (en) Chamber for uniform substrate heating
AU2001247537A1 (en) Method for improving uniformity and reducing etch rate variation of etching polysilicon
EP0747505A3 (en) Apparatus and method for depositing a substance with temperature control
TW200501254A (en) Method for removing silicon oxide film and processing apparatus
EP0214515A3 (en) Method and apparatus for forming metal silicide
TW373251B (en) Arrangement for processing a substrate wafer and operating method thereof
TW375764B (en) Method for recovering object to be treated
TW329017B (en) Method for forming dielectric film
TW200715397A (en) Low-temperature oxide removal using fluorine
WO2004036627A3 (en) Plasma system and method for anistropically etching structures into a substrate
AU2001250604A1 (en) Method and apparatus for temperature controlled vapor deposition on a substrate
WO2003043751A8 (en) An apparatus and method for cleaning glass substrates using a cool hydrogen flame
WO2002082522A1 (en) Single wafer processing method and system for processing semiconductor

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2006532962

Country of ref document: JP

122 Ep: pct application non-entry in european phase