WO2004109772A3 - Method and system for etching a high-k dielectric material - Google Patents

Method and system for etching a high-k dielectric material Download PDF

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Publication number
WO2004109772A3
WO2004109772A3 PCT/US2004/014610 US2004014610W WO2004109772A3 WO 2004109772 A3 WO2004109772 A3 WO 2004109772A3 US 2004014610 W US2004014610 W US 2004014610W WO 2004109772 A3 WO2004109772 A3 WO 2004109772A3
Authority
WO
WIPO (PCT)
Prior art keywords
etching
substrate
process gas
plasma
gas
Prior art date
Application number
PCT/US2004/014610
Other languages
French (fr)
Other versions
WO2004109772A2 (en
Inventor
Lee Chen
Hiromitsu Kambara
Nobuhiro Iwama
Meiki Koh
Hiromasa Mochiki
Masaaki Hagihara
Original Assignee
Tokyo Electron Ltd
Lee Chen
Hiromitsu Kambara
Nobuhiro Iwama
Meiki Koh
Hiromasa Mochiki
Masaaki Hagihara
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd, Lee Chen, Hiromitsu Kambara, Nobuhiro Iwama, Meiki Koh, Hiromasa Mochiki, Masaaki Hagihara filed Critical Tokyo Electron Ltd
Priority to EP04751808A priority Critical patent/EP1629529A2/en
Priority to JP2006532925A priority patent/JP4723503B2/en
Publication of WO2004109772A2 publication Critical patent/WO2004109772A2/en
Publication of WO2004109772A3 publication Critical patent/WO2004109772A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3

Abstract

A method for etching a high-k dielectric layer on a substrate in a plasma processing system is described. The high-k dielectric layer can, for example, comprise HfO2. The method comprises elevating the temperature of the substrate above 200 C (i.e., typically of order 400 C), introducing a process gas comprising a halogen-containing gas, igniting a plasma from the process gas, and exposing the substrate to the plasma. The process gas can further include a reduction gas in order to improve the etch rate of HfO2 relative to Si and SiO2.
PCT/US2004/014610 2003-05-30 2004-05-11 Method and system for etching a high-k dielectric material WO2004109772A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP04751808A EP1629529A2 (en) 2003-05-30 2004-05-11 Method and system for etching a high-k dielectric material
JP2006532925A JP4723503B2 (en) 2003-05-30 2004-05-11 Method and system for etching high-k dielectric materials

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US47422503P 2003-05-30 2003-05-30
US47422403P 2003-05-30 2003-05-30
US60/474,224 2003-05-30
US60/474,225 2003-05-30

Publications (2)

Publication Number Publication Date
WO2004109772A2 WO2004109772A2 (en) 2004-12-16
WO2004109772A3 true WO2004109772A3 (en) 2005-04-14

Family

ID=33514014

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/US2004/014757 WO2004109773A2 (en) 2003-05-30 2004-05-11 Method and system for heating a substrate using a plasma
PCT/US2004/014610 WO2004109772A2 (en) 2003-05-30 2004-05-11 Method and system for etching a high-k dielectric material

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PCT/US2004/014757 WO2004109773A2 (en) 2003-05-30 2004-05-11 Method and system for heating a substrate using a plasma

Country Status (5)

Country Link
US (2) US20050118353A1 (en)
EP (1) EP1629529A2 (en)
JP (2) JP2007502547A (en)
KR (1) KR101037308B1 (en)
WO (2) WO2004109773A2 (en)

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AU2003272656A1 (en) * 2002-09-27 2004-04-19 Tokyo Electron Limited A method and system for etching high-k dielectric materials
US20050136681A1 (en) * 2003-12-23 2005-06-23 Tokyo Electron Limited Method and apparatus for removing photoresist from a substrate
US20060019451A1 (en) * 2004-07-22 2006-01-26 Jeng-Huey Hwang Method for patterning hfo2-containing dielectric
JP4515956B2 (en) * 2005-05-02 2010-08-04 株式会社日立ハイテクノロジーズ Sample etching method
JP4725232B2 (en) * 2005-08-02 2011-07-13 セイコーエプソン株式会社 Manufacturing method of liquid crystal panel
US7964512B2 (en) 2005-08-22 2011-06-21 Applied Materials, Inc. Method for etching high dielectric constant materials
US20070056925A1 (en) * 2005-09-09 2007-03-15 Lam Research Corporation Selective etch of films with high dielectric constant with H2 addition
US7780862B2 (en) * 2006-03-21 2010-08-24 Applied Materials, Inc. Device and method for etching flash memory gate stacks comprising high-k dielectric
US8722547B2 (en) 2006-04-20 2014-05-13 Applied Materials, Inc. Etching high K dielectrics with high selectivity to oxide containing layers at elevated temperatures with BC13 based etch chemistries
JP2009021584A (en) * 2007-06-27 2009-01-29 Applied Materials Inc High temperature etching method of high k material gate structure
US7967995B2 (en) * 2008-03-31 2011-06-28 Tokyo Electron Limited Multi-layer/multi-input/multi-output (MLMIMO) models and method for using
KR101566029B1 (en) * 2008-04-10 2015-11-05 램 리써치 코포레이션 Selective etch of high-k dielectric material
US8313661B2 (en) * 2009-11-09 2012-11-20 Tokyo Electron Limited Deep trench liner removal process
JP5434970B2 (en) 2010-07-12 2014-03-05 セントラル硝子株式会社 Dry etchant
US8808562B2 (en) 2011-09-12 2014-08-19 Tokyo Electron Limited Dry metal etching method
JP6096762B2 (en) * 2012-04-26 2017-03-15 東京エレクトロン株式会社 Plasma processing method and plasma processing apparatus
GB201305674D0 (en) * 2013-03-28 2013-05-15 Spts Technologies Ltd Method and apparatus for processing a semiconductor workpiece
JP6211947B2 (en) * 2013-07-31 2017-10-11 東京エレクトロン株式会社 Manufacturing method of semiconductor device
JP6130313B2 (en) * 2014-02-26 2017-05-17 Ｓｐｐテクノロジーズ株式会社 Plasma etching method
JP6604738B2 (en) * 2015-04-10 2019-11-13 東京エレクトロン株式会社 Plasma etching method, pattern forming method, and cleaning method
JP6567487B2 (en) * 2016-11-28 2019-08-28 Ｓｐｐテクノロジーズ株式会社 Plasma etching method
US11189464B2 (en) * 2019-07-17 2021-11-30 Beijing E-town Semiconductor Technology Co., Ltd. Variable mode plasma chamber utilizing tunable plasma potential

Citations (7)

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US5225036A (en) * 1988-03-28 1993-07-06 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US5776356A (en) * 1994-07-27 1998-07-07 Sharp Kabushiki Kaisha Method for etching ferroelectric film
US6511918B2 (en) * 1998-12-04 2003-01-28 Infineon Technologies Ag Method of structuring a metal-containing layer
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EP1422751A2 (en) * 2002-11-20 2004-05-26 Applied Materials, Inc. Method of plasma etching high-K dielectric materials with high selectivity to underlying layers
EP1469510A2 (en) * 2003-04-17 2004-10-20 Applied Materials, Inc. Method for fabricating a gate structure of a field effect transistor

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US5225036A (en) * 1988-03-28 1993-07-06 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US5776356A (en) * 1994-07-27 1998-07-07 Sharp Kabushiki Kaisha Method for etching ferroelectric film
US6511918B2 (en) * 1998-12-04 2003-01-28 Infineon Technologies Ag Method of structuring a metal-containing layer
US6528328B1 (en) * 2001-12-21 2003-03-04 Texas Instruments Incorporated Methods of preventing reduction of irox during PZT formation by metalorganic chemical vapor deposition or other processing
US20030170986A1 (en) * 2002-03-06 2003-09-11 Applied Materials, Inc. Method of plasma etching of high-K dielectric materials with high selectivity to underlying layers
EP1422751A2 (en) * 2002-11-20 2004-05-26 Applied Materials, Inc. Method of plasma etching high-K dielectric materials with high selectivity to underlying layers
EP1469510A2 (en) * 2003-04-17 2004-10-20 Applied Materials, Inc. Method for fabricating a gate structure of a field effect transistor

Non-Patent Citations (1)

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Title
NORASETTHEKUL S ET AL: "Etch characteristics of HfO2 films on Si substrates", APPLIED SURFACE SCIENCE, ELSEVIER, AMSTERDAM, NL, vol. 187, no. 1-2, 14 February 2002 (2002-02-14), pages 75 - 81, XP002221366, ISSN: 0169-4332 *

Also Published As

Publication number Publication date
JP4723503B2 (en) 2011-07-13
JP2007501533A (en) 2007-01-25
WO2004109772A2 (en) 2004-12-16
EP1629529A2 (en) 2006-03-01
KR20060028636A (en) 2006-03-30
JP2007502547A (en) 2007-02-08
US7709397B2 (en) 2010-05-04
US20050164511A1 (en) 2005-07-28
WO2004109773A2 (en) 2004-12-16
KR101037308B1 (en) 2011-05-27
US20050118353A1 (en) 2005-06-02
WO2004109773A3 (en) 2005-07-14

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