WO2004109770A2 - Through wafer via process and amplifier with through wafer via - Google Patents
Through wafer via process and amplifier with through wafer via Download PDFInfo
- Publication number
- WO2004109770A2 WO2004109770A2 PCT/DK2004/000367 DK2004000367W WO2004109770A2 WO 2004109770 A2 WO2004109770 A2 WO 2004109770A2 DK 2004000367 W DK2004000367 W DK 2004000367W WO 2004109770 A2 WO2004109770 A2 WO 2004109770A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- wafer
- deposition
- deposited
- cmos
- hole
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
Definitions
- the invention concerns a process for generating a feed-through in a semiconductor wafer, which has electric circuitry embedded in a first surface.
- the embedded circuitry could be a CMOS or similar electronic device.
- the invention further concerns an amplifier comprising electric circuitry embedded in a first side of a semiconductor wafer and a feed-through from the first to a second side of the semiconductorwafer
- Amplifiers are produced on wafers and singulated after production. It has been proposed to mount separate electronic components directly on the wafer prior to singulation of the individual amplifiers. This technique is space saving as it becomes possible to omit the printed circuit board, as all components for driving the amplifier can be placed on the surface of the integrated circuit embedded in the silicon wafer. In some cases it is a problem to provide sufficient space also for the bond pads for in/out signals and for power supply for the IC on the surface when also the electric components are placed here. In this case it would be advantageous to be able to either place the bond pads or the electric components on the opposite side of the silicon wafer with the embedded IC. This requires electric leads or vias connecting the two sides of the semiconductor wafer.
- a feed-through or a via In the following such an electric conducting path leading through the wafer material from one to the other side thereof is called a feed-through or a via.
- the via or feed-through comprises a hole all the way through the wafer material, an insulation layer covering the inside surface of the hole and electrically conducting material preferably metal. In this way an electrically leading path from the one to the other side of the wafer is created which is electrically isolated from the other parts of the wafer.
- CMOS chip stacking or stacking of various types of microcomponents directly on for example a CMOS chip.
- the latter implies the possibility of stacking e.g. MEMS- devices on CMOS chips in order to provide the often needed direct conditioning of the
- MEMS device output signal If through- wafer vias is applied in combination with wafer level packaging, fabrication of ultra small 3-D packages containing several active devices is possible. Ultimately this 3-D package could represent a complete microsystem that could be surface mounted as a ball grid array (BGA) using solder bumps.
- BGA ball grid array
- the purpose of the invention it to present a simple process for post processing of high aspect ratio through-wafer vias in CMOS wafers.
- a process for through-wafer via fabrication is suggested, that has a realistic chance of being successfully implemented in a high-end portable product.
- the leading thoughts behind the process design is to create a process sequence containing as few critical process steps as possible, and to create a process sequence that is relatively insensitive to process variations and non-uniformities.
- the resulting process design according to the invention allows great latitude in the choice of parameters for the individual process steps, thus lightening the task of transferring the final process from development to production facility.
- the through-wafer via process presented is designed to be applicable as a post process to any kind of CMOS wafer regardless of the type of passivation provided by the CMOS foundry (usually silicon oxide, silicon nitride or polyimide).
- the thermal budget of a CMOS compatible process is rather limited, i.e. normally below ⁇ 450°C (above this approximate temperature the CMOS Al metallization will start diffusing into the silicon, thus causing non-functional circuits).
- the thermal budget is reduced even further.
- the highest process temperature has been kept at 300°C.
- the process developed offers simple but well controlled through-wafer via formation eliminating common problems like notching and poor distribution of via metallization and insulation material.
- the fast Si-DRTE process offers high etch rates in the range of 6 ⁇ m/min. depending on actual loading, feature sizes and etch depth.
- Fig. 1 is a 3-D illustration of a final through- wafer via providing electrical contact from a CMOS pad on the front side of the chip to a redistribution network on the backside.
- Fig. 2 is a simplified process sequence for processing of a through- wafer via in a CMOS wafer.
- Fig. 3 is a cross sectional illustration of a through- wafer via fabricated using a metal layer provided as an inherent part of the CMOS wafer as an etch stop.
- the through-wafer via process presented is designed to be applicable as a post process to any kind of CMOS wafer regardless of the type of passivation provided by the CMOS foundry (usually silicon oxide, silicon nitride or polyimide).
- CMOS foundry usually silicon oxide, silicon nitride or polyimide.
- the thermal budget of a CMOS compatible process is rather limited, i.e. normally below ⁇ 450°C (above this approximate temperature the CMOS Al metallization will start diffusing into the silicon, thus causing non-functional circuits).
- the thermal budget is reduced even further.
- the highest process temperature has been kept at 300°C.
- the process developed offers simple but well controlled through-wafer via formation eliminating common problems like notching and poor distribution of via metallization and insulation material.
- the process is based on fast Si-DRIE of wafer through-holes, low temperature deposition of through-hole insulation, double sided sputtering of Cr/Au, and electroless deposition of Cu.
- the fast Si-DRIE process offers high etch rates in the range of 6 ⁇ m/min. depending on actual loading, feature sizes and etch depth.
- FIG. 1 A 3-D illustration of a final through- wafer via is shown in Figure 1.
- the process sequence is applied directly on the CMOS wafer 1 as provided by the CMOS foundry (backlapped). Initially a protective PECVD silicon nitride layer 2 is deposited on the front side of the wafer ( Figure 2, a). The CMOS wafer 1 is then chemical mechanical polished (CMP) in order to obtain a smooth and defect free surface suitable for further processing. The protective PECVD nitride 2 covering the entire front surface has to be opened above the CMOS contact pads 3 in order to allow subsequent deposited metal layers to make electrical contact to the pads 3. The PECVD nitride 2 is patterned in a reactive ion etching (RIE) process using a suitable photoresist mask.
- RIE reactive ion etching
- a sacrificial Al layer 4 is sputter deposited on the backside of the wafer ( Figure 2, b) in order to provide an etch stop for the DRIE formation of the wafer through-holes ( Figure 2, d). Additionally, the Al etch stop 4 functions as a membrane preventing He leaking into the process chamber once the wafer 1 through-holes are formed (He is used for wafer cooling during Si-DRIE). In present case an Al thickness of 2 ⁇ m has been chosen in order to provide a sufficient mechanically stable etch stop layer. Other materials than Al can be used for the purpose of a conductive etch stop layer. The choice of material may depend on the specific rules and requirements of the production facility.
- the etch stop layer can be provided as an inherent part of the CMOS wafer such as a bond pad or as a buried metal layer ( Figure 3, 20).
- DRJE formation of the via holes will be performed from the backside of the CMOS wafer using a bond pad or a buried metal layer near the CMOS wafer front surface as an etch stop. In this case removal of a sacrificial etch stop layer can be avoided.
- a thick photoresist layer 5 (9.5 ⁇ m) is deposited on the front side of the wafer 1.
- the photoresist 5 is patterned to define circular openings 6 with a diameter of 100 ⁇ m.
- the PECVD silicon nitride 2 is then patterned correspondingly using RIE with the photoresist acting as a mask ( Figure 2-c).
- the wafer through-holes 7 are formed in a room temperature Si-DRTE process ( Figure 2, d) using alternating gas chemistry; SF 6 for Si etching and C F 8 for intermediate passivation (BOSCH process).
- the Si-DRIE process terminates on the Al layer 4 on the backside of the wafer 1 without deteriorating the profile of the wafer through-hole 7, i.e. without notching effects.
- the sacrificial Al etch stop layer 4 is etched using a mixture of phosphoric, acetic and nitric acid.
- the resulting etch rate is approximately 0.2 ⁇ m/min.
- the wafer through-holes 7 are insulated by room temperature CVD of 3 ⁇ m Parylene C (poly-monochloro-para-xylylene) 8 ( Figure 2,e).
- the Parylene C CVD process is characterized by the ability to coat the entire wafer conformably in one process step.
- the simultaneous coating of wafer front, backside and inside of wafer through-holes provides an efficient insulation of the final via.
- the wafer through-holes can be insulated using a low temperature CVD process for deposition of a silicon based dielectric material such as silicon oxide, silicon nitride or silicon oxynitride.
- the preferred alternative to CVD deposited parylene is PECVD deposition of silicon oxide based on a TEOS precursor.
- the Parylene 8 deposited on the CMOS contact pads 3 on the wafer front side is removed in a RIE process using a standard photoresist layer as a mask ( Figure 2, e).
- the small lateral dimension of the via holes 7 combined with the mild resolution requirement (only definition of large feature sizes is needed) allows for spinning of photoresist in a standard photoresist spinner.
- the Parylene surface Prior to deposition of the through-hole metallization the Parylene surface is treated in a mild oxygen plasma in order to improve the conditions for obtaining good metal adhesion.
- the through-hole metallization is deposited immediately after the plasma treatment.
- a plating base 9 consisting of 500 nm Cr and 500 nm Au is sputter deposited on both sides of the wafer ( Figure 2-f).
- a thick Cu- layer 10 is deposited (3-5 ⁇ m).
- the Cu 10 is deposited in an electroless process using the sputter deposited Cr/Au as a seed layer ( Figure 2-g), i.e. simultaneous deposition on both sides of the wafer and inside the wafer through-holes.
- the through-hole metallization is deposited by means of low temperature metal organic chemical vapour deposition (MOCVD).
- MOCVD TiN is deposited as an adhesion layer providing good adhesion to the through-hole insulation material, and MOCVD Cu is subsequently deposited in order to provide low electrical resistance of the through wafer via.
- MOCVD TiN and MOCVD Cu process can be followed by electrochemical deposition of Cu in order to further increase the via metal thickness and thereby further decrease the electrical resistance of the through- wafer via.
- electrochemical deposition of Cu is either performed as an electroless process or as a pulse reverse plating process.
- an electrodeposited, negatively working photoresist 11 is applied.
- a DC voltage across the Cr/Au/Cu metallization the resist is uniformly deposited all over the wafer (including inside of wafer through-holes) in a cataphoretic electrodeposition process taking place at 35°C ( Figure 2-h).
- This type of resist is not widely used within the field of MEMS, though it is well known in the printed circuit board (PCB) industry as it is originally developed for patterning of Cu wires on PCB.
- PCB printed circuit board
- Using a standard mask aligner the front and backside of the photoresist coated wafer is exposed, and the electrodeposited resist is subsequently developed in a dedicated developer.
- an electrodeposited, positively working photoresist can be used, however the negative tone photoresist is preferred as it is more chemically stable.
- the through- wafer via metallization is structured by wet chemical etching using the electrodeposited photoresist as an etch mask ( Figure 2-i).
- the Cu metal is etched using a sodium persulfate solution, whereas the underlying Cr/Au base layer is sequentially etched using commercial Au and Cr etchants, which are both Cu compatible.
- the electrodeposited photoresist mould is stripped using a dedicated remover ( Figure 2- j).
- the passivation layer protects the through wafer via from corrosion and wear.
- the deposited passivation material has to be patterned above input/output terminals in order to allow for external electrical contact to the CMOS chip with integrated vias. Additionally the passivation layer can have a vital function in the packaging of the device.
- the passivation layer can e.g. function as a construction material in the process of fabricating solder bumps.
- the passivation layer can be provided by spinning of a polymer material such as BCB (benzocyclobutene) or preferably by CVD deposition of parylene.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
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Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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DKPA200300832 | 2003-06-05 | ||
DKPA200300832 | 2003-06-05 |
Publications (2)
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WO2004109770A2 true WO2004109770A2 (en) | 2004-12-16 |
WO2004109770A3 WO2004109770A3 (en) | 2005-02-03 |
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PCT/DK2004/000367 WO2004109770A2 (en) | 2003-06-05 | 2004-05-26 | Through wafer via process and amplifier with through wafer via |
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Cited By (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1693891A2 (en) * | 2005-01-31 | 2006-08-23 | Interuniversitair Micro-Elektronica Centrum (IMEC) | Method of manufacturing a semiconductor device |
US7442635B2 (en) | 2005-01-31 | 2008-10-28 | Interuniversitair Microelektronica Centrum (Imec) | Method for producing a semiconductor device and resulting device |
US7683458B2 (en) | 2004-09-02 | 2010-03-23 | Micron Technology, Inc. | Through-wafer interconnects for photoimager and memory wafers |
US7749899B2 (en) | 2006-06-01 | 2010-07-06 | Micron Technology, Inc. | Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces |
US7759800B2 (en) | 2003-11-13 | 2010-07-20 | Micron Technology, Inc. | Microelectronics devices, having vias, and packaged microelectronic devices having vias |
US7795134B2 (en) | 2005-06-28 | 2010-09-14 | Micron Technology, Inc. | Conductive interconnect structures and formation methods using supercritical fluids |
US7830018B2 (en) | 2007-08-31 | 2010-11-09 | Micron Technology, Inc. | Partitioned through-layer via and associated systems and methods |
US7829976B2 (en) | 2004-06-29 | 2010-11-09 | Micron Technology, Inc. | Microelectronic devices and methods for forming interconnects in microelectronic devices |
US7863187B2 (en) | 2005-09-01 | 2011-01-04 | Micron Technology, Inc. | Microfeature workpieces and methods for forming interconnects in microfeature workpieces |
US7884015B2 (en) | 2007-12-06 | 2011-02-08 | Micron Technology, Inc. | Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods |
US7902643B2 (en) | 2006-08-31 | 2011-03-08 | Micron Technology, Inc. | Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods |
US7915736B2 (en) | 2005-09-01 | 2011-03-29 | Micron Technology, Inc. | Microfeature workpieces and methods for forming interconnects in microfeature workpieces |
US7973411B2 (en) | 2006-08-28 | 2011-07-05 | Micron Technology, Inc. | Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods |
US8030780B2 (en) | 2008-10-16 | 2011-10-04 | Micron Technology, Inc. | Semiconductor substrates with unitary vias and via terminals, and associated systems and methods |
US8084866B2 (en) | 2003-12-10 | 2011-12-27 | Micron Technology, Inc. | Microelectronic devices and methods for filling vias in microelectronic devices |
CN102376629A (en) * | 2010-08-17 | 2012-03-14 | 中国科学院上海微系统与信息技术研究所 | Method for realizing through-silicon-via interconnection by suspension photoresist |
US8283237B2 (en) | 2010-12-22 | 2012-10-09 | Applied Materials, Inc. | Fabrication of through-silicon vias on silicon wafers |
US8322031B2 (en) | 2004-08-27 | 2012-12-04 | Micron Technology, Inc. | Method of manufacturing an interposer |
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US8466061B2 (en) | 2010-09-23 | 2013-06-18 | Infineon Technologies Ag | Method for forming a through via in a semiconductor element and semiconductor element comprising the same |
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