WO2004109765A3 - Compression of emulation trace data - Google Patents

Compression of emulation trace data Download PDF

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Publication number
WO2004109765A3
WO2004109765A3 PCT/US2004/017402 US2004017402W WO2004109765A3 WO 2004109765 A3 WO2004109765 A3 WO 2004109765A3 US 2004017402 W US2004017402 W US 2004017402W WO 2004109765 A3 WO2004109765 A3 WO 2004109765A3
Authority
WO
WIPO (PCT)
Prior art keywords
scan chains
compression
trace data
data
emulation
Prior art date
Application number
PCT/US2004/017402
Other languages
French (fr)
Other versions
WO2004109765A2 (en
Inventor
Charley Selvidge
Robert W Davis
Peer Schmitt
Joshua D Marantz
Original Assignee
Mentor Graphics Corp
Charley Selvidge
Robert W Davis
Peer Schmitt
Joshua D Marantz
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mentor Graphics Corp, Charley Selvidge, Robert W Davis, Peer Schmitt, Joshua D Marantz filed Critical Mentor Graphics Corp
Priority to JP2006515109A priority Critical patent/JP4215801B2/en
Priority to EP04754091.9A priority patent/EP1629380B1/en
Publication of WO2004109765A2 publication Critical patent/WO2004109765A2/en
Publication of WO2004109765A3 publication Critical patent/WO2004109765A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

A system and method for compressing trace data from an emulation system. Scan chains may receive trace data from configurable logic blocks (401) inside one or more emulation chips (201), and the data received from the scan chains may be compressed. Where delta compression (403a) is used, the scan chains may also perform a delta detection function. Alternatively, delta detection may be performed using the outputs of the scan chains. In addition, event detectors may be implemented within or outside of the scan chains. Compression of the trace data may include receiving a plurality of data sets and performing compression along cross-sections of the combined data sets.
PCT/US2004/017402 2003-06-05 2004-06-03 Compression of emulation trace data WO2004109765A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2006515109A JP4215801B2 (en) 2003-06-05 2004-06-03 Compression method of emulation trace data
EP04754091.9A EP1629380B1 (en) 2003-06-05 2004-06-03 Compression of emulation trace data

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/454,818 US8099273B2 (en) 2003-06-05 2003-06-05 Compression of emulation trace data
US10/454,818 2003-06-05

Publications (2)

Publication Number Publication Date
WO2004109765A2 WO2004109765A2 (en) 2004-12-16
WO2004109765A3 true WO2004109765A3 (en) 2005-12-01

Family

ID=33489798

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/017402 WO2004109765A2 (en) 2003-06-05 2004-06-03 Compression of emulation trace data

Country Status (4)

Country Link
US (2) US8099273B2 (en)
EP (1) EP1629380B1 (en)
JP (1) JP4215801B2 (en)
WO (1) WO2004109765A2 (en)

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JP2007305137A (en) * 2006-05-12 2007-11-22 Samsung Electronics Co Ltd Distributed simultaneous simulation
US7725304B1 (en) * 2006-05-22 2010-05-25 Cadence Design Systems, Inc. Method and apparatus for coupling data between discrete processor based emulation integrated chips
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US8121825B2 (en) * 2008-04-30 2012-02-21 Synopsys, Inc. Method and apparatus for executing a hardware simulation and verification solution
GB2466078B (en) * 2008-12-15 2013-11-13 Advanced Risc Mach Ltd Apparatus and method for tracing activities of a shader program executed on shader circuitry of a data processing apparatus
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US9495378B2 (en) 2013-08-27 2016-11-15 Purdue Research Foundation Tracing message transmissions between communications network devices
US9372947B1 (en) 2014-09-29 2016-06-21 Cadence Design Systems, Inc. Compacting trace data generated by emulation processors during emulation of a circuit design
US10073932B2 (en) * 2016-03-04 2018-09-11 Synopsys, Inc. Capturing time-slice of emulation data for offline embedded software debug
US10409624B1 (en) * 2016-03-08 2019-09-10 Cadence Design Systems, Inc. Data array compaction in an emulation system
US10715177B2 (en) * 2017-06-20 2020-07-14 Samsung Electronics Co., Ltd. Lossy compression drive
US10506079B2 (en) * 2017-09-14 2019-12-10 Arm Limited Packet compression
US11573883B1 (en) * 2018-12-13 2023-02-07 Cadence Design Systems, Inc. Systems and methods for enhanced compression of trace data in an emulation system

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Also Published As

Publication number Publication date
EP1629380A4 (en) 2011-05-18
WO2004109765A2 (en) 2004-12-16
US8099273B2 (en) 2012-01-17
JP4215801B2 (en) 2009-01-28
EP1629380B1 (en) 2018-09-12
US20040249623A1 (en) 2004-12-09
JP2007526442A (en) 2007-09-13
US20070083353A1 (en) 2007-04-12
EP1629380A2 (en) 2006-03-01

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