WO2004107352A2 - Use of voids between elements in semiconductor structures for isolation - Google Patents
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- WO2004107352A2 WO2004107352A2 PCT/US2004/013986 US2004013986W WO2004107352A2 WO 2004107352 A2 WO2004107352 A2 WO 2004107352A2 US 2004013986 W US2004013986 W US 2004013986W WO 2004107352 A2 WO2004107352 A2 WO 2004107352A2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- This invention relates generally to the isolation of tightly packed elements in semiconductor structures, and, more specifically, to the electric field isolation of neighboring charge storage elements of non-volatile flash electrically erasable and programmable read-only-memory (flash EEPROM) cell arrays.
- memory cells are connected between adjacent bit line source and drain diffusions that extend in a column direction with control gates connected to word lines extending along rows of cells.
- One common memory cell has a "split-channel" between source and drain diffusions.
- a charge storage element of the cell is positioned over one portion of the channel and the word line (also referred to as a control gate) is positioned over the other channel portion as well as over the charge storage element.
- the word line extends over a row of charge storage elements. Examples of such cells, their uses in memory systems and methods of manufacturing them are given in United States patents nos. 5,070,032, 5,095,344, 5,315,541, 5,343,063, 5,661,053, and 6,281,075.
- a modification of this split-channel flash EEPROM cell adds a steering gate positioned between the charge storage element and the word line.
- Each steering gate of an array extends over one column of charge storage elements, perpendicular to the word line. The effect is to relieve the word line from having to perform two functions at the same time when reading or programming a selected cell. Those two functions are (1) to serve as a gate of a select transistor, thus requiring a proper voltage to turn the select transistor on and off, and (2) to drive the voltage of the charge storage element to a desired level through an electric field (capacitive) coupling between the word line and the charge storage element. It is often difficult to perform both of these functions in an optimum manner with a single voltage. With the addition of the steering gate, the word line need only perform function (1), while the added steering gate performs function (2).
- the use of steering gates in a flash EEPROM array is described, for example, in United States patent nos. 5,313,421 and 6,222,762.
- NAND arrays In a second category of flash memory array architectures, generally referred to as NAND arrays, series strings of more than two memory cells, such as 16 or 32, are connected along with one or more select transistors between individual bit lines and a reference potential to form columns of cells. Word lines extend across cells within a large number of these columns. An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be turned on hard so that the current flowing through a string is dependent upon the level of charge stored in the addressed cell.
- An example of a NAND architecture array and its operation as part of a memory system is found in United States patents nos. 5,570,315, 5,774,397 and 6,046,935.
- flash EEPROM arrays As in most all integrated circuit applications, the pressure to shrink the silicon substrate area required to implement some integrated circuit function also exists with flash EEPROM arrays. It is continually desired to increase the amount of digital data that can be stored in a given area of a silicon substrate, in order to increase the storage capacity of a given size memory card and other types of packages, or to both increase capacity and decrease size.
- One way to increase the storage density of data is to store more than one bit of data per memory cell. This is accomplished by defining more than two threshold levels as storage states for each storage element transistor, four such states (2 bits of data per storage element) now being included in commercial products. More storage states, such as 8 states (3 data bits) and 16 states (4 data bits) per storage element, are contemplated.
- Each storage element memory transistor has a certain total range (window) of threshold voltages in which it may practically be operated, and that range is divided into the number of states defined for it plus margins between the states to allow for them to be clearly differentiated from one another.
- a multiple state flash EEPROM structure and operation is described in United States patents nos. 5,043,940 and 5,172,338, for example.
- Another type of memory cell includes two storage elements that may also be operated in multiple states on each storage element.
- two storage elements are included over its channel between source and drain diffusions with a select transistor in between them.
- a 'steering gate is included along each column of storage elements and a word line is provided thereover along each row of storage elements.
- the amount of current flowing through the cell is then a function of the amount of charge on the storage element of interest but not of the other storage element in the same cell. Examples of this cell array architecture and operating techniques are described in United States patents nos. 5,712,180, 6,103,573 and 6,151,248.
- a triple layer dielectric formed of silicon oxide, silicon nitride and silicon oxide (“ONO") is sandwiched between a conductive control gate and a surface of a semi-conductive substrate above the memory cell channel.
- the cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region. This stored charge then changes the threshold voltage of a portion of the channel of the cell in a manner that is detectable.
- the cell is erased by injecting hot holes into the nitride. See also Nozaki et al., "A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application," IEEE Journal of ' Solid-State Circuits, Vol. 26, No. 4, April 1991, pp. 497-501, which describes a similar cell in a split-gate configuration where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor.
- the effect of this parasitic capacitance between storage elements can be compensated by taking into account the effect of the charge on the second group of storage elements when reading that of the first group. Also, the effect may be reduced by physically isolating the two groups of storage elements from each other, such as by placing a conductive shield between the two groups.
- One way in which such shielding has been accomplished is to extend control gate lines, which run across either rows or columns of floating gates, downward between the floating gates.
- the parasitic capacitance between floating gates may be reduced by positioning a dielectric material between them, either in a solid or a non-solid form, which has a very low dielectric constant, but of course not less than 1.0.
- Another technique to reduce coupling between floating gates is to make them very thin so that their opposing surface areas are small.
- Isolation between adjacent charge storage elements is provided by forming a dielectric between them that contains a void extending a major part of the distance between the elements instead of the usual technique of making the dielectric solid throughout the entire space between charge storage elements.
- the void will usually contain the gas present in the processing chamber when the dielectric is formed.
- Such a gas has a dielectric constant of 1.0 or only a small amount above 1.0, depending upon its exact composition. This is considerably less than that of commonly used dielectric materials such as silicon dioxide, with a dielectric constant of about 4.0, depending upon the exact composition and method of formation, and silicon nitride with a dielectric constant of about 7.5. A significant reduction in the coupling between adjacent charge storage elements is thus achieved.
- this isolation is formed in spaces between floating gates at the bottom of stacks of layers having a height of five, eight or more times the width of the spaces between the stacks.
- the other layers in the stacks usually contain at least one dielectric and a conductive control gate line.
- This 5:1, 8:1 or more cross- sectional aspect ratio of the spaces between the stacks allows a dielectric to be formed that extends downward into the spaces along sidewalls of the stacks but not filling the bottom segments of the spaces between the charge storage elements. Top portions of the spaces are filled with the dielectric, however, thereby leaving large voids sealed in the dielectric between the charge storage elements.
- isolation techniques are applied to a wide variety of non- volatile memory cell arrays, such as those within the two categories described in the Background.
- control gate (word) lines extend over rows of floating gates and down between them, thereby providing shielding along the rows as well as desirably increasing the coupling between each of the word lines and the floating gates in its row.
- the dielectric with voids is then formed between the rows in order to reduce capacitive coupling between floating gates along the columns (i.e., along NAND strings of floating gate transistors).
- Another example use of the isolation techniques herein is with an ETOXTM array having alternate source and drain implants in one direction across the array, between which the individual charge floating gates are positioned.
- a conductor usually extends between the floating gates to contact every other implant region along each row of memory cells, and thus provide some shielding between the floating gates on either side of the conductor, the alternate spaces between floating gates over the remaining implant regions are very small.
- the dielectric with voids is used in these small spaces instead of the usual solid dielectric such as silicon dioxide.
- Figure 1 is a plan view representation of a portion of a memory cell array according to one embodiment of the present invention.
- Figures 2A and 2B are cross-sectional views of the array of Figure 1, taken at respective orthogonal sections A - A and B - B thereof, when in a preliminary stage of processing;
- Figures 3 A and 3B are cross-sectional views of the array of Figure 1, taken at respective sections A - A and B - B thereof, at an intermediate stage in its formation;
- Figure 4 is a cross-sectional view of the array of Figure 1, taken at section A - A thereof , when in the stage of processing shown;
- Figure 5 is an equivalent electrical circuit of a portion of the memory cell array shown in Figures 1 - 4;
- Figure 6 is a cross-sectional view of an array according to a second embodiment of the present invention.
- Figure 7 is an equivalent electrical circuit of a portion of an array of memory cells of the type shown in Figure 6.
- FIG. 1 a plan view of the primary elements of a portion of a memory cell array is first described, and this plan view is then used as a reference for the cross-sectional views of Figures 2A - 4, which show the array's structure at various stages of its formation.
- Conductive floating gate charge storage elements 11 - 19 are regularly spaced in a two-dimensional x-y pattern across a semiconductor substrate surface, with a layer of gate dielectric therebetween.
- Control gate lines 21 — 23 are elongated in the x-direction across the array and spaced apart in the orthogonal y-direction to individually extend across and be aligned with a line of floating gates, with a layer of dielectric between them.
- the lines of floating gates extending in the x-direction are referenced in this example as rows of floating gates, and the lines of floating gates extending in the y-direction are referenced as columns.
- the control gate lines 21 - 23 can be, for example, word lines of the array.
- a combination of dielectric material and voids is positioned between the rows of floating gates and the control gate lines, as best described with respect to the cross- sectional view of Figures 2 A - 4.
- Figures 2A and 2B show the result of a few initial steps in processing, in sections extending in the y-direction and x-direction, respectively, across the array of Figure 1.
- a gate dielectric layer 25 is first formed on a surface 27 of a semiconductor substrate 29 over the substrate area occupied by the array.
- the layer 25 may be silicon dioxide grown on the surface 27 to a thickness of about 90 Angstroms.
- a layer of polysilicon is then deposited across the dielectric layer 25 from which the isolated floating gates are formed. The thickness of this polysilicon layer may be about 1500 Angstroms.
- the polysilicon may be conductively doped either as part of the deposition process or after deposition by ion implantation.
- this polysilicon layer is separated by an etching step into strips 31 - 33 having lengths extending in the y-direction, and with widths and spacing in the x- direction that are preferably a minimum that the process being used will allow.
- a layer 35 of dielectric is formed over the area of the array, over exposed surfaces of the doped polysilicon strips 31 - 33 and substrate surface areas therebetween.
- This dielectric is preferably formed of a composite layer of silicon dioxide, silicon nitride and silicon dioxide, commonly known as ONO. Its thickness may be about 160 Angstroms, as an example.
- a next step is to form a second layer of doped polysilicon, or a combination of doped polysilicon and a top portion of a metal such as tungsten, over the dielectric layer 35 in the area of the array, with a thickness that may be in a range of about 3000 - 4000 Angstroms.
- a rather thick layer 37 of dielectric is then formed over the area of the array, preferably silicon nitride with a thickness in a range of about 2500 - 3000 Angstroms.
- the combination of the layers of ONO 35, second polysilicon or polysilicon/metal and silicon nitride 37 are etched through a mask (not shown) formed on top of the layer 37 to form strips of all three layers that are elongated in the x- direction and spaced apart in the y-direction.
- the second doped polysilicon or polysilicon/metal layer is separated by this step into the control gate lines 21 — 23.
- the widths and spacing of these strips are also preferably made to be about a minimum that is practical with the processing being used.
- the three-layer composite strips are so formed, they, particularly the top silicon nitride layer 37, are used as a mask to etch away exposed portions of the first doped polysilicon layer strips 31 - 33 between them, thereby separating these first polysilicon strips into the individual floating gates 11 - 19.
- the result is a series of self-aligned stacks, as best illustrated in Figure 3A, of gate dielectric 25, one of the floating gates 12, 15 or 18, an inter-polysilicon layer 35, one of conductive gate lines 21, 22 or 23, and a dielectric 37.
- widths of these composite strips in the y-direction may be about
- the aspect ratio is also controlled, independent of the process resolution element size, by controlling the heights of the stacks without affecting operation of the resulting array, particularly by controlling the thickness of the top dielectric layer 37 or another dielectric layer that may be added on top of it. Aspect ratios of up to 12, 15 or more are contemplated.
- the spaces 41 would be completely filled with silicon dioxide or other suitable solid dielectric.
- a considerable amount of effort has been directed over the years to develop techniques for filling small spaces with silicon dioxide without leaving any voids or pockets in the solid dielectric material.
- United States patents describing this effort include nos. 4,892,753, 6,013,584, 6,106,678, 6,110,793 and 6,335,288.
- Technical articles on this subject include Lee et al. "Dielectric Planarization Techniques For Narrow Pitch Multilevel Interconnects", VMIC Conference, Jun. 1987, pp. 85-92, and Qian et al., "High Density Plasma Deposition and Deep Sub-micron Gap Fill with Low Dielectric Constant SiOF Films", California D MIC Conference, Feb.1995, pp. 50-56.
- a dielectric layer 45 is formed, for example by depositing silicon dioxide, which closes off the top of the spaces 41 but does not completely fill in the spaces. Rather, the dielectric is intentionally deposited in a manner to leave voids 47.
- the voids 47 occupy a majority of the width of the spaces 41 at least along the heights of the floating gates on opposite sides of the spaces, except to the extent, if any, that the dielectric formed on the bottoms of the spaces under the voids 47 is thicker than the gate dielectric layers 25.
- a thin layer 49 of silicon dioxide may optionally be grown over the exposed surfaces of the stacks and spaces between them.
- the dielectric layer 45 can be formed with voids 47 by depositing an oxide with lower pressures and temperatures than are normally used to deposit oxide layers, such as in a low-pressure chemical-vapor-deposition (CVD) process.
- CVD chemical-vapor-deposition
- Many different combinations of starting gasses, pressures, temperatures and times may be used to form the layer 45 of silicon dioxide to include the voids 47, and are usually dependent upon the particular deposition equipment being used.
- a process carried out in a plasma enhanced CVD deposition chamber causes silane (SiH 4 ) and oxygen (O 2 ) gases to react in the chamber to form the layer 45 of silicon dioxide (SiO 2 ) with the voids 47.
- PVD Physical vapor deposition
- the voids 47 are initially filled with whatever gas or gasses are present in the deposition chamber when forming the dielectric layer 45.
- gasses typically have a dielectric constant close to that of air, namely close to 1.0.
- these gases are usually replaced over time with other ambient gases, such as air, in which the wafers are placed after the deposition and before the top of the layer 45 is sealed by further processing steps. The result is a desired low level of capacitive coupling between each pair of floating gates on opposite sides of one of the spaces 41.
- the voids 47 occupy as much of the width of the spaces 41 as practical and extend over as much of the vertical floating gate surface areas bordering the spaces 41 as possible.
- the width of the voids 47 in the y-direction is one-half or more of the width of the spaces 41 in the region of the opposing floating gates, such as between floating gates 12 and 15. Even when materials having a dielectric constant less that those of silicon dioxide and silicon nitride are used, it is desirable to maintain this relative width of the voids.
- isolation between adjacent floating gates can be further increased by use of a dielectric material for the layer 45 that has a lower dielectric constant than those of silicon dioxide or silicon nitride.
- a dielectric material for the layer 45 that has a lower dielectric constant than those of silicon dioxide or silicon nitride.
- An example is fluorinated silicon oxide (SiOF) that may be deposited by plasma enhanced CVD or high density plasma CVD by reacting silane and one of SiF 4 , CF 4 or NF within the vacuum processing chamber.
- the material SiOF has a dielectric constant within a range of about 2.2 to 3.2.
- the voids 47 contribute significantly to minimizing field coupling between adjacent rows of floating gates in a very small-scale memory cell array, and thus minimizes the influence of the level of charge of one floating gate on the state read from memory cells in adjacent rows. Isolation between memory cells along the same row (between columns of memory cells) is provided by the control gate lines extending downward between adjacent floating gates, thus shielding them from one other. This is best shown in Figure 3B, wherein the control gate line 22 extends downward between adjacent floating gates 14 and 15, between floating gates 15 and 16, and so on.
- FIG. 5 An equivalent circuit of a portion of a NAND array is shown in Figure 5, with elements common to those of Figures 1 - 4 being identified by the same reference number.
- the memory cells in each column are electrically connected together in series by implanting isolated source and drain regions (not shown) between the floating gates in the column, Figures 3 A and 4 show cross-sectional views of one of the columns. These implants can be made at a convenient point in the processing described above, such as when in the intermediate structural state of Figures 3 A and 3B.
- the stacks of floating and control gates can serve as a portion of an implant mask, confining the implants in the y-direction to regions of the substrate surface 27 between them.
- the control gate lines 21 - 23 are word lines of the array, each extending in the x-direction across a row of one memory cell in each of a large number of such NAND columnar series strings of memory cells.
- Each columnar string of series connected memory cells in Figure 5 includes a pair of select transistors at each end of the string, such as transistors 51 and 53 for one of the strings of Figure 5. The string is connected through transistor 53 to a common voltage Vss such as ground, and through transistor 51 to an individual bit line BL6.
- control gate lines 21 - 23 can be steering gates and source/drain regions can be formed in continuous lengths in the x-direction along the substrate surface 27 in spaces between the steering gates the y-direction.
- Word lines can also be added with lengths extending in the y-direction over the steering gates and coupled with certain regions of the substrate surface 27.
- the source and drain regions are formed in every other space between steering gates in the y-direction, these spaces then being filled with the dielectric layer 45 and voids 47, as described.
- the word lines extend downward into these spaces and are coupled through a dielectric layer with the substrate surface 27 to form select transistors that are part of the memory cells.
- select transistors In such a cell, two floating gate transistors and an intermediate select transistor are connected in series in the y-direction between adjacent source/drain regions that are elongated in the x- direction.
- ETOXTM memory cell array is illustrated in the cross-sectional view in Figure 6 along a column of a few memory cells.
- Floating gates 61 - 66 are positioned across a surface of a semiconductor substrate with a layer 69 of gate oxide therebetween.
- Control gates 71 - 76 in this case word lines, are positioned over respective ones of the floating gates 61 - 66 with a dielectric layer 79 therebetween, and are elongated along rows of memory cells, across a large number of such columns.
- Thick dielectric regions 81 are formed over the control gates.
- Source regions 91 and drain regions 93 implanted into the substrate surface, alternate along the column of cells.
- a layer 83 of dielectric is deposited in the manner described above with respect to Figure 4 for dielectric layer 45.
- Voids 85 having the same characteristics described above for the voids 47, are formed. But rather than placing the dielectric 83 and a void 47 in each space between adjacent floating gates, they appear in every other such space over drain regions 93. This is because the common source regions 91 are contacted by a conductor 87 that extends along the column, and thus this conductor fills those alternate spaces between side- wall spacers 89. The spaces between the gate stacks that include material of the conductor 87 are necessarily wider than those containing the dielectric 83 and voids 85.
- the adjacent floating gates on opposite sides of the spaces containing the dielectric 83 and voids 85 are not shielded and are close enough to have a high level of capacitive coupling if the voids 85 were not present. Since floating gates in adjacent columns can also be shielded, by extending the word lines down between them (not shown), use of the dielectric 83 and voids 85 reduces the coupling between the remaining sets of unshielded floating gates.
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EP04751389A EP1625616A2 (en) | 2003-05-21 | 2004-05-03 | Use of voids between elements in semiconductor structures for isolation |
JP2006532783A JP2007501531A (en) | 2003-05-21 | 2004-05-03 | Use of voids between elements in semiconductor structures for element isolation. |
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US10/443,502 US7045849B2 (en) | 2003-05-21 | 2003-05-21 | Use of voids between elements in semiconductor structures for isolation |
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WO2004107352A3 (en) | 2005-02-03 |
TWI267943B (en) | 2006-12-01 |
EP1625616A2 (en) | 2006-02-15 |
US20040232496A1 (en) | 2004-11-25 |
CN1791974A (en) | 2006-06-21 |
TW200509296A (en) | 2005-03-01 |
US7569465B2 (en) | 2009-08-04 |
US7045849B2 (en) | 2006-05-16 |
CN100428440C (en) | 2008-10-22 |
KR20060017803A (en) | 2006-02-27 |
JP2007501531A (en) | 2007-01-25 |
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