WO2004102403A3 - A system including a host connected to a plurality of memory modules via a serial memory interconnect - Google Patents

A system including a host connected to a plurality of memory modules via a serial memory interconnect Download PDF

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Publication number
WO2004102403A3
WO2004102403A3 PCT/US2004/014441 US2004014441W WO2004102403A3 WO 2004102403 A3 WO2004102403 A3 WO 2004102403A3 US 2004014441 W US2004014441 W US 2004014441W WO 2004102403 A3 WO2004102403 A3 WO 2004102403A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
host
downlink
memory modules
system including
Prior art date
Application number
PCT/US2004/014441
Other languages
French (fr)
Other versions
WO2004102403A2 (en
Inventor
R Stephen Polzin
Frederick D Weber
Gerald R Talbot
Larry D Hewitt
Richard W Reeves
Shwetal A Patel
Fetra Ross V La
Dale E Gulick
Mark D Hummel
Paul C Miranda
Original Assignee
Advanced Micro Devices Inc
R Stephen Polzin
Frederick D Weber
Gerald R Talbot
Larry D Hewitt
Richard W Reeves
Shwetal A Patel
Fetra Ross V La
Dale E Gulick
Mark D Hummel
Paul C Miranda
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc, R Stephen Polzin, Frederick D Weber, Gerald R Talbot, Larry D Hewitt, Richard W Reeves, Shwetal A Patel, Fetra Ross V La, Dale E Gulick, Mark D Hummel, Paul C Miranda filed Critical Advanced Micro Devices Inc
Priority to GB0521694A priority Critical patent/GB2416056B/en
Priority to DE112004000821.2T priority patent/DE112004000821B4/en
Priority to JP2006532883A priority patent/JP4836794B2/en
Priority to KR1020057021598A priority patent/KR101095025B1/en
Publication of WO2004102403A2 publication Critical patent/WO2004102403A2/en
Publication of WO2004102403A3 publication Critical patent/WO2004102403A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4247—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
    • G06F13/4256—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6022—Using a prefetch buffer or dedicated prefetch cache

Abstract

A system (50) including a host (100) coupled to a serially connected chain of memory modules (150A-B). In one embodiment, each of the memory modules includes a memory control hub (160) for controlling access to a plurality of memory chips (261) on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links (110). Each memory link may include an uplink (211) for conveying transactions toward the host and a downlink (212) for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.
PCT/US2004/014441 2003-05-13 2004-05-10 A system including a host connected to a plurality of memory modules via a serial memory interconnect WO2004102403A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB0521694A GB2416056B (en) 2003-05-13 2004-05-10 A system including a host connected to a plurality of memory modules via a serial memory interconnect
DE112004000821.2T DE112004000821B4 (en) 2003-05-13 2004-05-10 System with a host connected to multiple storage modules via a serial storage connection
JP2006532883A JP4836794B2 (en) 2003-05-13 2004-05-10 A system including a host connected to a plurality of memory modules via a serial memory interconnect
KR1020057021598A KR101095025B1 (en) 2003-05-13 2004-05-10 A system including a host connected to a plurality of memory modules via a serial memory interconnect

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US47007803P 2003-05-13 2003-05-13
US60/470,078 2003-05-13

Publications (2)

Publication Number Publication Date
WO2004102403A2 WO2004102403A2 (en) 2004-11-25
WO2004102403A3 true WO2004102403A3 (en) 2005-08-25

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/014441 WO2004102403A2 (en) 2003-05-13 2004-05-10 A system including a host connected to a plurality of memory modules via a serial memory interconnect

Country Status (8)

Country Link
US (4) US7421525B2 (en)
JP (1) JP4836794B2 (en)
KR (1) KR101095025B1 (en)
CN (1) CN100444141C (en)
DE (1) DE112004000821B4 (en)
GB (1) GB2416056B (en)
TW (1) TWI351613B (en)
WO (1) WO2004102403A2 (en)

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