WO2004100253A2 - Elektronisches bauteil, sowie systemträger und nutzen zur herstellung desselben - Google Patents
Elektronisches bauteil, sowie systemträger und nutzen zur herstellung desselben Download PDFInfo
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- WO2004100253A2 WO2004100253A2 PCT/DE2004/000934 DE2004000934W WO2004100253A2 WO 2004100253 A2 WO2004100253 A2 WO 2004100253A2 DE 2004000934 W DE2004000934 W DE 2004000934W WO 2004100253 A2 WO2004100253 A2 WO 2004100253A2
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H05K1/187—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding the patterned circuits being prefabricated circuits, which are not yet attached to a permanent insulating substrate, e.g. on a temporary carrier
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10T29/49121—Beam lead frame or beam lead device
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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EP04730953A EP1620890A2 (de) | 2003-05-07 | 2004-05-04 | Elektronisches bauteil, sowie systemträger und nutzen zur herstellung desselben |
US11/267,589 US7795717B2 (en) | 2003-05-07 | 2005-11-07 | Electronic component embedded within a plastic compound and including copper columns within the plastic compound extending between upper and lower rewiring layers, and system carrier and panel for producing an electronic component |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10320646A DE10320646A1 (de) | 2003-05-07 | 2003-05-07 | Elektronisches Bauteil, sowie Systemträger und Nutzen zur Herstellung desselben |
DE10320646.9 | 2003-05-07 |
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Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/267,589 Continuation US7795717B2 (en) | 2003-05-07 | 2005-11-07 | Electronic component embedded within a plastic compound and including copper columns within the plastic compound extending between upper and lower rewiring layers, and system carrier and panel for producing an electronic component |
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WO2004100253A2 true WO2004100253A2 (de) | 2004-11-18 |
WO2004100253A3 WO2004100253A3 (de) | 2005-09-29 |
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PCT/DE2004/000934 WO2004100253A2 (de) | 2003-05-07 | 2004-05-04 | Elektronisches bauteil, sowie systemträger und nutzen zur herstellung desselben |
Country Status (4)
Country | Link |
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US (1) | US7795717B2 (de) |
EP (1) | EP1620890A2 (de) |
DE (1) | DE10320646A1 (de) |
WO (1) | WO2004100253A2 (de) |
Cited By (1)
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US8188585B2 (en) | 2006-08-10 | 2012-05-29 | Infineon Technologies Ag | Electronic device and method for producing a device |
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- 2003-05-07 DE DE10320646A patent/DE10320646A1/de not_active Ceased
-
2004
- 2004-05-04 EP EP04730953A patent/EP1620890A2/de not_active Withdrawn
- 2004-05-04 WO PCT/DE2004/000934 patent/WO2004100253A2/de active Application Filing
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2005
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EP1154474A1 (de) * | 1999-08-23 | 2001-11-14 | Rohm Co., Ltd. | Halbleiter und seine herstellung |
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US8188585B2 (en) | 2006-08-10 | 2012-05-29 | Infineon Technologies Ag | Electronic device and method for producing a device |
DE102006037538B4 (de) * | 2006-08-10 | 2016-03-10 | Infineon Technologies Ag | Elektronisches Bauteil, elektronischer Bauteilstapel und Verfahren zu deren Herstellung sowie Verwendung einer Kügelchenplatziermaschine zur Durchführung eines Verfahrens zum Herstellen eines elektronischen Bauteils bzw. Bauteilstapels |
Also Published As
Publication number | Publication date |
---|---|
DE10320646A1 (de) | 2004-09-16 |
US7795717B2 (en) | 2010-09-14 |
WO2004100253A3 (de) | 2005-09-29 |
US20060087044A1 (en) | 2006-04-27 |
EP1620890A2 (de) | 2006-02-01 |
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