WO2004095585A1 - Nonvolatile semiconductor storage device and method for manufacturing nonvolatile semiconductor storage device - Google Patents

Abstract

A nonvolatile semiconductor storage device exhibiting a high write efficiency and prevented from being overerased. First and second p-type regions (13, 14) are formed in the surface of an n-type well (12) and spaced from each other by a predetermined distance. The first and second p-type regions function as source and drain regions. ONO films (15, 16, 17) and a gate electrode (18) are formed over a channel region (20) between the first and second regions. Charge is trapped in left and right program regions on both sides of the charge trap layer (16) of the intermediate layer of the ONO films to write data. The write is carried out by BBHE injection. BBHE leads to high write efficiency because no current flows between the gate and drain. Because of the p-channel, the absolute value the threshold decreases when data is written and increases when data is erased, thus preventing the fear of overerase.

Description

 Description: Nonvolatile semiconductor memory device and method of manufacturing nonvolatile semiconductor memory device

 The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and more particularly to a nonvolatile semiconductor memory device capable of recording two bits of information in one memory cell and a method of manufacturing the same. Background art

In recent years, as described in U.S. Pat. No. 5,768,192, a charge trap layer such as a nitride film having low conductivity is formed instead of the floating gate of a conventional flash memory. Non-volatile semiconductor memories have been proposed in which two bits of information can be recorded in one memory cell by separately injecting charges into the source side and the drain side of the charge trapping layer. In other words, in this nonvolatile semiconductor memory, it is a part of the channel region on the electron emission (source) side that affects whether or not the voltage is applied between the source and the drain. Paying attention to this, one bit is stored by injecting charge into the source side region of the charge trap layer. If the electrodes are connected in reverse, the drain will be on the electron emission side. By injecting charges into the drain side region of the charge trapping layer, the drain will be grounded and a negative voltage (V dr) will be applied to the source. 1 bit that is read in the reverse connection. In this way, charges are separately injected into some regions on both sides of the charge trapping layer, and during reading, the direction of the applied voltage is reversed, that is, in two regions opposed to each other across the channel region. By reversing the role of the source drain and reading out the charges accumulated on both sides of the charge trap layer separately, it is possible to record and read 2-bit information. I have.

 With reference to FIG. 28, the configuration of the nonvolatile semiconductor memory and data write / read operations will be briefly described. As shown in the figure, the non-volatile semiconductor memory (memory cell) 100 is composed of a pair of n-type regions 100 2 serving as a source / drain formed in a surface region of a p-type silicon semiconductor substrate 101. , 103, and the tunnel oxide film 104, the charge trapping layer 105, the silicon oxide film 106, and the gate electrode 1 formed on the channel region between the n-type regions 102, 103. It has 0 7. Here, the charge trap layer 105 is composed of a silicon nitride film.

 The nonvolatile semiconductor memory 100 traps electrons independently in the left and right program areas 108 and 109 at both ends of the charge trapping layer 105, and the left and right program areas 108 and It is possible to record 1-bit data and 2-bit data in total, depending on whether or not electric charge is injected into each of the 109 (program erase). The charge injection (program) is performed by injecting charges into the charge trapping layer 105 through the tunnel oxide film 104. The charge injection is performed by channel hot electrons (CHE).

 For example, when programming the right program area 109, the source is set to 0 V and the drain is set to about 5 V to create a potential difference between the source Z drain and a high voltage (about 10 V) is applied to the gate 107. ) Is applied to form a channel 110 between the source and the drain. Here, the range 11 of the formed channel 110 has the same potential, and no electric field is generated. In the range 1 2 where the channel 110 is not formed, an electric field is generated due to the potential difference between the source and the drain. Therefore, channel hot electrons (CHE) are generated in the range 1 2 and the right program region 1 An electron is trapped in 09.

To read the bit data in the right program area 109, apply the read voltage V g read to the gate 107, and Voltage V d read is applied between the source and the drain. The absolute value of the voltage at this time is lower than that at the time of programming, and is about V d read = 1.5 V and V g read = 3 V. At this time, if electrons are trapped in the right program area 109, a channel is not formed in the lower layer of the program area 109 due to the rise of the threshold due to this charge, and the source-drain area On the other hand, if no electrons are trapped in the program area 109, a channel is formed between the source and the drain to turn on. As described above, by using the n-type region on the program region 109 side as a source and using the opposing n-type region as a drain, the bits of the program region 109 can be read.

 Even if electrons are trapped in the program area 109, if a voltage is applied in the same direction as in the program, the source-Z drain turns on due to depletion below the 109 area near the drain. Therefore, the presence or absence of the charge trap in the program area 109 does not affect the read operation in this direction. The program to the left program area 108 and the reading of the bit data can be performed in the same manner in the reverse manner, and as described above, the charge injection to the left and right program areas is performed independently. And the presence or absence of charge trapping in the other program area during a read operation on either the left or right program area has no effect. Therefore, one bit is assigned to each of the left and right program areas in this one memory cell. Data can be recorded and read out at a time.

Thus, the nonvolatile semiconductor memory device described in the above-mentioned US Pat. No. 5,768,192 injects electrons into the charge trapping layer using channel hot electrons. However, the injection of charge by the channel hot electron turns on between the source and drain, that is, injects some of the electrons into the charge trapping layer while flowing current between the source and drain. , the injection efficiency is 1 0 ⁶ degree and low efficiency, internal electrodeposition There is a problem that the load on the source circuit is large and high-speed writing cannot be performed. This memory is erased by erasing the charge in the charge trapping layer. However, erasing the charge lowers the apparent threshold voltage as seen from the gate electrode. The memory is erased not for each cell but for the whole chip or block (generally 512 bits). However, since the characteristics of each memory cell vary, When the erasing process is performed, the progress of the charge erasure varies. As a result, there may be a case where memory cells are charged with positive charges due to excessive erasure of negative charges, and such memory cells are depleted due to a negative threshold voltage. However, there is a problem in that the continuity is maintained (over-erase).

 SUMMARY OF THE INVENTION It is an object of the present invention to provide a nonvolatile semiconductor memory device that solves the above-mentioned problems, improves writing efficiency, and does not cause over-erasing, and a method of manufacturing the same. Disclosure of the invention

 (1) The present invention uses a semiconductor substrate having an n-type well formed near the surface, and first and second p-type regions formed at predetermined intervals on the surface of the n-type well;

 A non-conductive charge trapping layer formed above a channel, which is a region between the first and second p-type regions on the surface of the n-type well, via a tunnel oxide film, and is insulated above the charge trapping layer. A gate electrode formed through a film, and a memory cell comprising:

A first program region that is a partial region of the charge trap layer on the first p-type region side, or a second program region that is a partial region of the charge trap layer on the second p-type region side By trapping charge in the program area, Grams are made,

 In the reading of the first or second program area, a negative voltage is applied to a P-type area on the opposite side of the program area, and a threshold voltage during non-programming and a threshold voltage during programming are applied to the gate electrode. Memory cell performed by applying a read voltage that is a voltage between threshold voltages

 Are arranged in a plurality.

 (2) Further, in the present invention according to (1), by setting the first and second program areas independently to a program / non-program state, two bits can be stored in one memory cell. Specializes in programming.

 (3) The invention according to the invention (1), wherein the first and second! ) Type region, a negative voltage is applied to one of the p-type regions, a positive voltage is applied to the gate electrode, and the other p-type region is opened or grounded. BTBT: By the charge injection by the electrons generated in B and B and Tuning 1 ing (B BHE injection: B and H B Electron), the charge is applied to the program region on the P-type region side where the negative voltage is applied. Is injected.

 (4) In the invention according to (2), a write negative voltage is applied to one of the first and second p-type regions, and a positive voltage is applied to the gate electrode. Voltage is applied and the other p-type region is opened or grounded, and charge injection (BBHE injection) by electrons generated by band-to-band tunneling (BTBT) causes the p-type region to which the negative voltage is applied. It is characterized by injecting charges into the program region.

(5) In the invention according to (1), a positive voltage is applied to the n-type well, and the entire channel FN is pulled out by applying a negative voltage to the gate electrode. It is characterized in that charges in the second program area are erased. (6) In the invention according to (1), the semiconductor substrate is grounded, a first negative voltage is applied to the n-type well, and the first and second p-type regions are applied to the first and second p-type regions. A substrate by applying a second negative voltage having an absolute value larger than the negative voltage of 1 and further applying a negative high voltage having an absolute value larger than the second negative voltage to the gate electrode. The charge in the first and second program regions is erased by hot hole injection.

 (7) In the invention according to (1), the plurality of memory cells are arranged in a matrix of X (columns) and Y (rows).

 A lead line serving as a gate electrode of the memory cells arranged in the X direction is provided for each row,

 A bit line to which the first p-type region of the memory cells arranged in the Y direction is connected is provided for each column, and a second p-type region of the memory cell is connected to each block. A source line is provided.

Arranging the plurality of memory cells in a matrix,

 (8) In the invention according to (1), the plurality of memory cells are arranged in an X (column) Y (row) matrix.

 A lead line serving as a gate electrode of the memory cells arranged in the X direction is provided for each row,

 A first column line which is a wiring in the Y direction to which the first p-type region of the memory cells arranged in the Y direction is connected; 2) A second column line, which is a wiring in the Y direction to which the type region is connected, is provided for each column.

 (9) In the invention according to (8), the first and second power lines are each formed by one p-type linear region, and the first and second power lines are respectively formed by the first and second memory cells. It is characterized in that it also serves as a p-type region.

(10) In the invention according to (4), the plurality of memory cells are arranged in a matrix of X (columns) and Y (rows). A lead line serving as a gate electrode of the memory cells arranged in the X direction is provided for each row,

 A first column line, which is a wiring in the Y direction, to which the first p-type region of the memory cells arranged in the Y direction is connected, and a second p-type region of the memory cell, to which the first p-type region is connected A second column line, which is a wiring in the Y direction, is provided for each column.

 (11) The present invention is characterized in that, in the invention of (10), the first column line and the second column line adjacent in the X direction are shared.

(1 2) Further, according to the invention of (11), in the invention according to (11), the common first and second column lines are formed by p-type linear regions, and also serve as p-type regions of the memory cells. It is characterized by the following.

 (13) In the invention according to (10), the first and second column lines are each formed by one p-type linear region, and the first and second column lines are respectively formed by the first and second memory cells. It is characterized in that it also serves as a p-type region. (14) Further, according to the invention of (12), when the charge is injected into the first or second program area of a certain memory cell, the program area on the side of the program area into which the charge of the memory cell is injected is injected. A negative write voltage is applied to the column line that is the p-type region, a positive voltage is applied to the gate line that is the gate electrode of this memory cell, and these word lines and column lines are shared (X A write blocking voltage, which is a negative voltage having an absolute value smaller than the write negative voltage, is applied to a column line of the memory cell opposite to the supplied column line. .

(15) Further, according to the present invention, a plurality of p-type linear regions serving as a source, a drain and a column line are formed in a stripe shape on the surface of an n-type well of a semiconductor substrate, and a charge trapping layer is formed thereon. And a conductive film serving as a lead wire and a gate electrode formed thereon in a stripe shape so as to be orthogonal to the P-type linear region. (16) In the invention according to (15), a groove parallel to the p-type linear region is formed in a gap between the plurality of p-type linear regions in the semiconductor substrate. The ONO film is formed along the wall and bottom of the groove.

 (17) In the invention according to (15), the semiconductor substrate has a bottom portion having a width of the P-type linear region in the Y direction and a depth corresponding to the channel region in the Y direction. A plurality of grooves are formed sandwiching the upper surface of the width of the P-type linear region, and the P-type linear regions are formed at the bottom and the upper surface of the groove. It is characterized by being formed along the bottom surface.

 (18) In the invention according to (15), a silicide film is formed on one or both of the p-type linear region and the conductive film.

 (19) The present invention also provides a plurality of island-shaped P-type regions formed on a semiconductor substrate surface and arranged in a matrix of X (columns) and Y (rows),

 An ONO (Oxide—Nitride—Oxide) film formed on the semiconductor substrate;

 On the ONO film, a plurality of grid lines formed in stripes in gaps in the X direction of the p-type region groups arranged in matrix,

 A plurality of power lines formed in a stripe shape at the same pitch as the pitch in the X direction of the p-type region group arranged in the matrix further above the word lines,

 A local wiring connecting two P-type regions arranged in a matrix in the X direction via a layer between the column line and the ground line, and in each column, in the Y direction Local wiring in which the connection direction of each p-type region arranged in

 Has,

A via hole is formed in each local wiring and a column line formed in the upper layer. Characterized by being connected via

 (20) Further, the present invention provides a method for manufacturing the nonvolatile semiconductor memory device according to (19),

 On the surface of the semiconductor substrate, Forming a trench insulating film for electrically isolating elements from each other in a stripe-shaped region that is a gap in the Y direction of the matrix region group where the group of regions is to be formed, forming the ONO film, and forming the word line. After being formed of a metal layer, the P-type region is formed by ion implantation of self-alignment using the lead line.

 (21) The present invention also provides a plurality of p-type regions and trench insulating films formed on the surface of a semiconductor substrate, wherein the p-type regions and the trench insulating films are alternately arranged in a vertical direction (Y direction) and a horizontal direction (X direction). A horizontal rectangular P-type region and a vertical rectangular trench insulating film, which are arranged in a lattice by combining

 A 〇N O film formed on the semiconductor substrate,

 A plurality of stripes formed on the ON film in stripes in gaps in the X direction of the arranged p-type regions;

 A plurality of column lines formed in a stripe shape above the arrayed p-type regions at a pitch of half the X-direction pitch of the p-type regions above the arranged p-type regions;

 Each column line is connected to a p-type region formed therebelow via a contact hole.

 (22) Further, the present invention is the method for manufacturing the nonvolatile semiconductor memory device according to (21), wherein the trench insulating film is formed on a semiconductor substrate surface, and the ONO film is formed thereon. And forming the p-type region with a metal layer, and then forming the p-type region by ion implantation of a self-aligned line using the p-type line.

(23) Further, the present invention provides an ONO film formed on an upper layer of a semiconductor substrate, and a plurality of ground lines formed in an X direction on an upper layer of the ON film, A plurality of pairs of left column lines and right column lines formed in the Y direction further above the lead line;

 On the surface of the semiconductor substrate, a plurality of left Ρ-type regions formed at predetermined intervals in a lower region of the left column line, and a plurality of right ρ-type regions formed at predetermined intervals in a lower region of the right column line. , And

 Further, an insulating region is formed on the surface of the semiconductor substrate, which associates one left ρ-type region with one right ρ-type region obliquely opposed to a channel region, which is a lower layer region of one word line. It is characterized by.

 (24) Further, the present invention provides a semiconductor device, comprising: a source and a drain formed at predetermined intervals on a surface of an η-type well formed near a surface of a semiconductor substrate; A non-conductive charge trapping layer formed above a channel as a region via a tunnel oxide film, and a gate electrode formed above the charge trapping layer via an insulating film. When,

 A source and a drain formed at predetermined intervals on the surface of the ρ-type layer formed near the surface of the semiconductor substrate; and a tunnel oxide film above a channel which is a region between the source and the drain on the surface of the ρ-type well. A channel cell comprising: a non-conductive charge trap layer formed through the gate electrode; and a gate electrode formed above the charge trap layer via an insulating film.

 Are formed adjacently on the same semiconductor substrate, and their drains and gates are commonly connected.

(25) The present invention further provides a first and second ρ-type region formed at predetermined intervals on a surface of an η-type well formed near a surface of a semiconductor substrate; A non-conductive charge trap layer formed above a channel, which is a region between the first and second ρ-type regions, via a tunnel oxide film; and a non-conductive charge trap layer formed above the charge trap layer via an insulating film. Ρ a channel array region in which a plurality of channel cells including First and second n-type regions formed at predetermined intervals on a P-type well surface formed near the surface of a semiconductor substrate; and between the first and second n-type regions on the p-type well surface An N-channel cell including: a nonconductive charge trapping layer formed above a channel, which is a region of the above, via a tunnel oxide film; and a gate electrode formed above the charge trapping layer via an insulating film. A plurality of N-channel array regions,

 Are formed on the same semiconductor substrate. In the present invention, bit data is stored by trapping charges (negative charges) in the charge trapping layer, thereby changing the threshold voltage as viewed from the gate electrode. Since it is a p-channel, the threshold voltage is set to a negative voltage, and when a negative voltage whose absolute value is larger than the threshold is applied to the gate electrode, the channel between the first and second p-type regions Are formed to conduct. One of the first and second p-type regions functions as a source and the other functions as a drain, but the function is not fixed, and the function alternates depending on the applied voltage condition. I do. When a negative charge is trapped in the charge trapping layer, the negative potential generated by the negative charge causes conduction between the first and second p-type regions even when a low negative voltage is applied to the gate electrode. The threshold voltage (absolute value) decreases.

Since writing is performed one bit at a time unlike erasing, charges can be injected until the threshold reaches a certain potential while verifying the degree of charge trapping even if the cell characteristics vary. . For this reason, variation in the threshold value of each bit cell can be reduced, and it is possible to prevent the threshold value of the memory cell from becoming too positive due to excessive charge trapping and depletion. Conversely, the apparent threshold value rises in the negative direction by erasing performed for the entire chip or for each block, so that over-erasing causes memory cells to become depressed, as in n-channel flash memory. There is no end.

 In the present invention, a non-conductive film is used as the charge trapping layer. Generally, a silicon nitride film having a relatively high dielectric constant is used. Because it is a nonconductor, the trapped charge does not move and remains at the trapped position. In a general memory cell, charge trapping is performed from the vicinity of the source and the drain. In the memory cell of the present invention, for example, the above-described BBHE injection (electrons generated by interband tunneling (Bandto Band Hot The charge is trapped in the first and second program regions at both ends of the charge trapping layer by charge injection by E 1 ectron).

 The trapping of charges into the first and second charge trapping layers can be performed independently, and the reading can be performed independently by reversing the reading direction. With this, 2-bit data can be stored. Also, in the present invention, charge is injected into the charge trapping layer by BBHE injection. In BBHE injection, electrons are generated by applying a high negative voltage to the p-type region (gate or drain) without flowing a current between the gate and drain, and the electrons are turned into hot electrons by a high electric field. It is injected into the charge trapping layer by the positive voltage of the first electrode. In this way, since no channel current flows between the source and drain, as shown in Fig. 4, it is about three orders of magnitude more efficient than channel hot electron injection and uses a high-voltage generation circuit with an internal power supply of the same capacity. Cells that are three orders of magnitude larger can be programmed at the same time, and equivalently, three orders of magnitude faster writing can be achieved.

Since the memory cell of the present invention is composed of one transistor, various connection forms such as NOR connection, contactless connection, virtual ground array connection, etc. can be realized with a simple configuration. In the above embodiment, (8) is an invention relating to NOR connection, (8) and (10) are inventions relating to connectionless connection, and (12) is a virtual 'ground array'. It is the invention which concerns on. In the case of NOR connection, a metal wiring film may be used as a bit line, and the first p-type region (drain) of each memory cell may be connected by a contact plug.

 According to the present invention, in the case of the virtual ground array connection, the P-type region of the memory cell column arranged in one column in the Y direction is formed by one p-type linear region, and the diffusion layer wiring is formed. The configuration can be further simplified because it is used together with a column line (bit line). As described above, even when a linear p-type region is used as a column line, a metal column line is formed in the upper layer, and the linear p-type region is separated from the metal wiring at predetermined intervals (for example, 64 cells). The conductivity may be ensured by lowering the contact to the diffusion layer wiring in the mold region.When writing is performed with the virtual ground array connection, the column line to which the negative voltage of the memory cell to be written is applied The (P-type region) is common to the target memory cell and an adjacent memory cell adjacent in the X direction. Since the adjacent memory cell also has the same word line as the target memory cell, the voltage condition near the p-type region of the adjacent memory cell is also a write condition. Similarly, writing is performed on the adjacent memory cell. Therefore, in the invention of (14), in the next memory cell, the absolute value of the write voltage is smaller than that of the p-type region (column line) facing the P-type region shared with the target memory cell. Apply a negative voltage, write inhibit voltage. By applying the write inhibit voltage, the depletion layer of the left and right P-type regions interferes in the adjacent memory cell! The strong electric field near the boundary of the) type region is alleviated. As a result, BB HE does not occur in the unselected adjacent memory cell, and writing is not performed.

In the present invention, a memory cell array is formed by a stripe-shaped P-type linear region formed on the surface of an n-type well of a semiconductor substrate, and an ONO film and a conductive film perpendicular to the region. The P-type linear region is composed of the first and second p-type regions of each memory cell. And column line. The conductive film also serves as a gate electrode and a word line of each memory cell. Further, the ONO film functions as a charge trapping layer for each memory cell, and also functions as an interlayer insulating film on the p-type linear region. With this configuration, a memory cell array can be manufactured with a simple configuration and a simple manufacturing process.

 According to the present invention, in the memory cell array having the above-described configuration, a groove (trench) is formed in a gap between p-type linear regions, that is, a channel region, and an ONO film is formed along a wall surface and a bottom surface of the groove. . As a result, since the channel is formed along the groove, a sufficient channel length can be ensured even if the interval between the p-type linear regions is reduced and the integration is planarly increased in the X direction.

 In the present invention, a silicide film is formed on one or both of the p-type linear region serving as the column line and the conductive film serving as the lead line. As a result, the resistance of the column line and the word line can be reduced, and the speed of data reading can be increased. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a diagram showing a basic structure of a p-channel MONOS memory cell according to the first embodiment. FIG. 2 is a diagram showing an example of the processed shape of the p-channel MONOS memory cell. FIG. 3 is a diagram illustrating a write operation by BBHE injection in the same p-channel MON OS memory cell. Figure 4 compares the efficiency of the BBHE injection and the conventional writing method. FIG. 5 is a diagram showing a distribution of threshold values during programming / amplifying of the p-channel MONOS memory cell. FIG. 6 is a diagram illustrating a read operation in the p-channel M〇NOS memory cell. FIG. 7 is a diagram illustrating an erase operation in the p-channel MONOS memory cell. FIG. 8 is a diagram illustrating voltage application conditions during writing, reading, and erasing in the same p-channel MONOS memory cell. Figure 9 shows the same p-channel MONO FIG. 2 is a diagram illustrating a structure of a VGA type memory cell array using S memory cells. FIG. 10 is a diagram showing an equivalent circuit of the VGA type memory cell array and a voltage application method at the time of writing. FIG. 11 is a diagram showing a voltage application method and a depletion layer formation state at the time of writing in the VGA type memory cell array. FIG. 12 is a diagram showing another embodiment of the voltage application method at the time of writing in the VGA type memory cell array. FIG. 13 is a diagram showing a voltage application method at the time of reading of the VGA type memory cell array. FIG. 14 is a diagram showing a structure of a VGA type memory cell array using the p-channel MONOS memory cell. FIG. 15 is a sectional view showing a vertical structure of the VGA type memory cell array. FIG. 16 is a diagram showing the structure of another VGA type memory cell array using the p-channel MONOS memory cell. FIG. 17 is a cross-sectional view showing the vertical structure of another VGA type memory cell array. FIG. 18 is a diagram showing an equivalent circuit of the same NOR type memory cell array. FIG. 19 is a diagram showing the structure of a completely isolated memory cell array using the p-channel MONOS memory cells. FIG. 20 is a diagram showing an equivalent circuit of the completely separated memory cell array. FIG. 21 is a diagram showing a structure of a P-type linear region when the complete isolation type memory cell array is made contactless. FIG. 22 is a structural diagram of a P-channel MONOS memory cell array according to another embodiment of the present invention. FIG. 23 is a structural diagram of a p-channel MONOS memory cell array according to another embodiment of the present invention. FIG. 24 is a structural diagram of a p-channel MON OS memory cell array according to another embodiment of the present invention. FIG. 25 is a block diagram of a P-channel MONOS memory chip according to an embodiment of the present invention. FIG. 26 is a structural diagram of a CMOS logic circuit according to an embodiment of the present invention. FIG. 27 is a configuration diagram of the memory cell array according to the embodiment of the present invention. FIG. 28 is a diagram showing the structure of a conventional n-channel MONOS memory cell. BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described with reference to the drawings.

 FIG. 1 is a structural diagram of a P-channel MONOS memory cell according to an embodiment of the present invention. The memory cell includes an n-type well 12 formed on a p-type semiconductor substrate 11 and p-type regions 13 and 14 formed at predetermined intervals near the surface of the n-type well 12. have. During operation of the memory cell (during reading), one of the p-type regions 13 and 14 functions as a source and the other functions as a drain, but as described later, this memory cell writes bit data Since there are two program areas on the left and right, the one that takes charge of the source or drain function changes depending on which one is read.

 A region located between the two p-type regions 13 and 14 in the n-type well 12 is a channel region 20. Above the channel region 20, a three-layered ON film and a gate electrode 18 are formed so as to cover the channel region 20. The ONO film consists of a tunnel oxide film 15 made of silicon oxide, a charge trap layer 16 made of silicon nitride and accumulating injected charges (electrons), and an insulating film 17 made of silicon oxide. . The thickness of each of these three layers is about 5 to 8 nm. Further, the gate electrode 18 is made of polysilicon.

 When a memory cell array is configured with the memory cells having this configuration, the gate electrode 18 of the memory cell in the X direction is formed integrally so that the memory cell array also functions as a word line. ).

 The operation of the P-channel MONOS memory cell having the above structure will be described. In the MONOS memory cell, a nitride film is used as the charge trapping layer 16. However, since the nitride film has low electric conductivity, trapped charges do not move in the film and remain at the trapped position.

Injection (writing: program) of charges (electrons) into the charge trapping layer 16 is performed between the gate electrode 18 and one of the p-type regions 13 or 14. Since the BBHE injection is performed by applying a high voltage, electrons are injected into the charge trap layer 16 from the vicinity of the p-type region 13 or 14, and the left program region 16 L or the right program region 16 in the charge trap layer 16 is injected. The trapped charge in R does not move to the opposite side.

 That is, it is possible to select which of the left and right program areas 16L, R to perform writing, depending on which of the p-type areas 13, 14 is to be applied with a negative high voltage at the time of writing. At the time of reading (as will be described later), it is possible to select which of the left and right program areas 16 L and R to read depending on which of the p-type regions 13 and 14 functions as a source drain.

 Therefore, the left and right program areas 16L and 16R function as independent program areas, and this P-channel MONOS memory cell can store two bits of data in one memory cell. It is possible.

 Hereinafter, the write and read operations will be described in detail. Here, write and read operations to the left program area 16L will be described.

 The charge injection into the charge trapping layer 16 is performed by applying a high positive voltage (Vgw) to the gate electrode 18 and a high depletion layer generated when a high negative voltage (Vdw) is applied to the p-type region 13. Band-to-Band Tunneling induced Hot Electron (BBHE)

Electron) injection. At this time, the drain 14 is opened or grounded, and the semiconductor substrate 11 is grounded. _§ is preferably about 10 and Vdw is preferably about 15 to -8 V.

With this potential arrangement, as shown in FIG. 3, a depletion layer region 21 is generated at the junction between the p-type region 13 and the n-type well 11, and the band Electrons by tunneling (BTBT) A Z-hole pair is generated. These electrons are accelerated by the strong electric field in the depletion layer region 21 and become hot electrons with high energy. A part thereof is attracted by the positive voltage applied to the gate electrode 18 and is injected into the charge trap layer 16 over the tunnel oxide film 15.

Since this charge injection is performed while the p-type region 1314, that is, the source and the drain are off, by applying an appropriate voltage (before and after 15V) as Vdw, the charge is injected as shown in FIG. as shown in), 1 0 ² about injection efficiency can be ensured, as compared to FIG. (B), X 1 0 ³ as compared with the conventional switch catcher channel hot electron injection method A high degree of efficiency can be obtained.

 At the time of writing by the BBHE injection, the hot holes are attracted to the p-type regions 13 and 14 or the n-well 12 side, so that the hot holes are not injected into the charge trap layer 16 and the tunnel oxide film 17 Does not deteriorate.

 The charge by BBHE injection using the p-type region 13 is held in the left program region 16L of the charge trapping layer 16.

 Here, the p-channel MONOS memory cell (FET) turns on when a negative voltage is applied to the gate electrode, but charges are trapped (written: programmed) in the charge trapping layer between the gate electrode and the channel region. Then, the absolute value of the threshold voltage Vth of the gate electrode apparently decreases as shown in FIG. Here, the distribution of the threshold value of the written bit (memory cell) is narrower than the distribution of the threshold value of the erased bit because the writing is performed bit by bit. Writing can be performed while finely adjusting the threshold value of each bit. However, since erasing is performed in the entire memory or in block units, adjustment cannot be performed for each bit, and variations occur.

As described above, in the p-channel MONOS memory cell, erasing is performed in the direction in which the threshold value (absolute value) increases, so that even if the threshold value varies, the threshold value may be exceeded. The phenomenon of erase cannot occur.

 To read the left program area 16L written by the above operation, as shown in FIG. 6, ground the p-type area 13 and apply Vdr to the p-type area 14. V d i ^ i-l. About 5 to 12 V is preferable. That is, at this time, the p-type region 13 functions as a source, and the p-type region 14 functions as a drain. Hereinafter, in the description of this read operation, the left p-type region 13 is referred to as a source, and the right P-type region 14 is referred to as a drain.

 In this state, the read voltage V gr is applied to the gate electrode 18. The gate voltage Vgr is set so as to be a voltage between the threshold value Vth (e) at the time of erasing and the threshold value Vth (p) at the time of writing shown in FIG. As a result, when the gate voltage is applied, ON / OFF between the source and the drain is determined by whether or not the left program area 16L is written. That is, bit data (left bit) indicating whether or not the left program area 16L has been written can be read depending on whether or not the source drain is turned on. When the left program area 16L is written (when charges are trapped), the negative charge accumulated in the left program area 16L when the read voltage Vgr is applied to the gate electrode 18 Is added to exceed the threshold voltage, the source 13 side of the channel region 20 becomes a negative potential to form a channel, and the source Z drain is conducted to turn on. The bit data at this time is set to "0".

 On the other hand, when the left program area 16 L is not written (when no electric charge is accumulated), even if the read voltage V gr is applied to the gate electrode, the channel area 20 between the source / drain is not applied. There is no negative potential, and no channel is formed in the channel region 20. Therefore, conduction between the source and drain remains off without conduction. The bit data at this time is "1".

During the read operation of the left program area 16L, if the right program area 16R is not written, Naturally, this does not affect the read result (ON / OFF) of the area 16 L, but the channel area 20 on the drain side is depleted even if the right program area 16 R is written. Continuity is maintained, and the left program area

Does not affect the 16 L read result.

 Next, an erasing operation for removing charges from the charge trap layer 16 will be described. The erase operation is performed for the entire memory or for each block.

The erasing operation of one memory cell will be described.

 Erasing is performed by pulling out the entire channel FN or injecting a substrate hot hole. FIG. 7 (A) is a diagram illustrating the connection of FN (Fowler-Nordheim Tunneling) extraction on the entire channel. To perform FN extraction on the entire channel, apply a negative voltage (V ppg) of about _10 V to the gate electrode 18 and extract negative charges to the source 13, drain 14 and n-well 12 for

A positive voltage (Vde, Vsub) of about +10 V is applied. By applying the voltage in this manner, a strong electric field is generated between the charge trapping layer 16 and the channel region 20, and the electrons accumulated in the charge trapping layer 16 are converted to the tunnel oxide film 13. And is extracted by jumping to the n-layer 12 and the charge in the charge trapping layer 16 is erased.

 FIG. 1B is a diagram for explaining hot hole injection of the substrate. Substrate hot

When performing the gate injection, a negative high voltage V ge of about 110 V is applied to the gate electrode 18, and a negative voltage V _{2 of} about 13 V is applied to the source 13 and the drain 14. Then, a negative voltage V, of about 11 V is applied to the n-type well 12. The relationship between each voltage is

 I V g e I> I I> I V, I

So that Then, the semiconductor substrate 11 is grounded. By applying a voltage in this manner, the p-type substrate 11, n-type well 12 and p-type regions (source and drain) 13 and 14 function as pnp bipolar transistors, and the P-type semiconductor substrate Holes from 1 1 to source 13 and drain 14 Released. On the other hand, since a high negative voltage is applied to the gate electrode 18, some of the holes are drawn in the direction of the gate electrode, pass through the tunnel oxide film 15, and enter the charge trapping layer 16. The positive charge of the hole cancels the negative charge of the electron, and as a result, the charge of the charge trap layer 16 is erased.

 In the above, the operation of programming, reading, and erasing (erasing is common to the left and right) to the left program area 16 L (left bit) has been described. In the erase operation, the voltages and operations are exactly the same, except that the voltages applied to the P-type regions 13 and 14 are reversed from those described above.

 Here, the voltage application conditions for left bit program, read, write bit program, read and erase (erase) are summarized in Fig. 8. Note that this voltage application condition is a condition in which the substrate 11 is grounded, but since it is a p-channel transistor, it is possible to apply a back gate voltage to bias the entire memory cell to the positive side. Good. In that case, each voltage under the above voltage application conditions is a voltage obtained by subtracting the bias.

Here, a memory cell array in which a plurality of the memory cells are arranged will be described with reference to FIGS. This memory cell array has a VGA (virtual * ground 'array) type connection configuration. FIG. 9 (A) is a cross-sectional perspective view of a memory cell array, FIG. 9 (B) is a diagram showing a configuration of one of the memory cells, and FIG. 9 is an equivalent circuit thereof. In FIG. 9 (A), the broken lines are virtual lines indicating the boundaries of each memory cell. The equivalent circuit of FIG. 10 shows the voltages applied to each word line and column line at the time of writing. A plurality of p-type linear regions 30 in the Y direction are formed in stripes at predetermined intervals on the surface of the n-type well 12. The p-type linear region 30 is formed across the boundary of the memory cell, and one p-type linear region 30 is formed in the X direction. It also serves as the p-type regions 13 and 14 (source and drain) of two adjacent memory cells and also serves as a column line. This column line functions both as a bit line and a source line depending on the connection to the Y gate.

 The lead line 31 is formed in a stripe shape in the X direction so as to be orthogonal to the p-type linear region 30, and also serves as the gate electrode 18 above the channel region 20 of each memory cell. An ON0 film 32 is formed between the word line 31 and the semiconductor substrate (p-type regions 13 and 14, channel region 20). The 〇NO film 32 is also formed continuously in the X direction, like the word line 31. Of the 01 ^ 0 film 32, the section above the channel region 20 functions as the tunnel oxide film 15, the charge trapping layer 16 and the insulating film 17, and the section above the P-type regions 13 and 14 is the interlayer insulating film. Functions as a membrane.

 In this embodiment, the ONO film 32 is formed in a stripe shape in the X direction like the word line 31. However, since the ONO film 32 is not a conductive film, it may be formed on the entire memory cell array. This makes it possible to omit the process of etching the ONO film 32 in a stripe shape.

 Thus, in this memory cell array, one p-type linear region (column line) 30 also serves as the p-type regions 13 and 14 of two memory cells adjacent in the X direction, so that the memory configuration is simplified. And high integration is possible. In addition, in the memory cell array having this configuration, the following processing is required when writing to each memory cell.

When writing to the left program area 16 L (left bit) of the target memory cell, Vgw is applied to the word line 30 (WL n) as the gate electrode 18 of this memory cell, as shown in Figure 3. At the same time, Vdw is applied to the column line 31 serving as the p-type region (source) 13 of the memory cell to perform BBHE injection. As described above, the p-type region of the memory cell to which this writing is performed is performed. The region (source) 13 is the p-type region (drain) of the memory cell on the left (Because the word line 31 to which Vgw is applied is also common), writing to the left program area 16L of the target memory cell and writing to the memory on the left Writing is also performed to the right program area 16R (write bit) of the cell. (This is a phenomenon that does not occur in channel hot electron (CHE) injection, which increases the energy of electrons by flowing a current between the source Z drain.) Therefore, in this embodiment, FIG. As shown in FIG. 11 and FIG. 11, V dw is applied to the memory cell to the left of the memory cell to be written! A write-blocking voltage is applied to the P-type region 13 which is the P-type region facing the type region, thereby preventing writing to (the write bit of) the memory cell on the left side. I have. In FIG. 11, a write blocking voltage of about half (VdwZ2) of the write voltage Vdw is applied to the p-type region 13 of the memory cell on the left. Then, in the memory cell on the left side, the lateral electric field of the left and right p-type regions 13 and 14 is reduced, and the occurrence of BB HE can be suppressed, and the right program region 16R of the memory cell on the left side can be suppressed. It is possible to prevent data from being written by BB HE injection.

 Further, in the memory cell on the further left side having the p-type region 14 shared with the p-type region 13 to which VdwZ2 is applied, a depletion layer is generated near the boundary between the p-type region 14 and the channel region. However, since the intensity of the electric field is VdwZ 2, generation of BBHE is suppressed.

 In FIG. 11, a voltage of about Vd w / 2 is applied to a memory cell adjacent to a memory cell to be written. However, the method of applying the write blocking voltage is not limited to this. For example, as shown in Fig. 12 (A), Vdw is applied to all power lines on the program area side (left side in the figure) where the target memory cell is written, and the depletion layer is connected by applying Vdw. HE may not be generated.

Also, as shown in Fig. 12 (B), write the target memory cell. A gradually decreasing write blocking voltage may be applied to a plurality of column lines on the program area side (the left side in the figure). In the example shown in the figure, V dw is applied to the target column line i, 2 VdwZ3 is applied to the left column line i-11, and Vd wZ is applied to the left column line i-12. 3 is applied. As a result, the intensity of the electric field generated in the memory cell on the left side of the column line i-12 can be reduced to VdwZ3, and the occurrence of BBHE can be reliably prevented.

 In FIGS. 10 to 12, the case of writing to the left program area 16 L (left bit) of the target memory cell has been described, but the case of writing to the right program area 16 R (right bit) is described. Performs the same processing by inverting left and right.

FIG. 13 is a diagram showing the state of voltage application to each of the read lines and column lines at the time of reading in the VGA type memory cell array. At the time of reading, as shown in FIG. 5, of the column lines (P-type linear regions) 30 serving as the gate drains of the target memory cells, the column line (drain) on the side from which bit data (left bit right bit) is read is read. ) To apply Vdr (-1.5 to 12V), and ground the opposing column line (source). Leave the column lines other than the target memory cells open. In addition, a read voltage Vgr (-5 V) is applied to the word line serving as the gate electrode of the target memory cell. In this state, bit data is read depending on whether or not between the gate and drain is turned on. Figures 9 to 13 describe a VGA (virtual ground array) type memory cell array in which the p-type region of the memory cell also serves as a column line. The memory cell array formed and connected to the metal column lines formed in the upper layer by contact plugs will be described. In this memory cell array, the bit lines and the source lines are formed of metal, so that the resistance can be reduced, and high-speed writing and high-speed reading can be performed. Although the structure of each memory cell is different, the connection form of the memory cell array is the same VGA connection as that shown in Figs. FIG. 14 is a plan view showing the structure of the memory cell array, and FIG. 15 is a sectional view taken along line X1-X1, a sectional view taken along line X2-X2, and a sectional view taken along line YY of the same plan view. Fig. 18 shows the equivalent circuit. This memory cell array is also formed on the n-type well 40 near the surface of the p-type substrate. On the surface of the n-type cell 40, a p-type region 41 having an island-like planar shape is formed in a matrix. The memory cell S is formed between two island-shaped p-type regions 41 adjacent in the Y direction (up and down), and the region between them becomes a channel region 42. Therefore, each p-type region 41 also serves as the p-type regions 13 and 14 (source and drain: see FIG. 1) of two memory cells S adjacent in the Y direction.

 An ONO film 43 and word lines 44 are formed so as to cover a plurality of channel regions 42 arranged in the X direction (left and right). Further, a plurality of column lines 45 are formed in the Y-direction at the same interval as the p-type region 41 in a stripe shape. The column line 45 is formed in the upper layer, and is connected to the P-type region 41 via the intermediate wiring film 46 in the lower layer. The column line 45 and the intermediate wiring film 46 are connected by a via hole 47, and the intermediate wiring film 46 and the p-type region 41 are connected by a contact plug 48. Each p-type region 41 of one row arranged in the Y direction is connected alternately to the left and right column lines of the row.

 When manufacturing a memory cell having this configuration, a step of implanting p-type ions with a self-alignment line after forming a metal lead line 44 is adopted.At this time, the p-type regions are connected in the X direction. In order to prevent such a situation, a stripe-shaped trench isolation layer 40 in the Y direction is formed in advance at a pitch in the X direction of the memory cell.

In this embodiment, the ONO film 43 is formed in a stripe shape like the lead wire 44, but the {N} film 43 may be formed on the entire memory cell array. Further, the column line 45 is formed so as to pass through the center of the intermediate wiring film 46, but may not be located at the center as long as it passes above the intermediate wiring film 46. As one memory cell is configured with the two p-type regions 41 adjacent in the Y direction as the source and drain as described above, it is necessary to select a memory cell group in one column with two continuous column lines By selecting one word line, one memory cell can be selected.

 In the memory cell arrays of FIGS. 14 and 15, the column line 45 and the island-shaped p-type region 41 are connected via the intermediate wiring film 46. Shows an embodiment in which the contact plugs 147 are directly lowered from the column lines 45 to the p-type regions 141.

 In FIG. 16, the column lines 45 and the word lines 46 are indicated by broken lines, and the trench isolation 140, the p-type region 141, and the channel region 42 on the substrate are indicated by solid lines and hatching. . In this embodiment, the p-type region 14 1 is formed to have a length of 3 F in the X direction in the same manner as the intermediate wiring film 46 in FIG. In addition, in the memory cell array of this shape, if the column line 45 is located above the corresponding P-type region 141, it is necessary to form the contact plug 144 directly from 5 There is no.

 In order to form the P-type region 141 having the above shape with self-alignment, the trench separation 140 is not formed in the entire Y direction in parallel with the column line 45, but the P-type region 14 is formed. After forming at a portion where 1 is formed, it is formed in a brick-laid lattice shape as shown in FIG. 16 and a word line 44 is formed thereon, and then a p-type impurity is implanted.

 Note that the memory cell array having this configuration also has an equivalent circuit as shown in FIG. 18 similarly to the ones shown in FIGS.

Also in the memory cell arrays shown in FIGS. 14 to 18, one column line 45 is formed via the via hole 47 -intermediate wiring film 46 -contact plug 48 or via the contact plug 144. And in the word line direction (X direction) When V gw is applied to one read line 44 and V dw is applied to one column line at the time of writing, the voltage is connected to the adjacent P-type region 41. Data is written to the adjacent memory cell. Therefore, in order to prevent this, similarly to the memory cell of the first embodiment, a write-blocking voltage is applied to the p-type region 41 (adjacent column line 45) on the opposite side of the adjacent memory cell. Apply. The method of applying the write inhibit voltage may be the same as the method of applying the write inhibit voltage in the memory cell array shown in FIGS.

 The application of the write blocking voltage described in FIGS. 10 to 13 is a necessary process when both the left and right program areas 16 L and R of each memory cell are used as storage areas. When 1-bit cell storage is performed using only one program area of each memory cell, application of a write inhibit voltage is not required. This is because, as described above, in the reading of the program area on the target side, the program no-an program in the opposite program area does not affect the reading result.

 Even when both the program area 16 L and R of the memory cell are used as the storage area, the column line and the P-type area of the memory cell adjacent in the X direction as shown in FIGS. By configuring the array separately, it is possible to eliminate the need for a write inhibit voltage.

In the memory cell array of FIG. 19, each memory cell is formed diagonally as shown by a broken line in FIG. 19, and the left p-type region 41 L, the right P-type region 41 R and A channel region 42 is formed. The lower left P-type region 41 is connected to the left column line 45 L by a contact plug 48, and the upper right right p-type region 41 R is connected to the right column line 45 R by a contact plug 48. . In this memory cell array, regions other than the memory cells indicated by broken lines in FIG. On the surface of the semiconductor substrate, the p-type region and the column line are not shared in the memory cell adjacent in the X direction, and the high voltage applied to the column line at the time of writing is not applied to the adjacent memory cell. It is not applied to

 In this embodiment, in the plan view of the memory cell array, each memory cell is laid out from the upper right to the lower left, but may be formed from the upper left to the lower right.

 In the case of the memory cell array having the structure shown in FIG. 9, as shown in FIG. 21, the p-type regions (p-type linear regions) 13 and 14 of adjacent memory cells are formed separately on the left and right. By isolating the gap with a trench-shaped insulating film, the equivalent circuit is again as shown in FIG. 20 and the write-blocking voltage can be eliminated.

 In the memory cell array of each of the above embodiments, the word line is formed of a polysilicon film. However, by stacking a cobalt film and forming silicide, the resistance can be further reduced.

FIG. 22 shows an example in which a memory cell has a three-dimensional structure. The channel region 20 between the p-type linear regions 13 and 14 formed in a stripe shape is trench-etched by trench etching to form an ONO film 52 orthogonal to the trench, and A lead line 53 also serving as a gate electrode is formed along the side and bottom surfaces of the trench. As a result, even if the distance between the p-type linear regions 13 and 14 is reduced, the channel region 20 is formed around the trench, so that high integration in the X direction can be achieved while securing the channel length. Can be. FIG. 23 is a diagram showing a structure of a memory cell array having a configuration in which the trench etching of FIG. 22 is deeper and a P-type region is also formed on the bottom surface of the trench. In this configuration, p-type regions (source and drain) are formed on the surface of the semiconductor substrate and the bottom of the trench, and the channel is formed above and below the semiconductor substrate 11, so that the integration degree in the X direction is extremely high. It can be higher. FIG. 24 is a diagram showing the structure of a P-channel twin M〇 NOS memory cell. The twin MONOS memory cell uses the sidewall technology on both sides of the gate (word gate) 207 of a normal M〇S transistor. A sidewall control gate 205 L, R and a nitride film 206 L, R are formed, thereby shortening the channel length.

 High-efficiency writing can be realized for the memory cell of this twin MONOS structure by forming the source node with a p-type diffusion layer.

 FIG. 25 is a block diagram of a p-channel MONOS memory chip incorporating the above memory cell array. As described above, there are various types of connection types for the memory cell array, such as VGA type, NOR type, and contactless type. In any case, data can be written, read, and erased in this block. . In addition, any of the above types of memory cells may be used for the memory cell array.

 This memory chip includes a memory cell matrix 61 arranged in a matrix, an address buffer 65, an X address decoder 62, a Y address decoder 64, a Y gate 63, a write circuit 66, a read circuit 67, and , An input / output buffer 68, and various voltage generating circuits 70, 71, 72. The X-address decoder 62 is connected to the read line of the memory cell matrix 61. The Y gate 63 is connected to the column lines of the memory cell matrix 61, and selection information for selecting which column line is input from the Y address decoder 64.

 The memory cell matrix 61 is one of the various memory cell matrices shown in FIGS. It is formed in the n-type well region 64. The address buffer 65 buffers externally input address information and inputs it to the X address decoder 62 and the Y address decoder 64. The X address decoder 62 and the Y address decoder 64 select predetermined lead lines and column lines based on the input address information.

The X address decoder 62 generates a voltage from the voltage generator 71 on the selected word line. Apply the generated voltage. Voltage generating circuit 71 generates a voltage set according to a write operation, a read operation, and an erase operation.

 Y address decoder 64 transmits selection information indicating which column line is selected to Y gate 63. The Y gate 63 connects the selected (two) column lines to the write circuit 66, the read circuit 67, the voltage generation circuit 70, and the like. The voltage generation circuit 70 generates a write voltage, a write block voltage, a drain voltage, a positive voltage for erasure, and the like according to the write operation, the read operation, and the erase operation.

 At the time of writing, the writing data is buffered in the input / output buffer 68, and the writing circuit 66 writes this data to the bit of the designated address. At the time of reading, the read circuit 67 reads the bit data of the specified address, and buffers this data in the input / output buffer 68. In addition, as shown in FIG. 26, the above-described P-channel transistor cell (the above-mentioned memory cell is a single transistor cell, so that the memory cell A CMOS logic circuit can be formed using MONOS transistors by forming N-channel memory cells with inverted polarity. This CMOS logic circuit can be used for a peripheral circuit of a semiconductor memory or the like.

 Also, as shown in Fig. 27, the p-channel MONOS memory cell array area and the n-channel MONOS memory cell array area are mixedly arranged on one memory chip, and the different characteristics are used to store the information to be stored. You may use it properly according to a kind and content. Even with such a configuration, in addition to the above-described P-channel MONOS manufacturing process, an ion implantation process for forming an n-type active region is only added, so that the manufacturing cost does not increase so much.

As described above, according to the present invention, the threshold voltage in the erased state is changed to the state in the written state by performing BBHE injection as a p-channel nonvolatile memory cell. Since the absolute value becomes larger with respect to the threshold voltage, the memory cell does not become depleted due to over-erasing, and a memory cell having a large tolerance for the variation of each memory cell can be obtained.

 According to the present invention, the charge trap layer is made of a non-conductor and charges are trapped at both ends thereof, so that one cell can store 2-bit data.

 According to the present invention, by injecting charges into the charge trapping layer by BBHE injection, charges can be injected with high efficiency, and simultaneous writing of many bits becomes possible. Therefore, high throughput writing can be equivalently realized.

 According to the present invention, since the virtual ground array is used, the source lines can be omitted, and a memory cell array having a simpler configuration can be realized. In this case, the left and right p-type regions (source / drain) of the memory cells arranged in the Y direction are each composed of one p-type linear region, which simplifies the manufacturing process and reduces this type. The linear region can be used also as a column line.

 Furthermore, in the case of a virtual 'ground' array, the first p-type region of one of the two adjacent memory cells in the X direction is shared with the second p-type region of the other memory cell. Therefore, one p-type linear region can also serve as the first and second p-type regions and the column line, and the structure can be further simplified.

 According to the present invention, at the time of writing by BBHE, a write blocking voltage is applied to a p-type region on the opposite side of an adjacent memory cell that supplies a column line for applying a write voltage to a target memory cell. As a result, even if the virtual ground array shares a column line, it is possible to prevent writing to the adjacent memory cell.

According to the present invention, p-type linear regions are formed in stripes on the surface of an n-type well. In addition, since the memory cell array can be configured only by forming the ONO film and the conductive film in a stripe shape so as to be orthogonal to this, the memory cell array can be realized with a simple configuration and a simple manufacturing process. According to the present invention, since the channel region is formed into a three-dimensional structure by trench etching, high integration in the X direction can be achieved without shortening the channel length.

 According to the present invention, since the silicide film is formed on one or both of the p-type linear region and the conductive film, the conductivity of the silicide film is improved, and the resistance of the column line and the word line is reduced. In addition, data reading speed can be improved. Industrial applicability

 INDUSTRIAL APPLICABILITY The nonvolatile semiconductor memory device of the present invention has a simple configuration, has a high degree of integration, and can perform writing with high efficiency. Therefore, the nonvolatile semiconductor memory device is suitable as a memory device for small information devices such as mobile phones. .

Claims

The scope of the claims

(1) Using a semiconductor substrate with an n-type well formed near the surface,

 First and second p-type regions formed at predetermined intervals on the surface of the n-type well;

 A non-conductive charge trap layer formed via a tunnel oxide film above a channel which is a region between the first and second p-type regions on the surface of the n-type well, and is insulated above the charge trap layer. A gate electrode formed through the film; and

 A first program region that is a partial region of the charge trap layer on the first p-type region side, or a second program region that is a partial region of the charge trap layer on the second p-type region side The program is performed by trapping charge in the program area of

 In the reading of the first or second program area, a negative voltage is applied to the P-type area on the opposite side to the program area, and a threshold voltage at the time of non-programming and a threshold voltage at the time of programming are applied to the gate electrode. A memory cell that is operated by applying a read voltage that is a voltage between threshold voltages

 Nonvolatile semiconductor memory device in which a plurality of are arranged.

 (2) The nonvolatile semiconductor memory device according to claim 1, wherein two bits are programmed in one memory cell by setting the first and second program areas independently to a programmer non-program state.

(3) A negative voltage is applied to one of the first and second p-type regions, a positive voltage is applied to the gate electrode, and the other p-type region is opened or grounded. 2. The nonvolatile semiconductor memory device according to claim 1, wherein charges are injected into a program region on the p-type region side to which the negative voltage is applied by charge injection by electrons generated by band-to-band tunneling.

(4) A write negative voltage is applied to one of the first and second p-type regions, a positive voltage is applied to the gate electrode, and the other p-type region is opened or grounded. 3. The nonvolatile semiconductor memory device according to claim 2, wherein charges are injected into a program region on the p-type region side to which the negative voltage is applied, by charge injection by electrons generated by band-to-band tunneling by setting the state.

(5) The charge of the first and second program regions is erased by applying a positive voltage to the n-type well and extracting the entire channel FN by applying a negative voltage to the gate electrode. The non-volatile semiconductor storage device according to the above.

 (6) While the semiconductor substrate is grounded, a first negative voltage is applied to the n-type well, and a second negative voltage having an absolute value larger than the first negative voltage is applied to the first and second p-type regions. The first and second programs are applied by applying a negative high voltage to the gate electrode and further by applying a hot negative voltage having a larger absolute value than the second negative voltage to the gate electrode, thereby injecting the substrate hot hole. 3. The nonvolatile semiconductor memory device according to claim 1, wherein the charge in the region is erased.

 (7) The plurality of memory cells are arranged in a matrix of X (columns) and Y (rows), and a lead line serving as a gate electrode of the memory cells arranged in the X direction is provided for each row.

 A bit line to which the first p-type region of the memory cells arranged in the Y direction is connected is provided for each column, and a second p-type region of the memory cell is connected to each block. 2. The nonvolatile semiconductor memory according to claim 1, further comprising a source line.

(8) The plurality of memory cells are arranged in a matrix of X (columns) and Y (rows), and a gate line serving as a gate electrode of the memory cells arranged in the X direction is provided for each row.

A first column line which is a wiring in the Y direction to which the first P-type region of the memory cells arranged in the Y direction is connected, and a second p-type region of the memory cell 2. The nonvolatile semiconductor memory device according to claim 1, wherein a second column line, which is a wiring in the Y direction to which the regions are connected, is provided for each column.

 (9) The first and second column lines are formed by one ρ-type linear region, respectively, and also serve as the first and second ρ-type regions of the memory cell, respectively. Nonvolatile semiconductor memory device.

 (10) The plurality of memory cells are arranged in a matrix of X (column) Υ (row).

A lead line serving as a gate electrode of the memory cells arranged in the X direction is set to ΒΧU,

 The first ρ-type region of the memory cells arranged in the Υ direction is connected to the first column line, which is the Υ direction wiring, and the second ρ-type region of the memory cell is connected to the first ρ-type region. 5. The nonvolatile semiconductor memory device according to claim 4, wherein a second column line, which is a wiring in the Υ direction, is provided for each column.

 (11) The nonvolatile semiconductor memory device according to claim 10, wherein one first column line and a second column line adjacent to the first column line in the X direction are commonly formed.

 (12) The nonvolatile semiconductor device according to claim 11, wherein the common first and second column lines are formed of one ρ-type linear region, and also serve as a ρ-type region of the memory cell. Storage device.

 (13) The first and second column lines are each formed of one ρ-type linear region, and also serve as the first and second ρ-type regions of the memory cell, respectively. 3. The nonvolatile semiconductor memory device according to 1.

(14) When injecting charge into the first or second program area of a memory cell, write negative voltage to the column line which is the ρ-type area on the program area side where the charge of this memory cell is injected. A positive voltage is applied to the gate line, which is the gate electrode of this memory cell, and the word line and the column line are shared. 12. The nonvolatile semiconductor memory device according to claim 11, wherein a write-blocking voltage that is a negative voltage having an absolute value smaller than the write negative voltage is applied to a column line opposite to the column line.

 (15) On the surface of the n-type well of the semiconductor substrate, a plurality of p-type linear regions forming source, drain, and column lines are formed in stripes, and an ONO film serving as a charge trapping layer is formed on top of them. A nonvolatile semiconductor memory device further comprising a conductive film serving as a lead line and a gate electrode formed thereon in a stripe shape so as to be orthogonal to the p-type linear region.

 (16) A groove parallel to the p-type linear region is formed in a gap between the plurality of p-type linear regions on the semiconductor substrate, and the ONO film is formed along a wall surface and a bottom surface of the groove. 16. The non-volatile semiconductor storage device according to claim 15, formed by forming.

 (17) The semiconductor substrate has a bottom having a width of the p-type linear region in the Y direction and a groove having a depth corresponding to the channel region sandwiching an upper surface of the width of the p-type linear region. The p-type linear region is formed at the bottom and the top of the groove, and the {N} film is formed along the wall and bottom of the groove. Non-volatile semiconductor storage device.

 (18) The nonvolatile semiconductor memory device according to claim 15, wherein a silicide film is formed on one or both of the p-type linear region and the conductive film.

 (19) A plurality of island-shaped p-type regions formed on the surface of the semiconductor substrate and arranged in a matrix of X (columns) and Y (rows);

 An ONO (Oxide—Nitride—Oxide) film formed on the semiconductor substrate;

 A plurality of word lines formed in stripes on the ONO film in gaps in the X direction of the p-type region group arranged in a matrix;

A plurality of power lines formed in a stripe pattern at the same pitch as the pitch in the X direction of the p-type region group arranged in a matrix on a layer further above the word line; Arranged in the matrix via the layer between the column line and the code line! A local wiring that connects two p-type regions in the X direction, wherein the connection direction of each p-type region arranged in the Y direction is alternately left and right in each column;

 Has,

 A nonvolatile semiconductor memory device in which each local wiring is connected via a via hole to a column line formed thereon.

 (20) A method for manufacturing a nonvolatile semiconductor memory device according to claim 19,

 On the surface of the semiconductor substrate, a trench insulating film for electrically isolating elements from each other is formed in a stripe-shaped region that is a gap in the Y direction of the matrix region group where the p-type region group is to be formed; Forming the word line by a metal layer, and then forming the P-type region by ion implantation of self-alignment by the ground line.

 (2 1) A plurality of p-type regions and trench insulating films formed on the surface of a semiconductor substrate, which are combined in the vertical direction (Y direction) and the horizontal direction (X direction) so that they are alternated. A horizontally-long rectangular p-type region and a vertically-long rectangular trench insulating film arranged in a lattice,

 A 〇N〇 (Oxide—Nitride—Oxide) film formed on the semiconductor substrate;

 A plurality of striped word lines formed in a gap in the X direction between the arranged P-type regions on the ONO film;

 A plurality of column lines formed in a stripe shape above the arrayed p-type regions at a pitch of half the X-direction pitch of the p-type regions above the arranged p-type regions;

Each column line has a contact hole in the p-type region formed below it. Non-volatile semiconductor memory device connected via

 (22) A method for manufacturing a nonvolatile semiconductor memory device according to claim 21, wherein:

 The trench insulating film is formed on the surface of the semiconductor substrate, the ONO film is formed thereon, and the pad line is formed of a metal layer, and then the p-type region is ion-implanted with self-line by the above-described lead line. A method for manufacturing a nonvolatile semiconductor memory device, characterized by being formed by:

 (23) an ONO film formed on an upper layer of a semiconductor substrate;

 A plurality of lead lines formed in the X direction on the upper layer of the ONO film; a plurality of pairs of left column lines and right column lines formed in the Y direction further above the lead lines;

 A plurality of left P-type regions formed at predetermined intervals in a lower region of the left column line on the surface of the semiconductor substrate; and a plurality of right p-type regions formed at predetermined intervals in a lower region of the right column line. ,

 Has,

 Further, an absolutely green region is formed on the surface of the semiconductor substrate, which associates one left p-type region with one right p-type region obliquely opposed to a channel region that is a lower layer region of one word line. Nonvolatile semiconductor memory characterized by the following:

(24) A source and a drain formed at predetermined intervals on an n-type well surface formed near the surface of the semiconductor substrate, and a channel, which is a region between the source and the drain on the n-type well surface. A P-channel cell including: a nonconductive charge trapping layer formed above through a tunnel oxide film; and a gate electrode formed above the charge trapping layer through an insulating film;

A source and a drain are formed at a predetermined interval on the surface of the p-type well formed near the surface of the semiconductor substrate, and a tunnel oxide film is formed above a channel which is a region between the source and the drain on the surface of the P-type well. Formed through An N-channel cell including: a nonconductive charge trapping layer; a gate electrode formed above the charge trapping layer via an insulating film;

 Are formed adjacently on the same semiconductor substrate, and their drains and gates are commonly connected.

 (25) first and second p-type regions formed at predetermined intervals on the surface of an n-type well formed near the surface of the semiconductor substrate; and the first and second p-type regions formed on the surface of the n-type well. A non-conductive charge trap layer formed above a channel, which is a region between the p-type regions, through a tunnel oxide film; and a gate electrode formed above the charge trap layer via an insulating film. And a P channel array region in which a plurality of P channel cells including

 First and second n-type regions formed at predetermined intervals on a P-type well surface formed near the surface of a semiconductor substrate; and between the first and second n-type regions on the p-type well surface An N-channel cell including: a nonconductive charge trapping layer formed above a channel, which is a region of the above, via a tunnel oxide film; and a gate electrode formed above the charge trapping layer via an insulating film. A plurality of N-channel array regions,

 Non-volatile semiconductor memory characterized by forming on a same semiconductor substrate