WO2004091136A3 - Multi-node system in which global address generated by processing subsystem includes global to local translation information - Google Patents

Multi-node system in which global address generated by processing subsystem includes global to local translation information Download PDF

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Publication number
WO2004091136A3
WO2004091136A3 PCT/US2004/010237 US2004010237W WO2004091136A3 WO 2004091136 A3 WO2004091136 A3 WO 2004091136A3 US 2004010237 W US2004010237 W US 2004010237W WO 2004091136 A3 WO2004091136 A3 WO 2004091136A3
Authority
WO
WIPO (PCT)
Prior art keywords
global address
global
active device
node
address generated
Prior art date
Application number
PCT/US2004/010237
Other languages
French (fr)
Other versions
WO2004091136A2 (en
Inventor
Robert E Cypher
Anders Landin
Erik E Hagersten
Original Assignee
Sun Microsystems Inc
Robert E Cypher
Anders Landin
Erik E Hagersten
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc, Robert E Cypher, Anders Landin, Erik E Hagersten filed Critical Sun Microsystems Inc
Priority to EP04749678A priority Critical patent/EP1611513B1/en
Priority to AT04749678T priority patent/ATE491991T1/en
Priority to DE602004030548T priority patent/DE602004030548D1/en
Publication of WO2004091136A2 publication Critical patent/WO2004091136A2/en
Publication of WO2004091136A3 publication Critical patent/WO2004091136A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1072—Decentralised address translation, e.g. in distributed shared memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0822—Copy directories

Abstract

A system may include a plurality of nodes. Each node may include one or more active devices coupled to one or more memory subsystems. An active device included in one of the nodes includes a memory management unit configured to receive a virtual address generated within that active device and to responsively output a global address identifying a coherency unit. A portion of the global address identifies a translation function. A memory subsystem included in the node is configured to perform the translation function identified by the portion of the global address on an additional portion of the global address in order to obtain a local physical address of the coherency unit. Each active device included in the node is configured to use the portion of the global address identifying the translation function when determining whether a local copy of the coherency unit is currently stored in a cache associated with that active device.
PCT/US2004/010237 2003-04-04 2004-04-02 Multi-node system in which global address generated by processing subsystem includes global to local translation information WO2004091136A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP04749678A EP1611513B1 (en) 2003-04-04 2004-04-02 Multi-node system in which global address generated by processing subsystem includes global to local translation information
AT04749678T ATE491991T1 (en) 2003-04-04 2004-04-02 MULTI-NODE SYSTEM WHERE THE GLOBAL ADDRESS GENERATED BY A PROCESSING SUBSYSTEM INCLUDES GLOBAL-TO-LOCAL TRANSLATION INFORMATION
DE602004030548T DE602004030548D1 (en) 2003-04-04 2004-04-02 MORE NOTIFICATION SYSTEM WHERE THE GLOBAL ADDRESS CREATED BY A PROCESSING SUB-SYSTEM INCLUDES GLOBAL-TO-LOCAL TRANSLATION INFORMATION

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US46057903P 2003-04-04 2003-04-04
US60/460,579 2003-04-04

Publications (2)

Publication Number Publication Date
WO2004091136A2 WO2004091136A2 (en) 2004-10-21
WO2004091136A3 true WO2004091136A3 (en) 2005-01-20

Family

ID=33159783

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/010237 WO2004091136A2 (en) 2003-04-04 2004-04-02 Multi-node system in which global address generated by processing subsystem includes global to local translation information

Country Status (5)

Country Link
US (1) US7360056B2 (en)
EP (1) EP1611513B1 (en)
AT (1) ATE491991T1 (en)
DE (1) DE602004030548D1 (en)
WO (1) WO2004091136A2 (en)

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US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
US7685319B2 (en) 2004-09-28 2010-03-23 Cray Canada Corporation Low latency communication via memory windows
US8249089B2 (en) * 2006-09-29 2012-08-21 Intel Corporation Methods for pushing address translations mappings to PCI express endpoints
US9069672B2 (en) * 2009-06-12 2015-06-30 Intel Corporation Extended fast memory access in a multiprocessor computer system
US9128632B2 (en) 2009-07-16 2015-09-08 Netlist, Inc. Memory module with distributed data buffers and method of operation
US20150370721A1 (en) * 2013-01-31 2015-12-24 Hewlett-Packard Development Company, L.P. Mapping mechanism for large shared address spaces
CN110428855B (en) 2013-07-27 2023-09-22 奈特力斯股份有限公司 Memory module with local synchronization
US9542333B2 (en) 2014-12-04 2017-01-10 Qualcomm Incorporated Systems and methods for providing improved latency in a non-uniform memory architecture
US9575881B2 (en) 2014-12-04 2017-02-21 Qualcomm Incorporated Systems and methods for providing improved latency in a non-uniform memory architecture
US9892058B2 (en) * 2015-12-16 2018-02-13 Advanced Micro Devices, Inc. Centrally managed unified shared virtual address space
EP3469480B1 (en) 2016-04-25 2023-12-27 Netlist, Inc. Method and apparatus for uniform memory access in a storage cluster
US10970118B2 (en) 2017-08-02 2021-04-06 Advanced Micro Devices, Inc. Shareable FPGA compute engine
US11422812B2 (en) 2019-06-25 2022-08-23 Advanced Micro Devices, Inc. Method and apparatus for efficient programmable instructions in computer systems

Citations (3)

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US5822785A (en) * 1992-12-18 1998-10-13 Fujitsu Limited Data transfer using local and global address translation and authorization
US5896501A (en) * 1992-12-18 1999-04-20 Fujitsu Limited Multiprocessor system and parallel processing method for processing data transferred between processors
US6275900B1 (en) * 1999-01-27 2001-08-14 International Business Machines Company Hybrid NUMA/S-COMA system and method

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US6088768A (en) 1993-12-28 2000-07-11 International Business Machines Corporation Method and system for maintaining cache coherence in a multiprocessor-multicache environment having unordered communication
US5845331A (en) * 1994-09-28 1998-12-01 Massachusetts Institute Of Technology Memory system including guarded pointers
US5940870A (en) * 1996-05-21 1999-08-17 Industrial Technology Research Institute Address translation for shared-memory multiprocessor clustering
US5892970A (en) 1996-07-01 1999-04-06 Sun Microsystems, Inc. Multiprocessing system configured to perform efficient block copy operations
US5887138A (en) * 1996-07-01 1999-03-23 Sun Microsystems, Inc. Multiprocessing computer system employing local and global address spaces and COMA and NUMA access modes
US5802582A (en) 1996-09-10 1998-09-01 International Business Machines Corporation Explicit coherence using split-phase controls
WO1999012103A2 (en) 1997-09-05 1999-03-11 Sun Microsystems, Inc. Scalable shared memory multiprocessor system
US6209064B1 (en) * 1998-01-07 2001-03-27 Fujitsu Limited Cache coherence unit with integrated message passing and memory protection for a distributed, shared memory multiprocessor system
US6604184B2 (en) * 1999-06-30 2003-08-05 Intel Corporation Virtual memory mapping using region-based page tables
US6738889B2 (en) 1999-07-12 2004-05-18 International Business Machines Corporation Apparatus and method for providing simultaneous local and global addressing with hardware address translation
US6574714B2 (en) * 2001-02-12 2003-06-03 International Business Machines Corporation Efficient instruction cache coherency maintenance mechanism for scalable multiprocessor computer system with write-back data cache
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Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5822785A (en) * 1992-12-18 1998-10-13 Fujitsu Limited Data transfer using local and global address translation and authorization
US5896501A (en) * 1992-12-18 1999-04-20 Fujitsu Limited Multiprocessor system and parallel processing method for processing data transferred between processors
US6275900B1 (en) * 1999-01-27 2001-08-14 International Business Machines Company Hybrid NUMA/S-COMA system and method

Also Published As

Publication number Publication date
EP1611513A2 (en) 2006-01-04
US7360056B2 (en) 2008-04-15
WO2004091136A2 (en) 2004-10-21
ATE491991T1 (en) 2011-01-15
DE602004030548D1 (en) 2011-01-27
EP1611513B1 (en) 2010-12-15
US20040260905A1 (en) 2004-12-23

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