WO2004079789A2

WO2004079789A2 - Interstage isolation in darlington transistors

Info

Publication number: WO2004079789A2
Application number: PCT/US2004/006278
Authority: WO
Inventors: Tat-Sing Paul Chow; Yi Tang
Original assignee: Rensselaer Polytechnic Institute
Priority date: 2003-03-05
Filing date: 2004-03-01
Publication date: 2004-09-16
Also published as: WO2004079789A3; TW200421613A

Abstract

A Darlington transistor has a semiconductor collector region of one conductivity type adapted to form a collector for the device. A conductive collector contact and a semiconductor base region of opposite conductivity type are connected to the collector region. First and spaced apart second semiconductor emitter regions of the one conductivity type are connected to the base region and a first conductive emitter contact is connected to the first emitter region with a second conductive emitter contact connected to the second emitter region. A first conductive base contact is connected to the base region and is conductively connected to the first emitter contact. A second conductive base contact is conductively isolated from the first base contact and is connected to the base region. A resistive trench region extends at least partly into the base region for resistively separating the base region into a first base region communicating with the first emitter contact and the second base contact, and a second base region communicating with the first base contact and the second emitter contact.

Description

INTERSTAGE ISOLATION IN DARLINGTON TRANSISTORS

CROSS REFERENCE TO RELATED APPLICATION [0001] This application claims priority on, and incorporates here by reference, U.S. provisional patent application 60/452,424 filed March 5, 2003.

FIELD AND BACKGROUND OF THE INVENTION

[0002] The present invention relates generally to the field semiconductor devices and, in particular, to Darlington transistors.

[0003] Fig. 1 is a schematic cross-section of a conventional silicon Darlington transistor and Fig. 2 is a schematic equivalent circuit model thereof. The Darlington transistor 10 is two BJTs (Base-Junction-Transistors) T1 and T2, cascaded together to provide higher current gain. In silicon, most power bipolar transistors use double diffusion technique, hence the structure in Fig. 1 is used for silicon Darlington transistors.

[0004] Silicon Carbide (SiC) has long been recognized as the choice for high voltage, high temperature, high power applications. With the development of power devices and power electronics, silicon power devices are reaching their material limits. Wide band gap materials such as SiC and GaN are therefore considered as an alternative for power electronics application especially under hostile environment. SiC is superior to silicon because of its wide band-gap, high critical electric field and superior thermal conductivity.

[0005] At high voltage rating, SiC BJTs suffer from trade-off between current gain and blocking voltage. Compared with BJTs, a monolithic Darlington transistor structure would ease the requirement on base drive current while maintaining the blocking voltage.

[0006] SiC Schottky rectifiers of 300V and 600V rating are commercially available from Infineon Technologies. SiC BJT with 1.8kV and current gain of 20 was also experimentally demonstrated (S-H. Ryu, A. K. Agarwal, R. Singh and J. W. Palmour, 58" Annual Device Research Conference, Denver, CO, June, 2000).

[0007] To further increase the blocking voltage, however, current gain has to be sacrificed. One viable way of achieving both high voltage and high current gain is to cascade two BJTs in series to form what is called the Darlington configuration.

[0008] A problem to be solved by the present invention concerns the fact that in silicon, most bipolar junction transistors are made using double-diffusion, which means both the base region and the emitter region are formed by diffusion. All the SiC BJTs demonstrated to date used an epitaxial base, with the variation of either implanting emitter or using an epi-grown emitter. See: Y. Wang, W. Xie, J. A. Cooper, Jr., M. R. Meiloch and J. W. Palmour, Silicon Carbide and Related Materials Conf, pp. 809-812, Kyoto, Japan 1995; and Y. Tang, J. Fedlson, and T. P. Chow, 58" Annual Device Research Conference, Denver, CO, June, 2000. For silicon Darlington transistors, the isolation will not be difficult since the definition of P-Base diffusion will automatically isolate the two stage devices. However, for the SiC counterpart, the P-Base is epi-grown so that the inventors have discovered that a special isolation step or structure is needed.

SUMMARY OF THE INVENTION [0009] It is an object of the present invention to provide a Darlington transistor having a semiconductor collector region of one conductivity type, e.g. an epi-grown P-Base region, adapted to form a collector for the device. A conductive collector contact and a semiconductor base region of opposite conductivity type, e.g. an N-epi region, are connected to the collector region. First and spaced apart second semiconductor emitter regions of the one conductivity type are connected to the base region and a first conductive emitter contact is connected to the first emitter region with a second conductive emitter contact connected to the second emitter region. A first conductive base contact is connected to the base region and is conductively connected to the first emitter contact. A second conductive base contact is conductively isolated from the first base contact and is connected to the base region. A resistive trench region extends at least partly into the base region for resistively separating the base region into a first base region communicating with the first emitter contact and the second base contact, and a second base region communicating with the first base contact and the second emitter contact.

[0010] The trench region extends either completely through the base region to completely separate the two parts of the base region from each other, or it extends partly into the base region to leave a high resistance gap which still serves to isolate the two parts of the base region from each other.

[0011] The various features of novelty which characterize the invention are pointed out with particularity in the claims annexed to and forming a part of this disclosure. For a better understanding of the invention, its operating advantages and specific objects attained by its uses, reference is made to the accompanying drawings and descriptive matter in which preferred embodiments of the invention are illustrated.

BRIEF DESCRIPTION OF THE DRAWINGS [0012] In the drawings:

[0013] Fig. 1 is a schematic cross-section of a conventional silicon

Darlington transistor; [0014] Fig. 2 is a schematic equivalent circuit model of Fig. 1 ;

[0015] Fig. 3 is a schematic cross-section of a SiC Darlington transistor of the present invention; [0016] Fig. 4 is a schematic cross-section of a SiC Darlington transistor of another embodiment of the present invention; [0017] Fig. 5 is a graph plotting peak current gain against isolation trench depth from the junction of a trench having a 5μm width to show simulated peak current gain for the device of the present invention;

[0018] Fig. 6 is a graph plotting current gain against base-to-emitter voltage V_BE for the device of the present invention;

[0019] Fig. 7 is a top plan view of a device fabricated according the present invention;

[0020] Fig. 8 is a graph plotting two curves of current gain against voltage V_BE for the device of the present invention having emitter trenches of 0.7μm and 0.55μm depths; [0021] Fig. 9 is a graph plotting two curves of current gain against collector arrent density forthe device of the present invention having emitter trenches of 0.7μm and 0.55μm depths; [0022] Fig. 10 is a Gummel plot of current against voltage V_BE for the device of the present invention at a collector voltage V_CE of 7V; [0023] Fig. 11 is a graph plotting curves of current gain against voltage

V_BE for the device of the present invention at different temperatures to illustrate temperature effects; [0024] Fig. 12 is a graph plotting current against voltage V_BE at various base currents to show the forward l-V characteristics of the Darlington transistor of the present invention; [0025] Fig. 13 is a graph plotting curves for the two transistors of a single stage BJTs of a device of the present invention, to show the common emitter current gain therefore; [0026] Fig. 14 is a graph plotting two curves like those of Fig. 13, for another device of the present invention; and [0027] Fig. 15 is a graph plotting current gain against temperature to show the temperature dependence of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] Referring again to the drawings, in which like reference numerals are used to refer to the same or similar elements, Fig. 3 illustrates a Darlington transistor 20 of the present invention and the structure for one possible solution. This solution is to isolate the two stages by a deep trench-etching 22 or oxide (e.g. SiO₂) or polysilicon, through the P-Base region 24 of the device which is epi-grown. The top P+ epi-layer 42, 46 is epi-grown to ensure good P-contact and at the same time avoid high temperature annealing of P+ implantation.

[0029] As shown in Fig. 3, the device is an implanted-emitter, epi-base BJT.

An alternative structure, an epi-emitter, epi-base BJT, can utilize the same structure for a SiC Darlington transistor. Fig. 4 shows this alternative structure for the invention.

[0030] In the structure of Fig. 4, the P-Base layer 24 is partly etched at trench

22, leaving a small region 26 of the P-Base at the trench bottom. The two stages are still isolated as long as the region 26 between the two stages provides a resistance large enough to prevent the second stage base current from coming to the first stage BJT.

[0031] The approach of the present invention ensures good isolation between the two stages when the region 26 is thin enough to provide a large enough resistor effect, as in Fig. 4, or if the trench 22 is etched through the junction to isolate the two stages completely as in Fig. 3.

[0032] As in known Darlington transistors, the device of the present invention also has an N-Epi layer or semiconductor collector region of one conductivity type 28, connected to, and spanning a semiconductive base region 24 of opposite conductivity type having two P-Base regions 24a and 24b, as well as an N+Substrate 30 and conductive collector layer 32. A conductor 34 connects a first emitter conductive layer 36 on the N+ emitter layer or first semiconductive emitter region 38 of the first stage transistor (T1 in Fig. 2) to the conductive base layer 40 on the P+ base layer or first semiconductor base region 42 of the second stage transistor (T2 in Fig. 2). Conductive base layer 44 is connected to the base P+ layer 46 of the device 20 to form the base of the Darlington transistor, and conductive emitter layer 48 is connected to the emitter N+ layer 50 to form the emitter of the device.

[0033] Fig. 5 shows the peak current gain for the monolithic Darlington transistor at different trench depth. Trench width used is 5μm. When the trench is not deep enough, the two stage BJTs are not isolated well, and the current gain approaches single stage current gain. Fig 6 illustrates simulated peak current gain.

[0034] The present invention incorporates an internal resistor to aid in the turn-off of the device. For Darlington transistor operation, device turn-off sometimes takes a relatively long time if the device is turned off in an open- base configuration, because it takes time for the electron-hole plasma in the first and especially second stage BJT to recombine and disappear and restore the device to the blocking state. Therefore, a common solution in a silicon Darlington is to incorporate resistors between the base and emitter of the two transistors, providing a path for carriers to be drawn out of the device faster. In the isolation scheme shown in Fig. 4, essentially an internal resistor is put between the first stage and second stage base. Therefore during device turn-off, an additional current path is provided for fast switching of the device.

[0035] One concern related to the internal resistor is to make sure in the on- state, the internal resistor does not shunt the first stage BJT. In other words, the forward drop across the resistor has to be larger than the built-in voltage of SiC junction (usually 2.5-3V). Therefore the design of the trench region 26 has to take that into consideration, assuming doping is 2x10¹⁷cm^"3 in the P-Base region 24 and epi thickness is 1 μm for region N-Epi 28.

[0036] Breakdown voltage of the invention is close to that of the single stage

BJTs. For the invention of Fig. 4, at the trench corner, since the etch is not complete, the electric field will extend along the un-etched part. Under this circumstances, the un-etched part acts as a junction termination extension.

[0037] For the invention of Fig. 3, the novelty of the structure is that the breakdown voltage will not be degraded because of the deep trench. Because the trench is filled with oxide, the corner electric field will be different from the UMOSFET structure where the trench is filled with polysilicon with low potential, which will bring a high field point at the trench corner and cause pre-mature breakdown. In this structure, the electric field lines could go through the oxide, and other than the disrupt of the electric field concentration due to different dielectric constant, the breakdown will not occur at the trench corner. Therefore the blocking voltage will be like single stage BJTs, caused by drift layer, base punch through or termination.

[0038] The present invention has silicon applications. Both the structures of

Figs. 3 and 4 are also valid for silicon Darlington device structures. As mentioned, double-implanted Darlingtons can realize the isolation by implantation. However, if the base region is formed by blanket implant, the same structures can be used in silicon Darlingtons, so that an integrated resistor can be incorporate.

[0039] Experiments have verbified the practicality of the invention.

[0040] 4H-SiC monolithic Darlington transistors according to the present invention in Fig. 3 were fabricated. Current.gain as a function of collector bias is shown in Fig. 6. The peak Current gain is around 450. A top view of the fabricated device is shown in Fig. 7.

[0041] Returning to Fig. 3, the invention has an epi-base, implanted-emitter, monolithic Darlington transistor with high peak current gain of 2000.

[0042] The nominal thickness and the doping of the P-Base or P-epi layer 24 and the N-Epi or N-drift layer 28 are 1 μm at 4x10¹⁷ cm^"3 and 12μm at 4x10¹⁵ cm^"3 respectively. The emitter implantation 38, 48 was done at 600°C using phosphorus with a total dose of 3 x 10¹⁵ cm^"3, subsequently annealed at annealing temperature of 1400°C for 15 mins. The two stage BJTs are isolated by isolation trench 22 of 1.7μm as shown in Fig. 3. Emitter region 38 of the first stage BJT and base region 24b of the second stage BJT are connected using connecting metal Ti/Mo at 36, 34, 40.

[0043] For implanted-emitter BJTs and Darlington transistors, base width can be adjusted by controlling the emitter trench depth and emitter implantation. The emitter trench depth is increased from 0.55μm to 0.7μm, resulting in a base width of 0.25μm instead of 0.4μm. The current gain of the single stage BJT is increased comparing to the previous case, as shown in Fig. 8. A 2x increase in the single stage BJT current gain brought about further increase (4x) in the Darlington current gain, because of the relationship βD » β1 β2. In Table I, the design parameters for different base widths is shown together with the measured peak gain for single stage BJT and Dariington transistor.

[0044] Table

[0045] Common emitter current gain is measured at a collector voltage of 7V, with the Gummel plot shown in Fig. 10. Device turns on when base-emitter junctions of both the BJTs are forward-biased. The maximum current gain is above 2000. Fig. 9 shows the current gain versus collector current density plot. Comparison is shown for the two different emitter trench depth. It is observed that even though the peak current gain is increased, the current gain at 50A/cm² (-0.3A collector current) is lower than that of the previous results.

[0046] At higher temperatures, current gain decreases very fast. This is because at room temperature, there is incomplete ionization in the base due to the deep level acceptors. The base carrier concentration increases as temperature goes up, leading to a quick drop in the current gain. Fig. 11 shows the current gain at different temperatures up to 225°C. The peak common-emitter current gain decreases to 62 at 225°C.

[0047] The present invention also provides an epi-base, implanted-emitter, monolithic Dariington transistor with high current gain (peak gain up to 450) in 4H-SiC.

[0048] In greater detail, and referring back to Fig. 3, an emitter trench first was formed using reactive ion etching (RIE). The emitter implantation 38, 50 was then done at 600°C using phosphorus with a total dose of 3 x 10¹⁵ cm^"3, with multiple implantations to achieve a box-profile with a junction depth of 0.3μm. The implants were subsequently annealed at different annealing temperatures (1200-1600°C). The device was terminated with three-step trench termination. Therefore no additional implantation steps were needed. The two stage BJTs were isolated by the isolation trench 22 of 1.7μm. The isolation trench was then filled with oxide. Emitter region 38 of the first stage BJT and base region of the second stage BJT were connected using connecting metal Ti/Mo as noted, over oxide (e.g. SiO₂) as inter-level dielectric.

[0049] The device of the invention shown in top view in Fig. 7, has an area of

800μm x 800μm, emitter finger width of 10μm and cell pitch of 33μm.

[0050] Good isolation is essential in making the monolithic Darlington transistor of the invention. As noted, for a well-isolated Darlington transistor, the device gain βD is expected to be βD ~ β1 β2 where β1 and β2 are the current gain of the first and second stages respectively.

[0051] If the isolation is not effective, the current gain will be smaller because of current cross-coupling between the input and output stages. Numerical simulations have been done for the design of good isolation trench. Simulated current flow lines for two isolation trench widths at 100A/cm² were modeled. For an isolation trench width of 2μm, part of the base current was shown to be diverted directly to the second stage. This part of the base current acted as part of the base current from the second stage BJT, causing a decrease in the overall current gain. For good isolation, therefore, the initial stage base current fed the first stage BJT. Current from the emitter of first-stage BIT was equal to the base current of the second-stage, because of the shorting of the two stages.

[0052] Fig. 5 shows the simulated peak current gain as a function of the isolation trench depth with a trench width of 5μm. As the trench depth is decreased to above the junction, the peak current gain approaches single- stage BJT gain, indicating all the base current from the first stage BJT flows into second stage BJT without being amplified. For the trench width simulated, the isolation trench depth need to be at least deeper than the junction, to ensure good isolation.

[0053] Simulations of the blocking characteristics show that the blocking voltage is not degraded by the isolation trench, even though the trench is deeper than the reverse-biased base-collector junction. The reason for this is because the trench is filled with oxide. The trench corner is not stressed as in the case of a UMOSFET where the trench is filled with polysilicon attached to a low (grounded) potential. In this device the electric field lines go through oxide, avoiding field crowding at the trench comer.

[0054] According to the simulated forward and blocking characteristics of the device with different trench depths, the optimized isolation trench depth is at least 0.2μm deeper than the junction for trench width of 5μm, corresponding to an overall isolation trench depth of 1.7μm in our process.

[0055] The forward l-V of the fabricated Darlington transistor is shown in Fig.

12, exhibiting turn-on voltage knee as expected, since the emitter-base junctions of both the BJTs need to be forward biased, and the second stage BJT cannot be saturated. For an 800μm x 8θ0μm device, forward drop at 0.3A (~50A/cm²) is around 7.5V.

[0056] The common emitter current gain is measured at a collector voltage of

7V, with the Gummel plot and current gain plot shown in Fig. 10 and Fig. 6, respectively. Device turns on when base-emitter junctions of both the BJTs are forward-biased. The maximum current gain is above 450. The Gummel plot in Fig. 10 is very similar to the simulation results. Darlington transistors can circumvent the problem with the current gain-blocking voltage trade-off in SiC BJTs.

[0057] In the test structure, the shorting terminal between first stage emitter and second stage base is also accessible, which enables the testing of single stage of constituent BJTs. The individual current gain of the two single stage BJTs has been measured. For the device shown in Fig. 10, the peak current gain of T1 and T2 are 25 and 21 , respectively, as shown in Fig. 13.

[0058] Two different trench widths (2μm and 5μm) were used for the

Darlington isolation trench. Experimental data shows that for the trench depth of 1.7μm, 2μm trench width is not enough to isolate the two stage BJTs at low current level. The measured Darlington current gain is much smaller than the product of the two single stage BJT gains. The devices with 5μm isolation trench width have good isolation. This is consistent with the simulation results shown in Fig. 5.

[0059] It is observed that the current gain of our monolithic Darlington transistors drops very fast as temperature increases. A similar effect is observed for single stage SiC BJTs due to increased ionization of base dopant at high temperature. [0060] The blocking voltage of the devices is lower than expected for the epi thickness (-1500V expected), which has been found to be dependent on the emitter anneal temperature. The low temperature(1200°C) samples yield higher blocking voltage (500V). For the low temperature annealed samples, the breakdown voltage was degraded by premature breakdown at the edge termination area.

[0061] In summary, the epi-base, implanted-emitter Darlington transistor of the invention is demonstrated in 4H-SL Both simulation and experimental results prove that the isolation trench needs to be deeper than the junction to ensure good isolation. Peak current gain of 450 is observed in devices with effective isolation.

[0062] The implanted-emitter, epi-base 4H-SiC Darlington transistor of the invention as shown in Fig. 7 has a maximum common emitter current gain above 80. The forward drop at 0.3A (~50A/crn²) is around 7.5V. The Darlington transistor exhibits negative temperature effect of current gain. The inter-stage isolation is achieved with trenches filled with oxide.

[0063] In the test structure, the shorting terminal between first stage emitter and second stage base is also accessible, which enables the testing of single stage of constituent BJTs. The individual current gain of the two single stage BJTs has been measured and is shown in Fig. 14. The maximum common emitter current gain is measured to be about 9, which is consistent with the relationship for Darlington transistor current gain, β = β1 x (β2 + 1 ). It also indicates that the two-stage BJTs are effectively isolated from each other with the oxide trenches.

[0064] The blocking voltage of the devices is lower than expected for the epi thickness (~ 1500V expected). One reason is that the isolation trench between the two-stage BJTs causes pre-mature breakdown due to field crowding at the trench corner. Numerical simulations show that the open- emitter breakdown voltage can be reduced as much as 40% when the isolation trench is 0.2μrn deeper than the base/collector junction. Other causes for the low blocking voltage are still unknown at present.

[0065] The temperature dependence of the peak current gain is shown in

Fig. 15. It is observed that current gain of the monolithic Darlington transistor drops very fast as temperature increases. A similar effect is observed for single stage Sic BJTs due to increased ionization of base dopant at high temperature. At 175°C, the current gain is less than 20.

[0066] The first monolithic Darlington transistor in 4H-SiC has thus been demonstrated. Current gain of over 80 was observed. High temperature effect has been demonstrated which shows similar effect to single stage BJTs.

[0067] While specific embodiments of the invention have been shown and described in detail to illustrate the application of the principles of the invention, it will be understood that the invention may be embodied otherwise without departing from such principles.

Claims

WHAT IS CLAIMED IS:

1. A semiconductor device comprising: a semiconductor collector region of one conductivity type adapted to form a collector for the device; a conductive collector contact connected to the collector region; a semiconductor base region of opposite conductivity type connected to the collector region; a first and a spaced apart second semiconductor emitter region of the one conductivity type connected to the base region; a first conductive emitter contact connected to the first emitter region; a second conductive emitter contact connected to the second emitter region; a first conductive base contact connected to the base region and conductively connected to the first emitter contact; a second conductive base contact which is conductively isolated from the first base contact and which is connected to the base region; and a resistive trench region extending at least partly into the base region for separating the base region into a first base region communicating with the first emitter contact and the second base contact, and a second base region communicating with the first base contact and the second emitter contact and for at least partly isolating the first and second base regions from each other; the second base contact forming the base of a Darlington transistor, the second emitter contact forming the emitter of the Darlington transistor and the collector contact forming the collector of the Darlington transistor.

2. The device of claim 1 , wherein the collector and base regions are epi-grown.

3. The device of claim 1 , wherein the trench region is an oxide.

4. The device of claim 1 , wherein the trench region extends entirely through the base region to fully isolate the first and second base regions from each other.

5. The device of claim 1 , wherein the trench region extends partly through the base region to leave a resistor gap for isolating the first and second base regions from each other.

6. The device of claim 1 , wherein the semiconductors base and collector regions are SiC regions.

7. The device of claim 1 , wherein the semiconductors base and collector regions are doped silicone regions.

8. The device of claim 1 , including a plurality of said devices in a 4H-SiC monolithic Darlington transistor arrangement.