WO2004068582A1 - 半導体装置及びその作製方法 - Google Patents
半導体装置及びその作製方法 Download PDFInfo
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- WO2004068582A1 WO2004068582A1 PCT/JP2003/016355 JP0316355W WO2004068582A1 WO 2004068582 A1 WO2004068582 A1 WO 2004068582A1 JP 0316355 W JP0316355 W JP 0316355W WO 2004068582 A1 WO2004068582 A1 WO 2004068582A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 283
- 238000000034 method Methods 0.000 title claims abstract description 72
- 239000000758 substrate Substances 0.000 claims abstract description 154
- 239000000853 adhesive Substances 0.000 claims abstract description 84
- 230000001070 adhesive effect Effects 0.000 claims abstract description 84
- 229910052751 metal Inorganic materials 0.000 claims abstract description 67
- 239000002184 metal Substances 0.000 claims abstract description 67
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 22
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 22
- 239000010408 film Substances 0.000 claims description 413
- 230000003287 optical effect Effects 0.000 claims description 48
- 238000004519 manufacturing process Methods 0.000 claims description 44
- 238000006243 chemical reaction Methods 0.000 claims description 40
- 239000004033 plastic Substances 0.000 claims description 36
- 229920003023 plastic Polymers 0.000 claims description 36
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 21
- 229910052710 silicon Inorganic materials 0.000 claims description 21
- 239000010703 silicon Substances 0.000 claims description 21
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 21
- 229920005989 resin Polymers 0.000 claims description 18
- 239000011347 resin Substances 0.000 claims description 18
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 16
- 238000010438 heat treatment Methods 0.000 claims description 11
- 239000010409 thin film Substances 0.000 claims description 11
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 229910052707 ruthenium Inorganic materials 0.000 claims description 3
- 229910052725 zinc Inorganic materials 0.000 claims description 3
- 229910052726 zirconium Inorganic materials 0.000 claims description 3
- 150000002739 metals Chemical class 0.000 claims description 2
- 229910052703 rhodium Inorganic materials 0.000 claims description 2
- 229910017709 Ni Co Inorganic materials 0.000 claims 1
- 238000004026 adhesive bonding Methods 0.000 claims 1
- 239000003292 glue Substances 0.000 claims 1
- 239000007769 metal material Substances 0.000 claims 1
- 239000004034 viscosity adjusting agent Substances 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 17
- 238000000926 separation method Methods 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 48
- 229920005591 polysilicon Polymers 0.000 description 48
- 239000010410 layer Substances 0.000 description 47
- 229910021417 amorphous silicon Inorganic materials 0.000 description 36
- 230000015572 biosynthetic process Effects 0.000 description 17
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 description 17
- 229910001930 tungsten oxide Inorganic materials 0.000 description 17
- 230000015654 memory Effects 0.000 description 15
- 229910052721 tungsten Inorganic materials 0.000 description 14
- 238000010586 diagram Methods 0.000 description 13
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 13
- 239000010937 tungsten Substances 0.000 description 13
- 239000011521 glass Substances 0.000 description 12
- 239000011229 interlayer Substances 0.000 description 12
- 108091006146 Channels Proteins 0.000 description 11
- 229910052739 hydrogen Inorganic materials 0.000 description 11
- 239000001257 hydrogen Substances 0.000 description 11
- 150000001298 alcohols Chemical class 0.000 description 10
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 8
- 239000011368 organic material Substances 0.000 description 8
- 230000008569 process Effects 0.000 description 7
- -1 quartz or glass Chemical compound 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 239000004820 Pressure-sensitive adhesive Substances 0.000 description 5
- 238000002425 crystallisation Methods 0.000 description 5
- 238000009434 installation Methods 0.000 description 5
- 230000035945 sensitivity Effects 0.000 description 5
- 230000004913 activation Effects 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229920000139 polyethylene terephthalate Polymers 0.000 description 4
- 239000005020 polyethylene terephthalate Substances 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 239000003054 catalyst Substances 0.000 description 3
- 230000008025 crystallization Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 150000002431 hydrogen Chemical class 0.000 description 3
- 229910052740 iodine Inorganic materials 0.000 description 3
- 230000001678 irradiating effect Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 238000009832 plasma treatment Methods 0.000 description 3
- 239000004417 polycarbonate Substances 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- NIXOWILDQLNWCW-UHFFFAOYSA-M Acrylate Chemical compound [O-]C(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-M 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- 229910052779 Neodymium Inorganic materials 0.000 description 2
- 239000004721 Polyphenylene oxide Substances 0.000 description 2
- 239000004743 Polypropylene Substances 0.000 description 2
- UCKMPCXJQFINFW-UHFFFAOYSA-N Sulphide Chemical compound [S-2] UCKMPCXJQFINFW-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229920002457 flexible plastic Polymers 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910052741 iridium Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 239000012860 organic pigment Substances 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 229910052762 osmium Inorganic materials 0.000 description 2
- PJQYNUFEEZFYIS-UHFFFAOYSA-N perylene maroon Chemical compound C=12C3=CC=C(C(N(C)C4=O)=O)C2=C4C=CC=1C1=CC=C2C(=O)N(C)C(=O)C4=CC=C3C1=C42 PJQYNUFEEZFYIS-UHFFFAOYSA-N 0.000 description 2
- 125000002080 perylenyl group Chemical group C1(=CC=C2C=CC=C3C4=CC=CC5=CC=CC(C1=C23)=C45)* 0.000 description 2
- CSHWQDPOILHKBI-UHFFFAOYSA-N peryrene Natural products C1=CC(C2=CC=CC=3C2=C2C=CC=3)=C3C2=CC=CC3=C1 CSHWQDPOILHKBI-UHFFFAOYSA-N 0.000 description 2
- 239000000049 pigment Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229920003207 poly(ethylene-2,6-naphthalate) Polymers 0.000 description 2
- 229920000515 polycarbonate Polymers 0.000 description 2
- 239000011112 polyethylene naphthalate Substances 0.000 description 2
- 229920001155 polypropylene Polymers 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000007790 solid phase Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 101100366710 Arabidopsis thaliana SSL12 gene Proteins 0.000 description 1
- 101100366711 Arabidopsis thaliana SSL13 gene Proteins 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 101100366561 Panax ginseng SS11 gene Proteins 0.000 description 1
- 101100366563 Panax ginseng SS13 gene Proteins 0.000 description 1
- 239000004734 Polyphenylene sulfide Substances 0.000 description 1
- 239000004954 Polyphthalamide Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000005499 laser crystallization Methods 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000005300 metallic glass Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920003055 poly(ester-imide) Polymers 0.000 description 1
- 229920002492 poly(sulfone) Polymers 0.000 description 1
- 229920000570 polyether Polymers 0.000 description 1
- 229920006380 polyphenylene oxide Polymers 0.000 description 1
- 229920000069 polyphenylene sulfide Polymers 0.000 description 1
- 229920006375 polyphtalamide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
- H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/1446—Devices controlled by radiation in a repetitive configuration
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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- H—ELECTRICITY
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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Definitions
- the present invention relates to a method for manufacturing a thin and lightweight semiconductor device. Specifically, the present invention relates to a method for manufacturing a semiconductor device on an organic resin member or a plastic substrate.
- a semiconductor device is a semiconductor device that includes a semiconductor element having an amorphous semiconductor film in an active region and a semiconductor element having a crystalline semiconductor film in an active region.
- Optical sensors are used in a wide range of fields such as facsimile machines, copiers, video cameras, and digital still cameras as sensors for converting images into electric signals.
- Semiconductors are mainly used as the material of the optical sensor, and silicon is a typical example of the semiconductor material.
- Optical sensors using silicon include those using a single crystal silicon or polysilicon film and those using an amorphous silicon film.
- An optical sensor using a single-crystal silicon or polysilicon film has the highest sensitivity in the infrared region around 800 nm, and has a sensitivity up to approximately ⁇ 110 nm.
- an optical sensor using amorphous silicon has little sensitivity to light in the infrared region, has the highest sensitivity near the center of the wavelength in the visible light region, around 500 to 600 nm, and approximates human visibility. It has sensing characteristics. For this reason, it is preferable that the optical sensor uses amorphous silicon.
- Optical sensors using amorphous silicon can be broadly classified into 1) resistance type and 2) diode type.
- the resistive type can obtain a large current because of its amplifying action as a transistor.However, since the amplified photocharge is large, even after the light is cut off, the amplified photocharge will not disappear. Poor response speed and small dynamic range due to light intensity.
- the diode-type optical sensor has a fast response speed because the depletion layer spreads in amorphous silicon and the photocharge generated when light is incident is not detected immediately. Is big. However, since the current due to photocharge is small, a capacitor for holding the charge or an element for amplifying and outputting the photocharge is required.
- An element that amplifies and outputs the current detected by the optical sensor as an output signal in a time-division manner is a bare IC that uses a single-crystal semiconductor (mainly a silicon semiconductor) field-effect transistor.
- a single-crystal semiconductor mainly a silicon semiconductor
- the IC type optical sensor has high speed and reliability as an amplifying element, but the cost is extremely high because the same number of bare chip ICs as the optical sensor is required. Also, a substrate on which a photoelectric conversion element (photoelectric conversion layer) such as amorphous silicon is formed, and a bare IC chip. Is required, the area occupied by the installation board such as a printed wiring board is widened, and this is an obstacle to the miniaturization of electronic devices equipped with optical sensors.
- the TFT-type optical sensor can form the active region of the TFT, which is an amplifying element, and the photoelectric conversion layer of the photoelectric conversion element on the same substrate, thereby reducing the area occupied by a printed circuit board or other installation substrate.
- the cost is lower than that of an IC-type optical sensor using single-crystal silicon.
- a TFT using a polysilicon film has higher electrical characteristics than a TFT using an amorphous silicon film, so that a high-speed response as an amplifying element is possible. Therefore, by forming the amplifying element by TFT using a polysilicon film, it is effective to detect a weak photocurrent. (For example, the official gazette of JP-A-6-275808 (pages 3-4, Fig. 1)).
- an optical sensor using a TFT in which an active region is formed by a polysilicon film as an amplifying element as shown in Japanese Patent Application Laid-Open No. 6-275808 is limited in the type of substrate due to the manufacturing process.
- a substrate that can withstand the crystallization temperature or activation temperature of silicon such as quartz or glass, could be used. This is because a relatively high temperature (eg, 500 ° C. or higher) heating step is required for crystallization or activation of silicon. Since the thickness of these substrates is large, there has been a problem that the volume and weight of components of the optical sensor increase.
- the present invention relates to a semiconductor device in which an active region is formed by a polysilicon film on a lightweight and thin, preferably flexible substrate or an organic member, and an active region formed by an amorphous silicon film.
- An object is to manufacture a semiconductor device including a semiconductor element in which a region is formed, typically, a semiconductor device including an optical sensor, a photoelectric conversion element, and a solar cell element. Disclosure of the invention
- a metal film, an insulating film, and a first amorphous semiconductor film are sequentially formed on a first substrate, the first amorphous semiconductor film is crystallized, and the crystallized semiconductor film is formed.
- a first semiconductor element is formed using the active region, a support is adhered to the second semiconductor element, separated between the metal film and the insulating film, and the separated insulating film is formed.
- a second substrate is adhered to the substrate and the support is peeled off, a second amorphous semiconductor film is formed on the first semiconductor element, and the second amorphous semiconductor film is used as an active region.
- a method for manufacturing a semiconductor device comprising forming a second semiconductor element to be used.
- a metal film, an insulating film, and a first amorphous semiconductor film are sequentially formed on a first substrate, the first amorphous semiconductor film is crystallized, and the crystallized semiconductor film is formed in an active region.
- a metal film, an insulating film, and a first amorphous semiconductor film are sequentially formed on a first substrate, the first amorphous semiconductor film is crystallized, and the crystallized semiconductor film is formed in an active region.
- a method for manufacturing a semiconductor device may be employed.
- a metal film, an insulating film, and a first amorphous semiconductor film are sequentially formed on a first substrate, the first amorphous semiconductor film is crystallized, and the crystallized semiconductor film is formed in an active region.
- adhere a support to the first semiconductor element using an adhesive adhere a support to the first semiconductor element using an adhesive, and separate the metal film and the insulating film from each other.
- a second amorphous semiconductor film is formed on the first semiconductor element. And forming a second semiconductor element using the second amorphous semiconductor film for an active region.
- a metal film, an insulating film, and a first amorphous semiconductor film are sequentially formed on a first substrate, the first amorphous semiconductor film is crystallized, and the crystallized semiconductor film is formed in an active region.
- a metal film, an insulating film, and a first amorphous semiconductor film are sequentially formed on a first substrate, the first amorphous semiconductor film is crystallized, and the crystallized semiconductor film is formed in an active region.
- the support may be peeled off by removing the pressure-sensitive adhesive, and then a method for manufacturing a semiconductor device may be provided.
- a metal oxide is formed between the metal film and the insulating film.
- peeling between the metal film and the insulating film may be performed between the metal film and the metal oxide film, in the metal oxide film, or between the metal oxide film and the insulating film.
- the first amorphous semiconductor film and the second amorphous semiconductor film have a feature including hydrogen.
- the first semiconductor element is characterized in that it is a thin film transistor.
- the second semiconductor element is characterized in that it is a diode or a thin film transistor.
- the crystallization is performed by using the first amorphous semiconductor.
- the method is characterized in that heat treatment is performed at a temperature higher than the temperature at which hydrogen in the conductor film is released or diffused.
- the metal film is formed of W, Ti, Ta, Mo, Cr, Nd, Fe, Ni, Co, Zr, Zn, Ru, and R. h, Pd, Os, Ir, or a single layer made of an alloy material or a compound material containing the element as a main component, or a laminate of these metals or a mixture thereof.
- the insulating film is a silicon oxide film, a silicon oxynitride film, or a metal oxide film.
- the second substrate is characterized by being a plastic substrate or an organic resin member.
- the semiconductor device includes an optical sensor, a photoelectric conversion element, or a solar cell.
- another invention is characterized by having a first semiconductor element using a crystalline semiconductor film for an active region on an adhesive and a second semiconductor element using an amorphous semiconductor film for an active region. It is a semiconductor device.
- a semiconductor device having a first semiconductor element using a crystalline semiconductor film for an active region and a second semiconductor element using an amorphous semiconductor film for an active region on a plastic substrate is also provided. Good.
- the semiconductor device further includes a first semiconductor element using a crystalline semiconductor film as an active region on an adhesive and a second semiconductor element using an amorphous semiconductor film as an active region, and the first semiconductor element and the second semiconductor element. Note that the two semiconductor elements are electrically connected.
- the semiconductor device may be as follows.
- the semiconductor device further includes a first semiconductor element using a crystalline semiconductor film for an active region and a second semiconductor element using an amorphous semiconductor film for an active region on a plastic substrate, wherein the first semiconductor element and the second semiconductor element are used.
- the semiconductor element may be a semiconductor device which is electrically connected.
- the adhesive is provided with release paper.
- the first semiconductor element is a thin film transistor.
- the second semiconductor element is a diode or a thin film transistor.
- the semiconductor device includes an optical sensor, a photoelectric conversion element, or a solar cell element.
- a semiconductor device including a semiconductor element having a polysilicon film in an active region on a plastic substrate and a semiconductor element having an amorphous silicon film in an active region. That is, an optical sensor, a photoelectric conversion element, a solar cell element, and the like having a TFT in which an active region is formed by a polysilicon film and a diode in which an active region is formed by an amorphous silicon film can be manufactured.
- the semiconductor device manufactured according to the present invention is formed on a plastic substrate, it is lighter and thinner than a conventional device.
- the semiconductor device is an optical sensor or a photoelectric conversion device
- detection is performed using a photoelectric conversion element.
- the amplified signal can be amplified by an amplifying element formed of a TFT having a polysilicon film in the active region, so that it is possible to detect weak visible light even if the light receiving area of the sensor is small.
- the thickness can be reduced, and the selectivity of the installation location increases, so that the area of the mounting substrate can be reduced and the optical sensor, the photoelectric conversion element, or The light receiving area of the solar cell element can be increased.
- FIG. 1 is a diagram showing Embodiment 1 of the present invention.
- FIG. 2 is a diagram showing a second embodiment of the present invention.
- FIG. 3 is a diagram showing Example 1 of the present invention.
- FIG. 4 is a diagram showing Example 1 of the present invention.
- FIG. 5 is a diagram showing a third embodiment of the present invention.
- FIG. 6 is a diagram showing a third embodiment of the present invention.
- FIG. 7 is a diagram showing a third embodiment of the present invention.
- FIG. 8 is a diagram showing Example 1 of the present invention.
- FIG. 9 is a diagram showing a second embodiment of the present invention.
- FIG. 10 is a diagram showing a second embodiment of the present invention.
- FIG. 11 is a diagram illustrating a method for mounting a semiconductor device of the present invention.
- a method for manufacturing a semiconductor device including a semiconductor element including an amorphous silicon film in an active region and a semiconductor element including a polysilicon film in an active region over a plastic substrate is described with reference to FIGS.
- a metal film 102 is formed on a substrate 101.
- the metal film 102 an element selected from W, T, Ta, Mo, Cr, Nd, Fe, Nu Co, Zr, Zn, Ru, Rh, Pd, Os, and Ir, or a main component containing the above element
- a single layer made of an alloy material or a compound material to be used, a stacked layer thereof, a single layer of a nitride thereof, or a stacked layer thereof may be used.
- the thickness of the metal film 102 is 10 nm to 200 nm, preferably 50 nm to 75 nm.
- an insulating film 103 is formed over the metal film 102.
- a metal oxide film 100 in an amorphous state is formed between the metal film 102 and the insulating film 103 with a thickness of about 2 to 5 nm.
- peeling is performed in a later step, separation occurs in the metal oxide film 100, at the interface between the metal oxide film 100 and the insulating film 103, or at the interface between the metal oxide film 100 and the metal film 102.
- a film formed using silicon oxide, silicon oxynitride, or a metal oxide material may be formed by a sputtering method or a plasma CVD method.
- the thickness of the insulating film 103 is twice or more the thickness of the metal layer 102, preferably, 150 nrr! Power of ⁇ 200nm ⁇ desirable.
- a film of a material containing at least hydrogen is formed over the insulating film 103.
- a film of a material containing at least hydrogen a semiconductor film, a nitride film, or the like can be used.
- a semiconductor film is formed.
- heat treatment for diffusing hydrogen contained in the film of the material containing hydrogen is performed. This heat treatment may be performed separately from the formation process of the crystalline semiconductor film if the temperature is 410 ° C. or higher, or the process may be omitted because it is also used.
- amorphous silicon film containing hydrogen is used as a material film containing hydrogen and a polysilicon film is formed by heating, a heat treatment at 500 ° C. or more is performed to crystallize the polysilicon film. Hydrogen can be diffused simultaneously with the formation.
- the TFT is formed by etching the polysilicon film into a desired shape by a known method.
- a polysilicon film 105 having a source region, a drain region, and a channel formation region, a gate insulating film covering the polysilicon film, and a polysilicon film over the channel formation region are formed.
- a source electrode 107 and a drain electrode 108 connected to a source region and a drain region through an interlayer insulating film 119, respectively.
- the interlayer insulating film 119 is formed of a plurality of insulating films for insulating the source electrode, the drain electrode, and the gate electrode.
- a photoelectric conversion element connected to the source electrode 107 of the TFT is formed on the interlayer insulating film 119.
- a diode is formed as a photoelectric conversion element.
- a first electrode 110 connected to the source electrode 107 is formed, and an amorphous silicon film 111 and a second electrode 112 serving as a photoelectric conversion layer are formed thereon.
- the amorphous silicon film 111 and the second electrode 112 are etched into a desired shape to form a diode.
- the wiring 1 13 connected to the second electrode of the diode is formed.
- a wiring 114 connected to the drain electrode 108 and connected to the output terminal is formed.
- a second substrate 115 serving as a support for fixing the semiconductor film is attached with an adhesive 116.
- a substrate having higher rigidity than the first substrate 101 be used for the second substrate 115.
- a glass substrate, a quartz substrate, a metal substrate, a ceramic substrate, or a plastic substrate can be used as the second substrate 115 as appropriate.
- the adhesive 116 an adhesive made of an organic material may be used. At this time, a flattening layer may be formed on a part of the adhesive.
- a water-soluble resin 116a is applied to an adhesive made of an organic material, and a member 116b (hereinafter, referred to as a member) having both surfaces covered with a reactive peeling-type adhesive is applied thereon.
- the TFTs 104 and the diodes (110 to 112) and the second substrate 115 may be bonded by bonding a double-sided sheet. By using this bonding method, the subsequent peeling step can be performed with a relatively small force.
- the organic adhesive include various release adhesives such as a reactive release adhesive, a heat release adhesive, a light release adhesive such as an ultraviolet release adhesive, and an anaerobic release adhesive.
- the first substrate 101 and the metal film 102 formed thereon are referred to as an exfoliated body 150.
- a layer from the insulating film 103 to the wiring 113 connected to the second electrode of the diode and the wiring “I I4 connected to the external terminal” is referred to as a stacked body 151.
- the physical force is a relatively small force such as a human hand, a load using a member having a sharp end such as a wedge, a wind pressure of a gas blown from a nozzle, or ultrasonic waves.
- Metal oxide film 100, interface between insulating film 103 and metal oxide film 10Q or metal Peeling occurs at the interface between the oxide film 100 and the metal film 102, and the peeled body 150 and the laminated body 151 can be peeled off with a relatively small force.
- the laminate 1501 can be separated from the release body 150.
- the third substrate 117 and the insulating film 103 are bonded to each other with an adhesive 118.
- a plastic substrate or a member formed of an organic resin is used as the third substrate 117.
- Plastic substrates include PET (polyethylene terephthalate), PEN (polyethylene naphthalate), PES (polyether sulfide), polypropylene, polypropylene sulfide, polycarbonate, polyesterimide, polyphenylene sulfide, polyphenylene oxide, and polysulfone. Or a plastic substrate made of polyphthalamide.
- the adhesion between the second substrate 115 and the layer 151 to be peeled off with the adhesive 115 made of an organic material and the laminate 151 including the insulating film 103 are more effective than the adhesive 115. It is important that the material of the third substrate 11 has higher adhesion to the substrate 117.
- Examples of the adhesive 118 include various curable adhesives such as a reactive curable adhesive, a thermosetting adhesive, a photocurable adhesive such as an ultraviolet curable adhesive, and an anaerobic curable adhesive.
- curable adhesives such as a reactive curable adhesive, a thermosetting adhesive, a photocurable adhesive such as an ultraviolet curable adhesive, and an anaerobic curable adhesive.
- release paper that is, a sheet having a release surface on one or both sides of a base material such as a separator
- the release paper may be provided so that the adhesive does not adhere to other members. If the release paper is peeled off, it can be bonded to any member, so that a substrate is not required and the semiconductor device can be made thinner.
- the adhesive material 116 and the second substrate 115 are laminated from the laminate 1501. Peel off.
- the adhesive material 1 16 made of an organic material is subjected to a thermal reaction, a light reaction, a reaction due to humidity, or a chemical reaction (for example, the adhesive strength is reduced by using water, oxygen, etc.) to form an adhesive material 1 made of an organic material 1
- the substrate 16 and the second substrate 115 are peeled off from the multilayer body 151.
- a TFT comprising a polysilicon film and an element comprising an amorphous silicon film, in this embodiment a semiconductor device having a diode, are formed on a plastic substrate 117. can do.
- FIG. 11A is a top view of a semiconductor device formed according to the present embodiment which is divided by laser cutting or dicing using laser light.
- wirings 113, 114, 1101, and the wirings are electrically connected to the wirings formed on the printed wiring board.
- Connection wires 1102 to 1104 for connection are formed.
- FIG. 11 (B) is a cross-sectional view taken along (a)-(a) ′ of FIG. 11 (A) when the semiconductor device is mounted on a printed wiring board 110.
- a TFT whose active area is made of a polysilicon film and a diode whose active area is made of an amorphous silicon film are formed.
- Wirings 113, 114, and 111 (not shown)
- the connection wires 1102, 1103, and 1104 (not shown) connected to the semiconductor device are provided from the front end of the semiconductor device to the rear surface via the side surface.
- connection wires 1102 to 1104 are conductive films containing elements such as gold, copper, nickel, platinum, and silver, and are formed by a known technique such as an evaporation method or plating. It can be formed by using.
- connection wirings 1102 to 1104 are connected to the wirings (1107, 1108) provided on the printed circuit board via the outer wires 1105, 1106 and mounted.
- a bump formed of metal gold, silver, solder, or the like
- a bump formed of a conductive resin, or the like can be used for the external terminals 1105 and 1106, a bump formed of metal (gold, silver, solder, or the like), a bump formed of a conductive resin, or the like can be used.
- FIGS. 11 (C) and 11 (D) show a different mounting method from FIGS. 11 (A) and 11 (B). Note that the same parts as those in FIGS. 1, 11A and 11B are denoted by the same reference numerals.
- FIG. 11C is a top view of a semiconductor device formed according to the present embodiment, which is divided by dicing.
- the surface of the semiconductor device 1100 manufactured according to the present embodiment (this is the same as FIG. 1A), and the power lines 113, 114, and 1101 are formed.
- Connection wirings 1112-1114 for electrically connecting to the wiring formed thereon are formed.
- FIG. 11D is a sectional view taken along (port) 1 (port) ′ in FIG. 11 (G) when the semiconductor device is mounted on a printed wiring board 1110.
- a TFT whose active region is made of a polysilicon film and a diode whose active region is made of an amorphous silicon film are formed, and connection wirings 1112 to 1114 connected to the wirings 113, 114, and 1101, respectively, are formed.
- etching holes 1117 and 1118 penetrating the semiconductor device are formed by a known method such as trench etching and the like, and conductive lines 1112 to 111.4 are formed by the conductive materials 1112 to 111.4 through the holes.
- the conductive material 1 1 1 2 to 1 1 1 4 and the external terminal 1 1 1 1 5 and 1 1 1 6 are respectively the conductive material 1 102 to 1 104 and the external terminal 1 105 of FIG. It can be formed using the same material as in 110.
- the semiconductor device manufactured in this embodiment can function as an optical sensor or a photoelectric conversion element. Light incident on a diode is absorbed by a photoelectric conversion layer to form a photoelectric charge, and this photoelectric charge is generated. Amplify and detect by TFT.
- a Schottky diode having a photoelectric conversion layer interposed between an anode electrode and a force source electrode is used as the diode.
- the photoelectric conversion element for converting light into an electric signal is not limited to the diode having the above configuration, and a PIN type, PN type diode, an avalanche diode, or the like can also be used.
- the PIN photodiode is composed of a p-type semiconductor layer, an n-type semiconductor layer, and a ⁇ -type (intrinsic) semiconductor layer sandwiched between the p-type semiconductor layer and the n-type semiconductor layer. .
- a photoelectric conversion element one having a photoelectric conversion layer or the like composed of an organic material, specifically, a transparent negative electrode, and an organic pigment (perylene pigment: Me—PTC) vacuum-deposited thereon, A gold electrode or the like formed thereon may be used.
- an organic material specifically, a transparent negative electrode, and an organic pigment (perylene pigment: Me—PTC) vacuum-deposited thereon, A gold electrode or the like formed thereon may be used.
- a TFT having amorphous silicon in an active region can be used as a photoelectric conversion element.
- the semiconductor device manufactured according to this embodiment mode can use a lightweight and thin substrate, the volume can be smaller than that of a conventional semiconductor device. As a result, electronic devices using these semiconductor devices can be reduced in size and weight.
- the third substrate 117 is a plastic substrate, typically In addition to this, it can also be attached to organic resin in a package in which an IC chip or the like is sealed. In this case, the area of the component occupying the printed wiring board can be reduced. That is, the area of the printed wiring board can be reduced.
- a metal film 202, an insulating film 203, and a TFT 204 are sequentially formed on a first substrate 201.
- an amorphous metal oxide film 200 is formed between the metal film 202 and the insulating film 203 by 2 nm.
- the TFT 204 includes a polysilicon film having a source region, a drain region, and a channel formation region, a gate insulating film covering the polysilicon film, a gate electrode formed on the channel formation region of the polysilicon film, and an interlayer insulating film. And a source electrode and a drain electrode connected to the source region and the drain region.
- the interlayer insulating film 217 is formed of a plurality of insulating films for insulating the source electrode, the drain electrode, and the gate electrode.
- a second substrate 207 is bonded onto the TFT 204 and the interlayer insulating film 217 thereof using an adhesive 208 made of an organic resin.
- the pressure-sensitive adhesive 208 made of an organic resin the same as the pressure-sensitive adhesive 111 of Embodiment 1 can be used.
- a water-soluble resin 208a is applied as an adhesive made of an organic material, and both surfaces are reactively peeled thereon.
- a member 208b (hereinafter, referred to as a double-sided sheet) covered with the mold adhesive is adhered, and a second substrate 207 is further adhered thereon.
- the second substrate 207 a substrate similar to the second substrate 115 of Embodiment 1 can be used as appropriate.
- the first substrate 201 and the metal film 202 are a separated body 250, and the insulating member 203 and the TFT 204 are a stacked body 251.
- the peeled body 250 and the laminated body 251 are peeled off by physical means.
- the insulating film 203 and the metal oxide film 200 At the interface with the metal oxide film 200 and the metal layer 202, and the ⁇ lj separator 250 and the laminate 251 can be peeled off with a relatively small force.
- the third substrate 210 and the insulating film 203 are bonded to each other with an adhesive 209.
- the third substrate 210 and the adhesive 209 may be the same as those used as the third substrate 117 and the adhesive 118 in the first embodiment.
- an adhesive may be provided on the insulating film 103 in the same manner as in Embodiment 1 instead of the above steps.
- release paper release paper, that is, a sheet having a release surface on one or both sides of a substrate such as a separator
- the release paper may be provided so that the adhesive does not adhere to other members. If the release paper is peeled off, it can be bonded to any member, so that a substrate is not required and the semiconductor device can be made thinner.
- the double-sided sheet 208b is peeled off. Note that the double-sided sheet 208b and the second substrate 207 may be simultaneously peeled off from the water-soluble resin 208a.
- the water-soluble resin 208a is dissolved and removed using water.
- the remaining surface may cause a defect. Therefore, it is preferable that the surfaces of the source electrode 213 and the drain electrode 214 be cleaned by a cleaning treatment or an o 2 plasma treatment.
- a photoelectric conversion element 211 is formed over the source electrode 213, and a wiring 212 connected to the output terminal is formed over the drain electrode 214.
- a photoelectric conversion element 211 composed of a diode is formed as in the first embodiment.
- a method for producing the diode a known method may be used.
- the photoelectric conversion element 211 has a photoelectric conversion layer or the like made of an organic material, specifically, a transparent ITO electrode and an organic pigment vacuum-deposited thereon (perylene pigment: Me—PTC). ) And a gold electrode or the like formed thereon.
- a TFT having a polysilicon film in an active region and an element having an amorphous silicon film in an active region in this embodiment, a semiconductor device having a photoelectric conversion element can be formed over a plastic substrate.
- the semiconductor device formed in the present embodiment can be mounted on a printed wiring board by applying the mounting method described in the first embodiment.
- the optical sensor according to the present embodiment is a non-power storage type. It is an optical sensor.
- a TFT 304 is formed on a glass substrate (first substrate 300).
- a metal film 301 in this case, a tungsten film (80 nm in thickness) is formed on a glass substrate by a sputtering method, and an insulating film 302, here, a silicon oxide film (160 nm in thickness), which is not exposed to the air, is laminated.
- an amorphous tungsten oxide film 308 is formed between the tungsten film 301 and the silicon oxide film 301 at a force of about 2 to 5 nm.
- a silicon oxynitride film 303 (film thickness 100 nm) serving as a base insulating film is formed by a PCVD method, and an ⁇ amorphous silicon film (film thickness 54 nm) which is not exposed to the air is further laminated.
- a polysilicon film having a desired shape is formed using a known technique (solid phase growth method, laser crystallization method, crystallization method using a catalyst metal, etc.), patterning is performed to form a polysilicon film having a desired shape.
- a region is formed, and a TFT 304 is formed using the region as an active region.
- formation of a gate insulating film, formation of a gate electrode, formation of a source or drain region by doping an active region, formation of an interlayer insulating film, formation of a source or drain electrode, activation treatment, and the like are performed.
- a P-type channel type TFT is formed as the TFT.
- a first substrate 300 and a tungsten film 301 formed thereon are formed. Is called exfoliated body 350.
- the layers from the silicon oxide film 302 to the TFT 304 are referred to as a laminate 351.
- an adhesive 305 that is soluble in water or alcohols is applied to the entire surface and baked.
- the composition of the adhesive may be, for example, epoxy, acrylate, silicon, or the like.
- a film (thickness: 30 m) 305 composed of a water-soluble resin (manufactured by Toa Gosei: VL-WSH L10) is applied by spin coating, and is temporarily cured and finally cured.
- the step of curing the water-soluble resin may be divided into two steps, that is, provisional curing and main curing, and the curing may be performed at once.
- a treatment for partially reducing the adhesion between the tungsten film 301 and the silicon oxide film 302 is performed.
- the treatment for partially reducing the adhesion is a treatment for partially irradiating the tungsten film 301 or the silicon oxide film 302 with laser light along the periphery of the region to be peeled, or a region for peeling.
- a hard needle may be pressed vertically with a diamond pen or the like and moved with a load.
- a scriber device is used, the pressing amount is set to 0.1 mm to 2 mm, and the pressing may be performed by applying pressure.
- the pressing amount is set to 0.1 mm to 2 mm, and the pressing may be performed by applying pressure.
- This step may be performed before applying the adhesive 305 soluble in water or alcohols to the entire surface.
- the second substrate is applied to an adhesive 305 made of a water-soluble resin.
- a third substrate (not shown) is attached to the first substrate 300 using a double-sided sheet.
- the third substrate prevents the first substrate 300 from being damaged in a later peeling step.
- a substrate having higher rigidity than the first substrate 300 for example, a quartz substrate or the like is preferably used.
- the double-sided sheet is a member having an ultraviolet-peelable pressure-sensitive adhesive on both sides.
- the first substrate 300 provided with the tungsten film 301 is peeled off by physical means from the region where the adhesion is partially reduced.
- peeling occurs in the tungsten oxide film 308, and can be peeled off by a relatively small force (for example, human hand, wind pressure of gas blown from a nozzle, ultrasonic waves, or the like).
- a relatively small force for example, human hand, wind pressure of gas blown from a nozzle, ultrasonic waves, or the like.
- the tungsten oxide remains on the surface of the silicon oxide film 302, the tungsten oxide is removed by dry etching or the like. Note that the tungsten oxide film need not be removed.
- the fourth substrate 312 and the layer to be peeled 351 including the silicon oxide film 302 are bonded to each other with an adhesive 311.
- the state after bonding is shown in FIG. 3 (B).
- the adhesive 311 the oxide film 302 (and the layer to be peeled 315) and the fourth substrate 312 are better than the adhesiveness between the second substrate 307 and the layer to be peeled off by the double-sided sheet 306. It is important that the adhesion is higher.
- a polyethylene terephthalate substrate (PET substrate) is used as the fourth substrate 312.
- an ultraviolet-curable adhesive is used.
- the double-sided sheet 306 is peeled off from the adhesive 305 soluble in water or alcohols.
- the adhesive 305 soluble in water or alcohols is dissolved using water and removed. The state at this time is shown in FIG. Now there remains soluble adhesive in water or alcohols, it will cause defective, the source electrode 31 3 of the TFT, the surface of the drain electrode 31 4, cleaning in the cleaning process and 0 2 plasma treatment It is preferable to have a smooth surface.
- the gate electrode of the TFT is formed via an interlayer insulating film.
- a wiring 343 connected to the first electrode 3 15 is formed. It is preferable that the wiring 343 connected to the gate electrode covers a polysilicon region which is an active region of the TFT and also has a function as a light shielding film.
- the wiring 341 connected to the source electrode 313 is connected to the power supply line (406 in FIG. 4), and the wiring 342 connected to the drain electrode is connected to the second resistor (404 in FIG. 4) and the output terminal (FIG. 4). 4 at 408).
- the anode electrode 344 is connected to a wiring 343 connected to the gate electrode of the TFT and a first resistor (403 in FIG. 4), and is formed of a thin film containing Ni in this embodiment.
- a silicon film 345 having P, I, and N conductive layers is formed on the anode electrode 344 by a plasma CVD method.
- the P-type and N-type conductive layers are microcrystalline layers to increase the electrical conductivity
- the I-type conductive layer is an amorphous layer
- the thickness of the silicon thin film to be laminated is 800 nm.
- a P layer, an I layer, and an N layer are formed in this order from the layer in contact with the anode electrode, and a force source electrode 346 is formed on the N layer.
- ITO is used for the force source electrode 346.
- the power source electrode 346 is connected to the power source electrode 346 via the interlayer insulating film, and the power supply line (40 in FIG. The wiring 347 connected to 6) is formed.
- the wiring 341 connected to the source electrode of the TFT is connected to the power supply line (406 in FIG. 4), and the wiring 342 connected to the drain electrode is connected to the second resistor (404 in FIG. 4).
- the wiring connected to the output terminal (408 in FIG. 4) are exposed on the surface of the interlayer insulating film.
- ALF anisotropic conductive film
- FPC flexible printed circuit
- TAB tape automated bonding tape or tape carrier package
- FIG. 8 is a top view and a sectional view of a module of an electronic device to which the present embodiment is applied.
- FIG. 8A shows an external view of the module on which the panel 800 is mounted.
- the panel 800 includes a pixel portion 803, a scan line driver circuit 804 for selecting a pixel included in the pixel portion 803, and a signal line driver circuit 805 for supplying a video signal to the selected pixel.
- an optical sensor 810 provided on a print substrate 806 via a controller 801, a power supply circuit 802, and an FPC 809 is provided.
- Various signals and power supply voltages output from the controller 801 or the power supply circuit 802 are provided as follows. It is supplied to the pixel portion 803 of the panel 800, the scanning line driving circuit 804, and the signal line driving circuit 805 via the FPC 807.
- a power supply voltage and various signals to the printed circuit board 806 are supplied via an interface (I / F) unit 808 in which a plurality of input terminals are arranged.
- FIG. 8 (B) is a cross-sectional view of ( ⁇ ) — ( ⁇ ′) in FIG. 8 (A).
- the optical sensor 810 is printed. It can be installed on a package such as an IC chip 811 or a CPU installed on the substrate 806, and it is possible to increase the light receiving area of the optical sensor and reduce the area of the printed wiring board. .
- FIG. 3 a circuit diagram of a non-storage type optical sensor formed according to this embodiment is shown in FIG.
- the diode power source electrode 346 is connected to the power supply line 406, and the anode electrode 344 is connected to the first resistor 403 and the gate electrode 407 of the TFT 402.
- the source electrode of the TFT is connected to the power supply line 406, and the drain electrode is connected to the output terminal 408 and the second resistor 404.
- the voltage is applied to the gate electrode 407 of the electromotive force FT402 generated in the diode 401.
- the current flowing through the TFT 402 and the second resistor 404 is converted from a resistance value to a voltage, and detected by a voltage difference between the output terminal 408 and the ground potential.
- the anode electrode 344 of the diode connected to the TFT 402 is made of Ni, and the force source electrode 346 is made of ITO.
- the anode electrode 344 may be a light-transmitting conductive film, and the force electrode 346 may be a metal electrode. In this case, if light enters the TFT, the light affects the TFT. Therefore, it is preferable to form a light-shielding film below the silicon film.
- an anisotropic conductive film is used to connect the optical sensor to the printed wiring board, but the present invention is not limited to this. It is also possible to connect using a conductive paste such as solder.
- the optical sensor formed according to this embodiment includes a diode in which the active region is formed of an amorphous silicon film and a TFT amplifying element in which the active region is formed of a polysilicon film. Therefore, even if the area of the photoelectric conversion layer (light receiving layer) is small, that is, even if it is small, it is possible to detect weak light. Also, since it is formed on a plastic substrate, it can be lighter and thinner than conventional ones. In addition, if an anisotropic conductive film is used to connect to the printed circuit board wiring, it can be installed on an IC chip mounted on the printed circuit board wiring, or on a package such as a CPU, thus increasing the light receiving area of the optical sensor. At the same time, the area of the printed wiring board can be reduced.
- an example of manufacturing an optical sensor including a TFT having a polysilicon film in an active region and a diode having an amorphous silicon film in an active region using the process of Embodiment 2 is shown in FIG.
- the optical sensor of this embodiment is a storage type optical sensor, and by using a plurality of 1 bits, which are one pixel of the optical sensor, it is possible to read a radiation image such as a facsimile, a scanner, and an X-ray. A high-performance and large-area photoelectric conversion device can be manufactured.
- a metal film 901 and an insulating film 902 are formed on a glass substrate (first substrate 900) as in the first embodiment.
- a tungsten film film thickness 10 nm to 200 nm, preferably 50 nm to 75 nm
- the insulating film 902 here silicon oxide film (fl (150 nm to 200 nm thick).
- a silicon oxynitride film 903 (thickness 100 nm) to be a base insulating film is formed by a PCVD method, and an amorphous silicon film (thickness 54 nm) which is not exposed to the air is further deposited. Form a layer.
- an amorphous tungsten oxide film 915 is formed between the tungsten film 901 and the silicon oxide film 902 at a thickness of about 2 nm to 5 nm.
- Amorphous silicon film contains hydrogen, so if a polysilicon film is formed by heating, heat treatment at 500 ° C or higher to crystallize will cause hydrogen diffusion while forming the polysilicon film. Can be.
- a TFT can be formed using the obtained polysilicon film. At this time, the tungsten oxide film 915 in an amorphous state is also crystallized.
- a polysilicon film is formed by using a known technique (a solid-phase growth method, a laser monocrystallization method, a crystallization method using a catalyst metal, or the like).
- the polysilicon film is buttered to form a silicon region having a desired shape, and a TFT 904 having the silicon region as an active region is manufactured.
- formation of a gate insulating film, formation of a gate electrode, formation of a source or drain region by doping an active region, formation of an interlayer insulating film, formation of a source or drain electrode, activation treatment, and the like are performed.
- a P-channel TFT is formed as the TFT.
- a wiring 907 connected to the source electrode 905 of the TFT 904 is formed. Note that a wiring 907 connected to the source electrode 905 is an anode electrode of the diode.
- a silicon semiconductor film 909 having P, I, and N conductive films is formed on the anode electrode 907 by a plasma CVD method.
- the silicon semiconductor film having the P, I, and N conductive layers can be manufactured by the same steps as in the first embodiment.
- a force source electrode 914 is formed on the silicon semiconductor film.
- ITO is used for the force source electrode.
- the wiring 910 connected to the force source electrode via the interlayer insulating film and the TFT drain The wiring 908 connected to the ground electrode 906 is formed.
- the wiring 910 is connected to the power supply line (1002 in FIG. 10A), and the wiring 908 is connected to the signal wiring (100A in FIG. 10A).
- a glass substrate 900 and a metal film 901 formed thereon are referred to as a peeled body 950.
- a layer from the oxide film 902 to the wiring 910 connected to the diode and the power source electrode of the diode is referred to as a stacked body 951.
- an adhesive 911 which is soluble in water or alcohols is applied to the entire surface of the laminate and fired.
- the composition of the pressure-sensitive adhesive 911 soluble in water or alcohols may be, for example, any of epoxy-based, acrylate-based, and silicone-based adhesives.
- a film (thickness: 30 m) made of a water-soluble resin (Toa Gosei: VL-WSH L10) is applied by spin coating, and is temporarily cured and then fully cured.
- the step of curing the water-soluble resin may be divided into two stages, that is, temporary curing and main curing, and may be performed at one time.
- a treatment for partially reducing the adhesion between the metal film 901 and the oxide film 902 is performed in order to facilitate subsequent peeling. This step may be the same as in the first embodiment.
- a holding substrate 913 is attached to an adhesive 911 which is soluble in water or alcohols.
- the glass substrate 900 on which the metal film 901 was provided was peeled off from the side where the adhesion was partially reduced. Is peeled off by physical means.
- separation occurs in the tungsten oxide film 915. Note that when a tungsten oxide film remains on the surface of the oxide film 902, it is preferable to remove the tantalum oxide film by dry etching or the like. Thus, the layer 951 to be separated including the oxide film 902 can be separated from the glass substrate 900.
- the plastic substrate 922 and the layer to be peeled 951 including the oxide film 902 are bonded with an adhesive 921.
- the adhesive 921 the adhesion between the oxide film 902 (and the layer 951 to be peeled) and the plastic substrate 922 is better than the adhesiveness between the holding substrate 913 and the layer to be peeled 951 by the double-sided sheet 912. It is important that sex is higher.
- plastic substrate 922 a polycarbonate substrate (PC substrate) is used.
- adhesive 921 an ultraviolet curable adhesive is used.
- the double-sided sheet 912 is peeled off from the adhesive 911 which is soluble in water or alcohols.
- the adhesive 911 soluble in water or alcohols is dissolved and removed using water.
- the adhesive may cause a defect. Therefore, the surface of the wiring 910 connected to the cathode electrode 914 of the diode and the wiring 908 connected to the drain electrode of the thin film transistor are removed. it is preferable that the clean surface in the cleaning treatment or O 2 plasma treatment.
- anisotropic conductive film (ACF: Anisotropic Conductive Film) or flexible printed circuit (FPC: Flexible Printed Circuit), TAB (Tape Automated Bonding) tape or TCP (Tape Carrier Package)
- ACF Anisotropic Conductive Film
- FPC Flexible Printed Circuit
- TAB Tape Automated Bonding
- TCP Tape Carrier Package
- FIG. 10A shows a 1-bit equivalent circuit, which is one pixel of the storage-type optical sensor formed by this embodiment.
- the anode electrode 907 is connected to the power line 1002. It is composed of a diode 1001 connected and having a force source electrode 914 connected to the source electrode of the TFT 1003, and a TFT 1003 for transferring the photocharge accumulated in the diode by a transfer switch function by a control signal of the gate electrode.
- the drain electrode of the TFT is connected to the signal wiring 1004, and the charge generated by the diode is transferred to the capacitance (not shown) on the signal wiring through the TFT, and read by a readout circuit (not shown) connected to the signal wiring. Is read.
- FIG. 10B shows an equivalent circuit when the 1-bit equivalent circuit shown in FIG. 10A is arranged in 3 ⁇ 3. The driving method will be described with reference to FIG.
- the gate signal line g1 of the shift register SR1 is activated to turn on the charge transfer transistor " ⁇ 1-T13" of the pixel in the first column, and the photocharges of the diodes SS11-SS13 are transferred to the signal lines S1-S3.
- the control signals of the transfer switches M1 to M3 of the shift register SR2 are sequentially activated, and the photocharges of the SS11 to SS13 amplified by the buffer amplifier (Amp) are read out in chronological order at Vout.
- the procedure of activating the gate signal line g2 of the shift register SR1 is repeated to read out the photoelectric charge of each pixel, that is, the diode.
- the anode electrode 907 of the diode connected to the TFT is Ni, and the cathode electrode 914 is ITO.
- the anode electrode 907 may be a light-transmitting conductive film, and the force source electrode 914 may be a metal electrode. In this case, when light enters the TFT, the TFT affects the TFT. Therefore, it is preferable to form a light shielding film below the silicon film.
- a photoelectric conversion device including a plurality of optical sensors can be formed over a plastic substrate. That is, it is possible to manufacture a photoelectric conversion device including a plurality of optical sensors including a TFT whose active region has polysilicon in the active region and a diode having an active region amorphous silicon in the active region.
- the photoelectric conversion device formed according to this embodiment has a plurality of photosensors each including a diode formed of an amorphous silicon film and a TFT amplifying element formed of a polysilicon film. Even if the area of the light receiving layer) is small, that is, even if it is small, it can detect weak light and has high sensitivity. Also, since it is formed on a plastic substrate, it can be lighter and thinner than conventional ones. In addition, if an anisotropic conductive film is used to connect to a drive circuit such as a shift register or a power supply line, the IC chip mounted on the printed circuit board, the drive circuit, the package that constitutes the power supply circuit, etc. It is possible to increase the light receiving area of the photoelectric conversion device and reduce the area of the printed wiring board.
- a drive circuit such as a shift register or a power supply line
- FIG. 5 is a top view of the card type computer
- FIG. 5 (B) is a top view of a module of the card type computer formed on a plastic substrate. Note that this embodiment , A plastic substrate provided with a keypad 503 by a known method is used. As shown in FIG.
- a solar cell 501 is used as a power source
- an EL display device is used for a display unit 502 which is a part of an output unit
- a driving circuit 504 of the display unit and a keyboard which is a part of an input unit.
- a computer having a pad 503, a central integrated circuit 505 (CPU), a memory 506, and a power supply circuit 507 connected to a solar cell and a manufacturing method thereof will be described.
- FIG. 6 shows a block diagram of an IC card, in this embodiment, a card type computer.
- Reference numeral 601 denotes a central processing unit (hereinafter, referred to as a CPU)
- 602 denotes a control unit
- 603 denotes an operation unit
- 604 denotes memory
- 605 denotes an input unit
- 605 denotes an output unit
- 607 denotes a power supply unit.
- the combination of the arithmetic unit 603 and the control unit 602 is the CPU 601.
- the arithmetic unit 603 performs arithmetic operations such as addition and subtraction and logical operations such as AND, OR, and NOT. , ALU), various registers for temporarily storing operation data and results, and a counter for counting the number of input 1s.
- Circuits constituting the arithmetic unit 603, for example, an AND circuit, an OR circuit, a NOT circuit, a buffer circuit, or a register circuit can be constituted by TFTs.
- a continuous oscillation type A semiconductor film crystallized using the above laser beam may be formed as an active region of the TF.
- a method of obtaining a polysilicon film by irradiating a continuous oscillation type laser beam to the amorphous silicon film may be used, or a method of heating the amorphous silicon film to obtain a polysilicon film, and then obtaining a polysilicon film.
- a method of obtaining a polysilicon film by irradiating a laser beam may be used.
- a continuous wave laser beam may be used after adding a metal element serving as a catalyst to an amorphous silicon film, heating to obtain a polysilicon film. May be used to obtain a polysilicon film.
- the direction of the channel length of the TFT constituting the calculation unit 603 and the scanning direction of the laser beam are aligned.
- the control unit 602 executes a command stored in the memory 604 and controls the entire operation.
- the control unit 602 includes a program counter, an instruction register, and a control signal generation unit.
- the control unit 602 can also be constituted by a TFT, and a polysilicon film crystallized using one continuous wave laser beam may be formed as an active region of the TFT.
- the direction of the channel length of the FT constituting the control unit 602 and the scanning direction of one laser beam are aligned.
- the memory 604 is a place for storing data and instructions for performing calculations, and stores data and programs frequently executed by the CPU.
- the memory 604 includes a main memory, an address register, and a data register. Further, a cache memory may be used in addition to the main memory. These memories may be formed of SRAM, DRAM, flash memory, or the like.
- a polysilicon film crystallized using a continuous wave laser beam can be formed as an active region of the TFT. In this embodiment, the channel length direction of the TFT constituting the memory 604 and the scanning direction of the laser beam are aligned.
- the input unit 605 is a device that takes in data and programs from the outside.
- the output unit 606 is a device for displaying the result, typically a display device.
- the power supply unit 607 is a device that supplies power necessary for processing the CPU and the like.
- the power supply unit includes a solar cell. It is to be noted that a secondary battery for storing electric power formed by a solar cell may be provided.
- EL display electoluminescent display
- the power supply circuit and the capacitor can be manufactured by TFT. Also in this case, a polysilicon film crystallized by using a continuous wave laser beam can be manufactured as an active region of the TFT. In the present embodiment, the channel length direction of the TFT constituting the power supply unit and the scanning direction of one laser beam are aligned.
- the channel length direction of the TFT By aligning the channel length direction of the TFT with the scanning direction of the laser beam, a CPU with less variation can be built on an insulating substrate. In addition, the CPU, output unit, memory, and power supply unit that complicate circuit design and manufacturing processes can be built on the same substrate. Also in the display unit, it is preferable that the channel length direction of the plurality of TFTs arranged in each pixel is aligned with the scanning direction of the laser beam.
- FIG. 7 shows an example in which a card-type computer module formed on a glass substrate is transferred onto a plastic substrate on which a keyboard pad is formed.
- FIG. 7 is a cross-sectional view of (L)-(L) ′ in FIG. 5 (B).
- a silicon oxide layer 703 is formed on a glass substrate 701 via a tungsten film 702.
- an amorphous tungsten oxide film 712 is formed between the tungsten film 702 and the silicon oxide film 703 at a thickness of about 2 nm to 5 nm.
- an amorphous silicon film is formed on the silicon oxide film.
- a crystalline silicon film is formed by a known method, and this film is used for an active region such as a TFT in the pixel area 751, a TF in the pixel driving circuit 752, a TFT in the CPU 753, and a capacitive element in the memory 755. .
- the n-channel TFTs 705, 707, 709, p-channel TFTs 704, 706, 708, and the capacity ⁇ ! 5710, 711, terminal portions (not shown) and the like are formed.
- CMOS circuit By combining the n-channel TFT 707 and the p-channel TFT 706, and the n-channel TFT 709 and the p-channel TFT 708, respectively, a CMOS circuit can be formed, and various integrated circuits such as a CPU and a drive circuit can be configured. can do.
- a method for forming an active region of a CPU, a driving circuit, or the like it is preferable to use a method using a continuous wave laser beam as described in this embodiment.
- a solar cell 721 connected to the drain electrode of a TFT (not shown) of the power supply circuit is formed in the power supply unit 754.
- a diode whose active region is formed of amorphous silicon 723 is formed over the conductive film 722 connected to the TFT of the power supply circuit.
- a capacitor 711 connected to the solar cell is formed below the solar cell. This is to temporarily store the electric energy generated by the solar cell, and by providing this, the electric energy is not lost during use and can be used even in a dark place.
- the pixel 724 connected to the drain electrode of the switching TFT 704 in the pixel area is formed.
- an EL display device is used as a display device.
- a known display device such as a liquid crystal display device can also be used.
- an adhesive 731 (a removable adhesive, for example, a water-soluble adhesive, or a double-sided sheet).
- a mechanical force is applied between the metal film 702 and the oxide film 703 to separate the glass substrate 701 and the tungsten film 702 from the silicon oxide film 703.
- separation occurs in the tungsten oxide film 7 12.
- the tungsten oxide may be removed by dry etching or the like.
- the keyboard pad is put on the surface of the silicon oxide film 703 via the adhesive 733.
- the plastic substrate 734 on which is formed is fixed.
- an integrated circuit (IC) including a TFT having crystalline silicon in the active region and a diode having amorphous silicon in the active region is completed on the plastic substrate 734.
- an IC card such as a card type computer having an integrated circuit (IC) including a power supply unit 754 formed of a solar cell, a pixel area 751, a pixel driving circuit 752, a CPU 753, a memory 755, and the like on a plastic substrate. Can be formed.
- the electronic device such as an IC card manufactured according to this embodiment is thin and light because it is formed on a plastic substrate. Further, since the power supply unit, the input unit, the central processing unit, the output unit, and the like are formed on the same substrate, the throughput can be improved without the step of bonding a plurality of panels.
Description
Claims
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EP03780931A EP1583148A4 (en) | 2003-01-08 | 2003-12-19 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME |
AU2003289448A AU2003289448A1 (en) | 2003-01-08 | 2003-12-19 | Semiconductor device and its fabricating method |
JP2004539104A JP4693413B2 (ja) | 2003-01-08 | 2003-12-19 | 半導体装置の作製方法 |
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JP (4) | JP4693413B2 (ja) |
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CN (1) | CN100392861C (ja) |
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- 2003-12-19 JP JP2004539104A patent/JP4693413B2/ja not_active Expired - Fee Related
- 2003-12-19 EP EP10009803.7A patent/EP2256807A3/en not_active Withdrawn
- 2003-12-19 KR KR1020057012724A patent/KR101026644B1/ko active IP Right Grant
- 2003-12-19 EP EP03780931A patent/EP1583148A4/en not_active Withdrawn
- 2003-12-19 CN CNB2003801085331A patent/CN100392861C/zh not_active Expired - Fee Related
- 2003-12-19 WO PCT/JP2003/016355 patent/WO2004068582A1/ja active Application Filing
- 2003-12-29 TW TW092137331A patent/TWI338362B/zh not_active IP Right Cessation
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2004
- 2004-01-02 US US10/749,552 patent/US7449718B2/en not_active Expired - Fee Related
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2006
- 2006-09-20 US US11/523,642 patent/US7501306B2/en not_active Expired - Fee Related
-
2009
- 2009-02-12 US US12/369,802 patent/US7919779B2/en not_active Expired - Fee Related
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2010
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2013
- 2013-07-31 JP JP2013159341A patent/JP5736422B2/ja not_active Expired - Fee Related
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2015
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KR101406768B1 (ko) | 2007-03-20 | 2014-06-12 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치의 제작 방법 |
JP2008294414A (ja) * | 2007-04-27 | 2008-12-04 | Semiconductor Energy Lab Co Ltd | 半導体装置及びその作製方法 |
WO2010035544A1 (ja) * | 2008-09-29 | 2010-04-01 | シャープ株式会社 | フォトダイオードおよびその製造方法ならびにフォトダイオードを備えた表示装置 |
WO2011108156A1 (ja) * | 2010-03-02 | 2011-09-09 | コニカミノルタエムジー株式会社 | 放射線検出パネル、放射線画像検出器、放射線検出パネルの製造方法および放射線画像検出器の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN100392861C (zh) | 2008-06-04 |
AU2003289448A1 (en) | 2004-08-23 |
US20090212285A1 (en) | 2009-08-27 |
KR101026644B1 (ko) | 2011-04-04 |
JPWO2004068582A1 (ja) | 2006-05-25 |
EP2256807A2 (en) | 2010-12-01 |
EP2256807A3 (en) | 2017-05-17 |
US20070015302A1 (en) | 2007-01-18 |
JP2014003307A (ja) | 2014-01-09 |
US7449718B2 (en) | 2008-11-11 |
JP2015144300A (ja) | 2015-08-06 |
JP2011109116A (ja) | 2011-06-02 |
CN1735968A (zh) | 2006-02-15 |
TWI338362B (en) | 2011-03-01 |
EP1583148A4 (en) | 2007-06-27 |
JP5352572B2 (ja) | 2013-11-27 |
US20050056842A1 (en) | 2005-03-17 |
US7919779B2 (en) | 2011-04-05 |
EP1583148A1 (en) | 2005-10-05 |
US7501306B2 (en) | 2009-03-10 |
JP6242831B2 (ja) | 2017-12-06 |
KR20050094428A (ko) | 2005-09-27 |
TW200503256A (en) | 2005-01-16 |
JP5736422B2 (ja) | 2015-06-17 |
JP4693413B2 (ja) | 2011-06-01 |
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