WO2004064146A1 - Procede de realisation d'une structure contrainte destinee a etre dissociee - Google Patents
Procede de realisation d'une structure contrainte destinee a etre dissociee Download PDFInfo
- Publication number
- WO2004064146A1 WO2004064146A1 PCT/FR2003/003622 FR0303622W WO2004064146A1 WO 2004064146 A1 WO2004064146 A1 WO 2004064146A1 FR 0303622 W FR0303622 W FR 0303622W WO 2004064146 A1 WO2004064146 A1 WO 2004064146A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- assembled
- producing
- complex structure
- structure according
- substrates
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
Definitions
- the invention relates to a method for producing a complex microelectronic structure by assembling two elementary microelectronic structures, this complex structure being intended to be dissociated.
- this complex structure being intended to be dissociated.
- the notion of microelectronic structure should be considered as also covering optoelectronic, microtechnological, or nanotechnological or even nanoelectronic structures.
- FR 2 681 472 and its various improvements (incorporated by reference). It includes in particular the following stages: creation by ion implantation of a weakened area buried within the source substrate delimiting within this substrate the thin layer to be transferred, - assembly of the source substrate with the target substrate at the free surface of the thin layer,
- a problem can arise when it is desired to use a heat treatment to induce all or part of the fracture in the weakened zone and the source and target substrates have materials with very different coefficients of thermal expansion. This is the case, for example, if one wishes to transfer a silicon film onto a molten silica substrate.
- the heat treatment can induce within the structure formed by the assembly of the two substrates, because of the difference in thermal expansion coefficients, significant internal stresses which can be damaging for the structure. These stresses can also be damaging at the time of the actual fracture, since, at this time, the structures, by suddenly dissociating, immediately relax. There is therefore, at this time, a sudden jump in stresses at the level of each structure, that formed of the thin transferred layer integral with the target substrate and that formed by the rest of the source substrate. This jump, if too large, can damage at least one of these two structures.
- the problem is to control the stresses within a heterostructure (complex structure which can be formed by assembling at least two different materials) at the time of dissociation of this heterostructure when this dissociation requires a change in temperature.
- the invention proposes a method for producing a complex structure by assembling two substrates by two respective connecting faces, this structure being intended to be dissociated at the level of a separation zone, which is characterized by the fact that, before assembly, a difference in tangential stress state is created between the two faces to be assembled, this difference being chosen so as to obtain within the assembled structure a predetermined stress state at the time of dissociation .
- the difference in tangential stress state between the two faces to be assembled is chosen so as to minimize the stresses at the level of the separation zone at the time of dissociation.
- the invention recommends voluntarily generating stresses in the assembled structure to allow it to compensate for the stresses which will be generated subsequently during the rise in temperature necessary for the dissociation of the structure.
- the method of the invention does not have these limitations.
- the stress state generated within the complex structure depends on the stresses generated independently before assembly, in each substrate. These constraints, see below, are precisely adjustable. The process is therefore reproducible and precisely adjustable, which makes it possible to control (or master) the constraints according to future needs.
- the bonding forces between the substrates to be assembled are no longer limited since the complex structure does not have, in the context of the invention, to come off during assembly. In the rest of the document, the substrates to be assembled are also called elementary structures as opposed to the complex structure formed by the assembly of these two substrates.
- the difference in tangential stresses between the faces to be bonded of the two elementary structures can advantageously be created by deforming (mainly in an elastic manner) each of said structures before assembly.
- deforming mainly in an elastic manner
- a simple and easy technique to implement to generate constraints is to bend these structures.
- the two elementary structures will be curved so that the two faces to be assembled are respectively concave and convex. They can also be complementary, for example concave spherical and convex spherical, respectively.
- Bending elementary structures to generate stresses can, for example, be implemented by applying localized mechanical forces and / or distributed over the structures to be deformed.
- a pressure difference can be created between the two faces of the structure to be bent.
- suction of said structure on a concave preform of suitable profile chosen as a function of that to be given to the face to be assembled and on which the structure rests locally on its periphery.
- seals may be made for seals to improve the seal between the structure and the preform. Mention may also be made of the suction of said structure inside a cavity (without preform), the structure resting locally at its periphery on a joint bordering this cavity.
- the curved elementary structure can be obtained by deformation of this structure between two complementary preforms, one concave, the other convex, of profiles chosen according to that to be given to the face to be assembled.
- it can be provided on the preform which receives the elementary structure of the suction channels to maintain the curved structure, once the other preform has been removed.
- This other preform can advantageously be the other elementary structure to be assembled already curved according to the desired profile.
- Another alternative consists in applying the mechanical forces simultaneously on the two structures to be assembled, for example by deformation of the two structures between two preforms of profiles chosen according to those to be given to the faces to be assembled.
- the application of mechanical forces to at least one of the substrates is carried out using a preform consisting of a mold, this preform consists of a porous mold, the application of mechanical forces on the substrates is carried out using at least one deformable preform.
- the assembly between the two structures is a molecular bonding making it possible to achieve significant adhesion forces and a good quality interface.
- said faces are treated in order to facilitate subsequent bonding.
- These treatments may consist, for example, of mechanical and / or chemical polishing, chemical treatment, UV ozone treatment, RIE (reactive ion etching), plasma, hydrogen annealing, etc.
- the assembly between the substrates is carried out by direct contact, the surface of at least one of the substrates being arranged so as to avoid air trapping between the surfaces assembled, at least one of the substrates is drilled, this substrate is drilled in its center, - at least one of the substrates comprises at least one non-through channel opening out at the edge of the substrate, the assembly between the substrates is carried out by means of a creep layer, the assembly is carried out at a temperature above ambient, - the substrates are heated by contact with heated preforms, the preforms are respectively heated to different temperatures.
- the invention also relates to a method for transferring a thin layer from a source substrate to a target substrate, comprising the following steps:
- this process being characterized by the fact that, before assembly, a difference in tangential stress state is created between the two faces to be assembled, this difference being chosen so as to obtain within the assembled structure a predetermined stress state at the time of dissociation.
- this difference in tangential stress state between the two faces to be assembled is chosen so as to minimize the stresses at the level of the buried layer at the time of dissociation. This makes it possible to guarantee the quality of the structures obtained after dissociation.
- the difference in state of tangential stresses between the two faces to be assembled is imposed by bending, before assembly, each of the two substrates to be assembled.
- FIG. 1 is a graph illustrating the evolution of the stresses with the temperature at the surfaces of the substrate of fused silica within a conventional heterostructure (silica + silicon),
- FIG. 2 is a similar graph illustrating the constraints on the surfaces of the silicon substrate of this heterostructure
- FIG. 3 is a diagram of a heterostructure obtained by the method of the invention
- FIGS. 7, 8 and 9 illustrate variants of stressing the elementary structures to be assembled
- FIGS. 10A and 10B show a top view of two exemplary embodiments of one of the structures to be assembled in order to avoid trapping of air bubbles
- FIG. 11 is a schematic sectional view of a couple of two deformable preforms.
- a film composed of a silicon layer of approximately 0.4 ⁇ m and an oxide layer of approximately 0.4 ⁇ m from a source substrate of surface oxidized silicon 200 mm in diameter and 750 ⁇ m thick, on a target substrate of fused silica 200 mm in diameter and 1200 ⁇ m thick.
- this film can be transferred according to the following process:
- a weakened zone which delimits the thin layer to be transferred under implantation conditions known to those skilled in the art, for example implantation of hydrogen at a dose about 6.10 16 H + / cm 2 under an energy of 75 keV),
- FIGS. 1 and 2 respectively illustrate the stresses obtained by calculation which are generated respectively at the surface of the fused silica and silicon substrates during the heat treatment in the conventional complex structure formed from the assembly of these two substrates. At room temperature, the two substrates are relaxed, there is no internal stress within the complex structure.
- curve 1 in FIG. 1 illustrates the evolution of these constraints on the assembled face of the molten silica substrate, curve 2 on its free face
- curve 3 of FIG. 2 illustrates the evolution of these constraints in voltage on the assembled face of the silicon substrate, curve 4 on its free face.
- This relaxation corresponds to a jump of about 100 MPa at the level of the fracture zone for the silicon substrate, of 160 MPa for the assembled face of the fused silica.
- the complex structure sees its stress level change with temperature as illustrated in FIG. 4 respectively for the assembled face (curve 7) of the fused silica and its free face (curve 8) and FIG. 5 respectively for the assembled face (curve 9) silicon and its free face (curve 10).
- the internal stresses at the level of the fracture zone having been minimized at the fracture temperature these stresses no longer intervene in the fracture mechanism. This may have only a negligible influence on the thermal budget (temperature-duration couple) necessary for the fracture and in this case, we will keep the same thermal budget.
- constraints of external origin traction, torsion, ...) generalized or localized.
- Figure 6 illustrates an example process.
- a first elementary structure 11 is deformed by suction on a first preform 12 of specific shape, for example concave spherical.
- the suction is carried out by means of suction channels 15 opening onto the surface of the preform.
- Joints 16 located at the periphery of the preform can support the first structure 11 and make it possible to ensure a pressure difference between the two faces of this structure.
- the latter under the effect of this pressure difference deforms to match the shape of the first preform 12. Due to the deformation, constraints known and quantifiable by those skilled in the art arise within the first structure 11 and in particular on its free face (upper).
- a second structure 13 is then placed opposite the free face of the first structure 11.
- a second preform 14, of suitable shape and advantageously complementary to the shape of the first preform 12, for example spherical convex, is provided to ensure the deformation elastic of the second structure 13 between the second preform 14 and the first structure 11.
- the arrow shown in FIG. 6 symbolizes the application of the forces intended to carry out the actual deformation.
- the second structure 13 gradually deforms in contact with the first structure 11 until it matches its shape.
- the two faces to be assembled having been conditioned here, for example before the two structures are stressed, in a manner known to those skilled in the art, in order to allow bonding by molecular adhesion, this bonding is carried out when the two faces are look coincide.
- the preforms 12 and 14 can for example be rigid molds, porous molds or even deformable membranes ...
- a variant of the process consists, as illustrated in FIG. 7, in replacing the first preform 12 by a hollow device 17 provided with a central cavity 18 The first structure 11 then rests on this device in its periphery by means of tight seals 19.
- Suction channels 20 make it possible to create a depression in the cavity.
- the pressure difference which applies between the two faces of the first structure 11 it is thus possible to deform this first structure 11 according to a determined curvature.
- a vacuum in the cavity of about 0.25 bar the other face of the structure being subjected to atmospheric pressure, we obtain 3 mm of arrow on a 200 mm standard diameter silicon wafer of thickness 750 microns with a 195mm diameter seal.
- the first structure 1 can then be assembled with the second structure 3 as explained above.
- FIG. 8 Another variant is illustrated in FIG. 8. It consists in deforming the second structure 13 between two adapted preforms of complementary shapes, one concave 22 and the other convex 21.
- the convex preform is provided with channels suction 24 to allow the second structure 13 to be maintained in its position after the deformation and withdrawal of the concave preform 22.
- the second structure 13 can then be assembled with the first structure 11 itself already deformed (for example according to the figure 7), by bonding using an adhesive for example.
- Another variant consists in assembling without constraint at room temperature the two elementary structures to be assembled by molecular bonding. This assembled structure is then deformed between two complementary molds. It is then ensured that each of the structures is integral with one of the molds (by suction for example), then by any means known to a person skilled in the art, a separation of the assembled structure is caused at the molecular bonding zone. Two constrained elementary structures are then obtained which can then be assembled according to the invention.
- This variant has the advantage of preserving the surface condition at the level of the faces to be assembled, thus making it possible for example to assemble the two elementary structures constrained by a new molecular bonding.
- the assembly of the two elementary structures can therefore be a bonding by molecular adhesion or a bonding by means of an adhesive or even a sealing layer. It is also possible to provide for using an adhesion layer between the preform and the structure to be deformed or else to use electrostatic or magnetic forces to keep the preform and the curved elementary structure in contact.
- FIG. 9 consists in facing the two structures 11 and 13 without them being glued and in stamping them simultaneously between two concave 25 and convex preforms 26 respectively of complementary shapes. The arrows in FIG. 9 illustrate the pressure forces to be applied to ensure the deformation. The two structures then deform together, an air film remaining interposed between the two structures. Once the desired curvature has been reached, the air film is evacuated due to the forces applied, bonding by molecular adhesion is then carried out.
- an air bubble may be trapped between the two structures and hinder bonding by molecular adhesion.
- An alternative consists in providing on one or both structures one or more evacuation channels 28 on the face to be assembled, opening at the edge of the plate as illustrated in FIG. 10B.
- These channels can, for example, have dimensions of the order of 100 ⁇ m in width and 5 ⁇ m in depth and be produced by the usual techniques of lithography and engraving.
- Suction means may be associated with these channels 28 or with the bore 27 to facilitate the evacuation of the trapped air.
- Another alternative can consist in carrying out the deformation and the assembly under a partial vacuum in order to minimize the volume of trapped air.
- This method has the disadvantage of requiring all the more deep voids to ensure the deformation of the structures.
- a last alternative may consist in placing spacers in a radial position at the periphery of the plate, which will be removed once the central zone has been bonded. More generally, we can use any method that allows initiate bonding between the two structures at their centers and then propagate it towards the edges. For this, for example, a slight difference in curvature can be introduced before bonding between the two structures.
- a constrained complex structure is obtained, the constraints of which are known at all points, by imposing a difference in tangential stresses between the faces of the two structures to be assembled.
- stresses within this structure evolve but this, in a determined way and known to those skilled in the art.
- This evolution is a function, among other things, of the types and thicknesses of the different materials constituting each of the two initial structures and of the difference in stresses present at the bonding interface.
- the methods described above allow dissociation under controlled constraints of a heterostructure formed of substrates of different materials.
- These substrates can be more or less thick, simple or composite (formed by a stack of different layers of more or less thin materials) processed or not.
- the materials concerned are all the semiconductors such as in particular silicon, germanium, their alloys (S ' Hx Ge x ), indium phosphide (InP), gallium arsenic (GaAs), lithium niobate, silicon carbide (SiC), gallium nitride (GaN), sapphire, superconductors such as, for example, compounds of the YbaCuO, NbN, or BiSrCaCuO type, all insulators such as, in particular, fused silica, quartz, glasses of different compositions, gO, all metals such as in particular tungsten, copper or aluminum.
- the preforms can be heated to allow temperature bonding of the deformed intermediate structures.
- the preforms may not be at the same temperature so that the two intermediate structures have a temperature difference at the time of assembly.
- the fact of bonding the intermediate structures in temperature also makes it possible to control the internal stresses of the complex structure in addition to the control already enabled by the controlled deformation of the intermediate structures. It is then, for example, possible to cancel internal stresses of a complex structure at a given temperature by limiting the deformation of the intermediate structures.
- the two intermediate structures consisting of a silicon plate 750 ⁇ m thick and 200 mm in diameter and a molten silica plate of 1200 ⁇ m thick and 200 mm in diameter.
- These two intermediate structures deformed to approximately 1, 4 m before bonding give a complex structure where the internal stresses are canceled in approximately 300 ° C if the bonding took place at 20 ° C.
- the two intermediate structures are bonded at 100 ° C, the internal stresses of the complex structure will cancel out at 380 ° C, therefore at a higher temperature without having to deform the intermediate structures more significantly.
- a layer which flows at a certain temperature, Tf can be placed between the two intermediate structures.
- Tf a certain temperature
- the preforms can be molds, for example porous molds.
- FIG. 11 shows by way of example an enclosure 30 containing two preforms 31 and 32 each comprising a deformable membrane 31 A or 32A. At the surface of these membranes open suction channels 33 and 34, here shown schematically as being tangential. The suction or pressurization circuits are shown diagrammatically by simple double lines.
- the suction channels make it possible to maintain the deformed elementary structures; the surface of the suction channels can be limited by subjecting the free face of the intermediate structure to a pressure higher than atmospheric pressure (for example 2 bar inside the enclosure). Furthermore, if this deformable preform is deformed by a pressure difference, a greater deformation can be achieved by increasing the pressure on the free face of the elementary structure.
- the preform 31 is at an internal pressure of 1.5 bar while the channels 33 are at a pressure of 0.3 bar; the preform 32 is at an internal pressure of 2.5 bar while the channels 34 are at a pressure of 0.3 bar.
- the pressure of the enclosure (2 bar) is intermediate between the pressures of the preforms 31 and 32.
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004566101A JP4943656B2 (ja) | 2002-12-09 | 2003-12-08 | 分離されるよう構成された応力下での構造体の製造方法 |
US10/538,482 US20060205179A1 (en) | 2002-12-09 | 2003-12-08 | Method for making a stressed structure designed to be dissociated |
DE60305067T DE60305067T2 (de) | 2002-12-09 | 2003-12-08 | Verfahren zur herstellung einer für dissoziation ausgelegten belasteten struktur |
EP03815088A EP1570516B1 (fr) | 2002-12-09 | 2003-12-08 | Procede de realisation d'une structure contrainte destinee a etre dissociee |
US12/628,772 US8389379B2 (en) | 2002-12-09 | 2009-12-01 | Method for making a stressed structure designed to be dissociated |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR02/15550 | 2002-12-09 | ||
FR0215550A FR2848336B1 (fr) | 2002-12-09 | 2002-12-09 | Procede de realisation d'une structure contrainte destinee a etre dissociee |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10538482 A-371-Of-International | 2003-12-08 | ||
US12/628,772 Division US8389379B2 (en) | 2002-12-09 | 2009-12-01 | Method for making a stressed structure designed to be dissociated |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2004064146A1 true WO2004064146A1 (fr) | 2004-07-29 |
Family
ID=32320122
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/FR2003/003622 WO2004064146A1 (fr) | 2002-12-09 | 2003-12-08 | Procede de realisation d'une structure contrainte destinee a etre dissociee |
Country Status (7)
Country | Link |
---|---|
US (2) | US20060205179A1 (fr) |
EP (1) | EP1570516B1 (fr) |
JP (1) | JP4943656B2 (fr) |
AT (1) | ATE325429T1 (fr) |
DE (1) | DE60305067T2 (fr) |
FR (1) | FR2848336B1 (fr) |
WO (1) | WO2004064146A1 (fr) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8048766B2 (en) | 2003-06-24 | 2011-11-01 | Commissariat A L'energie Atomique | Integrated circuit on high performance chip |
US8252663B2 (en) | 2009-06-18 | 2012-08-28 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method of transferring a thin layer onto a target substrate having a coefficient of thermal expansion different from that of the thin layer |
US8389379B2 (en) | 2002-12-09 | 2013-03-05 | Commissariat A L'energie Atomique | Method for making a stressed structure designed to be dissociated |
US8470712B2 (en) | 1997-12-30 | 2013-06-25 | Commissariat A L'energie Atomique | Process for the transfer of a thin film comprising an inclusion creation step |
US8664084B2 (en) | 2005-09-28 | 2014-03-04 | Commissariat A L'energie Atomique | Method for making a thin-film element |
US8778775B2 (en) | 2006-12-19 | 2014-07-15 | Commissariat A L'energie Atomique | Method for preparing thin GaN layers by implantation and recycling of a starting substrate |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2748851B1 (fr) | 1996-05-15 | 1998-08-07 | Commissariat Energie Atomique | Procede de realisation d'une couche mince de materiau semiconducteur |
FR2848337B1 (fr) * | 2002-12-09 | 2005-09-09 | Commissariat Energie Atomique | Procede de realisation d'une structure complexe par assemblage de structures contraintes |
FR2861497B1 (fr) | 2003-10-28 | 2006-02-10 | Soitec Silicon On Insulator | Procede de transfert catastrophique d'une couche fine apres co-implantation |
EP1894234B1 (fr) * | 2005-02-28 | 2021-11-03 | Silicon Genesis Corporation | Procédé de rigidification du substrat et système pour un transfert de couche. |
WO2010057068A2 (fr) * | 2008-11-16 | 2010-05-20 | Suss Microtec, Inc. | Procédé et appareil de liaison de plaquette à connexion de plaquette améliorée |
JP5549344B2 (ja) * | 2010-03-18 | 2014-07-16 | 株式会社ニコン | 基板接合装置、基板ホルダ、基板接合方法、デバイス製造方法および位置合わせ装置 |
FR2962594B1 (fr) * | 2010-07-07 | 2012-08-31 | Soitec Silicon On Insulator | Procede de collage par adhesion moleculaire avec compensation de desalignement radial |
FR2972078A1 (fr) * | 2011-02-24 | 2012-08-31 | Soitec Silicon On Insulator | Appareil et procédé de collage par adhésion moléculaire |
FR2972848A1 (fr) * | 2011-03-18 | 2012-09-21 | Soitec Silicon On Insulator | Appareil et procédé de collage par adhésion moléculaire avec minimisation de déformations locales |
FR2985370A1 (fr) | 2011-12-29 | 2013-07-05 | Commissariat Energie Atomique | Procede de fabrication d'une structure multicouche sur un support |
US8916450B2 (en) * | 2012-08-02 | 2014-12-23 | International Business Machines Corporation | Method for improving quality of spalled material layers |
CN106548972B (zh) * | 2015-09-18 | 2019-02-26 | 胡兵 | 一种将半导体衬底主体与其上功能层进行分离的方法 |
FR3077923B1 (fr) * | 2018-02-12 | 2021-07-16 | Soitec Silicon On Insulator | Procede de fabrication d'une structure de type semi-conducteur sur isolant par transfert de couche |
KR102648711B1 (ko) | 2018-09-20 | 2024-03-20 | 삼성전자주식회사 | 기판 본딩 장치 및 그를 이용한 기판 본딩 방법 |
US11414782B2 (en) | 2019-01-13 | 2022-08-16 | Bing Hu | Method of separating a film from a main body of a crystalline object |
US20240047414A1 (en) * | 2019-11-08 | 2024-02-08 | Ev Group E. Thallner Gmbh | Device and method for joining substrates |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4254590A (en) * | 1978-11-13 | 1981-03-10 | Bbc Brown Boveri & Company Limited | Method for the production of a disk-shaped silicon semiconductor component with negative beveling |
JPS644013A (en) * | 1987-06-26 | 1989-01-09 | Sony Corp | Formation of substrate |
EP0410679A1 (fr) * | 1989-07-25 | 1991-01-30 | Shin-Etsu Handotai Company Limited | Méthode pour préparer un substrat pour fabriquer des éléments semi-conducteurs |
US5400548A (en) * | 1992-07-23 | 1995-03-28 | Wacker-Chemitronic Gesellschaft Fur Elektronik-Grundstoffe Mbh | Process for manufacturing semiconductor wafers having deformation ground in a defined way |
WO2000048238A1 (fr) * | 1999-02-10 | 2000-08-17 | Commissariat A L'energie Atomique | Structure multicouche a contraintes internes controlees et procede de realisation d'une telle structure |
EP1050901A2 (fr) * | 1999-04-30 | 2000-11-08 | Canon Kabushiki Kaisha | Procédé de séparation d'un elément composé et procédé pour la fabrication d'un film mince |
Family Cites Families (218)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3915757A (en) | 1972-08-09 | 1975-10-28 | Niels N Engel | Ion plating method and product therefrom |
US3913520A (en) | 1972-08-14 | 1975-10-21 | Precision Thin Film Corp | High vacuum deposition apparatus |
US3993909A (en) | 1973-03-16 | 1976-11-23 | U.S. Philips Corporation | Substrate holder for etching thin films |
FR2245779B1 (fr) * | 1973-09-28 | 1978-02-10 | Cit Alcatel | |
US3901423A (en) | 1973-11-26 | 1975-08-26 | Purdue Research Foundation | Method for fracturing crystalline materials |
US4170662A (en) | 1974-11-05 | 1979-10-09 | Eastman Kodak Company | Plasma plating |
US4121334A (en) | 1974-12-17 | 1978-10-24 | P. R. Mallory & Co. Inc. | Application of field-assisted bonding to the mass production of silicon type pressure transducers |
US3957107A (en) * | 1975-02-27 | 1976-05-18 | The United States Of America As Represented By The Secretary Of The Air Force | Thermal switch |
US4039416A (en) | 1975-04-21 | 1977-08-02 | White Gerald W | Gasless ion plating |
GB1542299A (en) * | 1976-03-23 | 1979-03-14 | Warner Lambert Co | Blade shields |
US4028149A (en) * | 1976-06-30 | 1977-06-07 | Ibm Corporation | Process for forming monocrystalline silicon carbide on silicon substrates |
US4074139A (en) * | 1976-12-27 | 1978-02-14 | Rca Corporation | Apparatus and method for maskless ion implantation |
US4108751A (en) | 1977-06-06 | 1978-08-22 | King William J | Ion beam implantation-sputtering |
US4179324A (en) | 1977-11-28 | 1979-12-18 | Spire Corporation | Process for fabricating thin film and glass sheet laminate |
JPS55104057A (en) * | 1979-02-02 | 1980-08-09 | Hitachi Ltd | Ion implantation device |
US4324631A (en) * | 1979-07-23 | 1982-04-13 | Spin Physics, Inc. | Magnetron sputtering of magnetic materials |
CH640886A5 (de) | 1979-08-02 | 1984-01-31 | Balzers Hochvakuum | Verfahren zum aufbringen harter verschleissfester ueberzuege auf unterlagen. |
US4244348A (en) * | 1979-09-10 | 1981-01-13 | Atlantic Richfield Company | Process for cleaving crystalline materials |
FR2506344B2 (fr) * | 1980-02-01 | 1986-07-11 | Commissariat Energie Atomique | Procede de dopage de semi-conducteurs |
FR2475068B1 (fr) * | 1980-02-01 | 1986-05-16 | Commissariat Energie Atomique | Procede de dopage de semi-conducteurs |
US4342631A (en) | 1980-06-16 | 1982-08-03 | Illinois Tool Works Inc. | Gasless ion plating process and apparatus |
US4471003A (en) | 1980-11-25 | 1984-09-11 | Cann Gordon L | Magnetoplasmadynamic apparatus and process for the separation and deposition of materials |
FR2501727A1 (fr) | 1981-03-13 | 1982-09-17 | Vide Traitement | Procede de traitements thermochimiques de metaux par bombardement ionique |
US4361600A (en) | 1981-11-12 | 1982-11-30 | General Electric Company | Method of making integrated circuits |
US4412868A (en) | 1981-12-23 | 1983-11-01 | General Electric Company | Method of making integrated circuits utilizing ion implantation and selective epitaxial growth |
US4486247A (en) | 1982-06-21 | 1984-12-04 | Westinghouse Electric Corp. | Wear resistant steel articles with carbon, oxygen and nitrogen implanted in the surface thereof |
FR2529383A1 (fr) * | 1982-06-24 | 1983-12-30 | Commissariat Energie Atomique | Porte-cible a balayage mecanique utilisable notamment pour l'implantation d'ioris |
FR2537768A1 (fr) | 1982-12-08 | 1984-06-15 | Commissariat Energie Atomique | Procede et dispositif d'obtention de faisceaux de particules de densite spatialement modulee, application a la gravure et a l'implantation ioniques |
FR2537777A1 (fr) * | 1982-12-10 | 1984-06-15 | Commissariat Energie Atomique | Procede et dispositif d'implantation de particules dans un solide |
US4500563A (en) * | 1982-12-15 | 1985-02-19 | Pacific Western Systems, Inc. | Independently variably controlled pulsed R.F. plasma chemical vapor processing |
DE3246480A1 (de) | 1982-12-15 | 1984-06-20 | Wacker-Chemitronic Gesellschaft für Elektronik-Grundstoffe mbH, 8263 Burghausen | Verfahren zur herstellung von halbleiterscheiben mit getternder scheibenrueckseite |
US4468309A (en) | 1983-04-22 | 1984-08-28 | White Engineering Corporation | Method for resisting galling |
GB2144343A (en) * | 1983-08-02 | 1985-03-06 | Standard Telephones Cables Ltd | Optical fibre manufacture |
US4567505A (en) * | 1983-10-27 | 1986-01-28 | The Board Of Trustees Of The Leland Stanford Junior University | Heat sink and method of attaching heat sink to a semiconductor integrated circuit and the like |
JPS6088535U (ja) | 1983-11-24 | 1985-06-18 | 住友電気工業株式会社 | 半導体ウエハ |
FR2558263B1 (fr) | 1984-01-12 | 1986-04-25 | Commissariat Energie Atomique | Accelerometre directif et son procede de fabrication par microlithographie |
GB2155024A (en) | 1984-03-03 | 1985-09-18 | Standard Telephones Cables Ltd | Surface treatment of plastics materials |
FR2563377B1 (fr) | 1984-04-19 | 1987-01-23 | Commissariat Energie Atomique | Procede de fabrication d'une couche isolante enterree dans un substrat semi-conducteur, par implantation ionique |
US4542863A (en) | 1984-07-23 | 1985-09-24 | Larson Edwin L | Pipe-thread sealing tape reel with tape retarding element |
US4566403A (en) * | 1985-01-30 | 1986-01-28 | Sovonics Solar Systems | Apparatus for microwave glow discharge deposition |
US4837172A (en) * | 1986-07-18 | 1989-06-06 | Matsushita Electric Industrial Co., Ltd. | Method for removing impurities existing in semiconductor substrate |
US4717683A (en) * | 1986-09-23 | 1988-01-05 | Motorola Inc. | CMOS process |
US4764394A (en) | 1987-01-20 | 1988-08-16 | Wisconsin Alumni Research Foundation | Method and apparatus for plasma source ion implantation |
EP0284818A1 (fr) * | 1987-04-03 | 1988-10-05 | BBC Brown Boveri AG | Procédé et dispositif pour lier des couches |
JPS63254762A (ja) * | 1987-04-13 | 1988-10-21 | Nissan Motor Co Ltd | Cmos半導体装置 |
US4847792A (en) * | 1987-05-04 | 1989-07-11 | Texas Instruments Incorporated | Process and apparatus for detecting aberrations in production process operations |
SE458398B (sv) | 1987-05-27 | 1989-03-20 | H Biverot | Ljusdetekterande och ljusriktningsbestaemmande anordning |
FR2616590B1 (fr) | 1987-06-15 | 1990-03-02 | Commissariat Energie Atomique | Procede de fabrication d'une couche d'isolant enterree dans un substrat semi-conducteur par implantation ionique et structure semi-conductrice comportant cette couche |
US4956698A (en) | 1987-07-29 | 1990-09-11 | The United States Of America As Represented By The Department Of Commerce | Group III-V compound semiconductor device having p-region formed by Be and Group V ions |
US4846928A (en) * | 1987-08-04 | 1989-07-11 | Texas Instruments, Incorporated | Process and apparatus for detecting aberrations in production process operations |
US4887005A (en) | 1987-09-15 | 1989-12-12 | Rough J Kirkwood H | Multiple electrode plasma reactor power distribution system |
US5015353A (en) * | 1987-09-30 | 1991-05-14 | The United States Of America As Represented By The Secretary Of The Navy | Method for producing substoichiometric silicon nitride of preselected proportions |
US5138422A (en) | 1987-10-27 | 1992-08-11 | Nippondenso Co., Ltd. | Semiconductor device which includes multiple isolated semiconductor segments on one chip |
GB8725497D0 (en) | 1987-10-30 | 1987-12-02 | Atomic Energy Authority Uk | Isolation of silicon |
US5200805A (en) * | 1987-12-28 | 1993-04-06 | Hughes Aircraft Company | Silicon carbide:metal carbide alloy semiconductor and method of making the same |
US4904610A (en) * | 1988-01-27 | 1990-02-27 | General Instrument Corporation | Wafer level process for fabricating passivated semiconductor devices |
DE3803424C2 (de) * | 1988-02-05 | 1995-05-18 | Gsf Forschungszentrum Umwelt | Verfahren zur quantitativen, tiefendifferentiellen Analyse fester Proben |
JP2666945B2 (ja) * | 1988-02-08 | 1997-10-22 | 株式会社東芝 | 半導体装置の製造方法 |
US4894709A (en) * | 1988-03-09 | 1990-01-16 | Massachusetts Institute Of Technology | Forced-convection, liquid-cooled, microchannel heat sinks |
US4853250A (en) | 1988-05-11 | 1989-08-01 | Universite De Sherbrooke | Process of depositing particulate material on a substrate |
NL8802028A (nl) | 1988-08-16 | 1990-03-16 | Philips Nv | Werkwijze voor het vervaardigen van een inrichting. |
JP2670623B2 (ja) | 1988-09-19 | 1997-10-29 | アネルバ株式会社 | マイクロ波プラズマ処理装置 |
US4952273A (en) | 1988-09-21 | 1990-08-28 | Microscience, Inc. | Plasma generation in electron cyclotron resonance |
US4996077A (en) * | 1988-10-07 | 1991-02-26 | Texas Instruments Incorporated | Distributed ECR remote plasma processing and apparatus |
US4891329A (en) * | 1988-11-29 | 1990-01-02 | University Of North Carolina | Method of forming a nonsilicon semiconductor on insulator structure |
NL8900388A (nl) | 1989-02-17 | 1990-09-17 | Philips Nv | Werkwijze voor het verbinden van twee voorwerpen. |
JPH02302044A (ja) * | 1989-05-16 | 1990-12-14 | Fujitsu Ltd | 半導体装置の製造方法 |
US4929566A (en) * | 1989-07-06 | 1990-05-29 | Harris Corporation | Method of making dielectrically isolated integrated circuits using oxygen implantation and expitaxial growth |
US4948458A (en) | 1989-08-14 | 1990-08-14 | Lam Research Corporation | Method and apparatus for producing magnetically-coupled planar plasma |
US5036023A (en) * | 1989-08-16 | 1991-07-30 | At&T Bell Laboratories | Rapid thermal processing method of making a semiconductor device |
US5013681A (en) * | 1989-09-29 | 1991-05-07 | The United States Of America As Represented By The Secretary Of The Navy | Method of producing a thin silicon-on-insulator layer |
US5310446A (en) * | 1990-01-10 | 1994-05-10 | Ricoh Company, Ltd. | Method for producing semiconductor film |
JPH0650738B2 (ja) | 1990-01-11 | 1994-06-29 | 株式会社東芝 | 半導体装置及びその製造方法 |
US5034343A (en) * | 1990-03-08 | 1991-07-23 | Harris Corporation | Manufacturing ultra-thin wafer using a handle wafer |
JP2535645B2 (ja) * | 1990-04-20 | 1996-09-18 | 富士通株式会社 | 半導体基板の製造方法 |
US5529108A (en) * | 1990-05-09 | 1996-06-25 | Lanxide Technology Company, Lp | Thin metal matrix composites and production methods |
CN1018844B (zh) * | 1990-06-02 | 1992-10-28 | 中国科学院兰州化学物理研究所 | 防锈干膜润滑剂 |
US5131968A (en) * | 1990-07-31 | 1992-07-21 | Motorola, Inc. | Gradient chuck method for wafer bonding employing a convex pressure |
JPH0719739B2 (ja) | 1990-09-10 | 1995-03-06 | 信越半導体株式会社 | 接合ウェーハの製造方法 |
US5198371A (en) * | 1990-09-24 | 1993-03-30 | Biota Corp. | Method of making silicon material with enhanced surface mobility by hydrogen ion implantation |
US5618739A (en) * | 1990-11-15 | 1997-04-08 | Seiko Instruments Inc. | Method of making light valve device using semiconductive composite substrate |
US5300788A (en) * | 1991-01-18 | 1994-04-05 | Kopin Corporation | Light emitting diode bars and arrays and method of making same |
DE4106288C2 (de) | 1991-02-28 | 2001-05-31 | Bosch Gmbh Robert | Sensor zur Messung von Drücken oder Beschleunigungen |
JP2812405B2 (ja) | 1991-03-15 | 1998-10-22 | 信越半導体株式会社 | 半導体基板の製造方法 |
US5110748A (en) * | 1991-03-28 | 1992-05-05 | Honeywell Inc. | Method for fabricating high mobility thin film transistors as integrated drivers for active matrix display |
US5442205A (en) | 1991-04-24 | 1995-08-15 | At&T Corp. | Semiconductor heterostructure devices with strained semiconductor layers |
US5256581A (en) | 1991-08-28 | 1993-10-26 | Motorola, Inc. | Silicon film with improved thickness control |
FR2681472B1 (fr) * | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
JPH06196377A (ja) * | 1991-11-19 | 1994-07-15 | Sumitomo Metal Mining Co Ltd | 半導体基板の接合方法 |
JP3416163B2 (ja) * | 1992-01-31 | 2003-06-16 | キヤノン株式会社 | 半導体基板及びその作製方法 |
JPH05235312A (ja) * | 1992-02-19 | 1993-09-10 | Fujitsu Ltd | 半導体基板及びその製造方法 |
US5614019A (en) * | 1992-06-08 | 1997-03-25 | Air Products And Chemicals, Inc. | Method for the growth of industrial crystals |
US5234535A (en) | 1992-12-10 | 1993-08-10 | International Business Machines Corporation | Method of producing a thin silicon-on-insulator layer |
WO1994017558A1 (fr) * | 1993-01-29 | 1994-08-04 | The Regents Of The University Of California | Composant monolithique passif |
US5400458A (en) * | 1993-03-31 | 1995-03-28 | Minnesota Mining And Manufacturing Company | Brush segment for industrial brushes |
FR2714524B1 (fr) | 1993-12-23 | 1996-01-26 | Commissariat Energie Atomique | Procede de realisation d'une structure en relief sur un support en materiau semiconducteur |
EP0942161B1 (fr) * | 1993-12-28 | 2003-03-19 | Honda Giken Kogyo Kabushiki Kaisha | Mécanisme d'admission de carburant gazeux et de détermination et d'indication de la quantité de ce carburant pour moteur à combustion à gaz |
DE4400985C1 (de) * | 1994-01-14 | 1995-05-11 | Siemens Ag | Verfahren zur Herstellung einer dreidimensionalen Schaltungsanordnung |
FR2715503B1 (fr) | 1994-01-26 | 1996-04-05 | Commissariat Energie Atomique | Substrat pour composants intégrés comportant une couche mince et son procédé de réalisation. |
FR2715501B1 (fr) | 1994-01-26 | 1996-04-05 | Commissariat Energie Atomique | Procédé de dépôt de lames semiconductrices sur un support. |
FR2715502B1 (fr) | 1994-01-26 | 1996-04-05 | Commissariat Energie Atomique | Structure présentant des cavités et procédé de réalisation d'une telle structure. |
JP3352340B2 (ja) * | 1995-10-06 | 2002-12-03 | キヤノン株式会社 | 半導体基体とその製造方法 |
JP3293736B2 (ja) * | 1996-02-28 | 2002-06-17 | キヤノン株式会社 | 半導体基板の作製方法および貼り合わせ基体 |
US5880010A (en) * | 1994-07-12 | 1999-03-09 | Sun Microsystems, Inc. | Ultrathin electronics |
JPH0851103A (ja) | 1994-08-08 | 1996-02-20 | Fuji Electric Co Ltd | 薄膜の生成方法 |
US5524339A (en) * | 1994-09-19 | 1996-06-11 | Martin Marietta Corporation | Method for protecting gallium arsenide mmic air bridge structures |
FR2725074B1 (fr) | 1994-09-22 | 1996-12-20 | Commissariat Energie Atomique | Procede de fabrication d'une structure comportant une couche mince semi-conductrice sur un substrat |
US5567654A (en) | 1994-09-28 | 1996-10-22 | International Business Machines Corporation | Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging |
JP3743519B2 (ja) * | 1994-10-18 | 2006-02-08 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | シリコン−酸化物薄層の製造方法 |
ATE216802T1 (de) | 1994-12-12 | 2002-05-15 | Advanced Micro Devices Inc | Verfahren zur herstellung vergrabener oxidschichten |
JP3381443B2 (ja) * | 1995-02-02 | 2003-02-24 | ソニー株式会社 | 基体から半導体層を分離する方法、半導体素子の製造方法およびsoi基板の製造方法 |
FR2736934B1 (fr) | 1995-07-21 | 1997-08-22 | Commissariat Energie Atomique | Procede de fabrication d'une structure avec une couche utile maintenue a distance d'un substrat par des butees, et de desolidarisation d'une telle couche |
FR2738671B1 (fr) * | 1995-09-13 | 1997-10-10 | Commissariat Energie Atomique | Procede de fabrication de films minces a materiau semiconducteur |
FR2744285B1 (fr) * | 1996-01-25 | 1998-03-06 | Commissariat Energie Atomique | Procede de transfert d'une couche mince d'un substrat initial sur un substrat final |
FR2747506B1 (fr) | 1996-04-11 | 1998-05-15 | Commissariat Energie Atomique | Procede d'obtention d'un film mince de materiau semiconducteur comprenant notamment des composants electroniques |
FR2748850B1 (fr) | 1996-05-15 | 1998-07-24 | Commissariat Energie Atomique | Procede de realisation d'un film mince de materiau solide et applications de ce procede |
FR2748851B1 (fr) | 1996-05-15 | 1998-08-07 | Commissariat Energie Atomique | Procede de realisation d'une couche mince de materiau semiconducteur |
US5863832A (en) * | 1996-06-28 | 1999-01-26 | Intel Corporation | Capping layer in interconnect system and method for bonding the capping layer onto the interconnect system |
US5897331A (en) * | 1996-11-08 | 1999-04-27 | Midwest Research Institute | High efficiency low cost thin film silicon solar cell design and method for making |
US6127199A (en) * | 1996-11-12 | 2000-10-03 | Seiko Epson Corporation | Manufacturing method of active matrix substrate, active matrix substrate and liquid crystal display device |
SG65697A1 (en) * | 1996-11-15 | 1999-06-22 | Canon Kk | Process for producing semiconductor article |
US6054363A (en) * | 1996-11-15 | 2000-04-25 | Canon Kabushiki Kaisha | Method of manufacturing semiconductor article |
DE19648501A1 (de) * | 1996-11-22 | 1998-05-28 | Max Planck Gesellschaft | Verfahren für die lösbare Verbindung und anschließende Trennung reversibel gebondeter und polierter Scheiben sowie eine Waferstruktur und Wafer |
KR100232886B1 (ko) * | 1996-11-23 | 1999-12-01 | 김영환 | Soi 웨이퍼 제조방법 |
DE19648759A1 (de) | 1996-11-25 | 1998-05-28 | Max Planck Gesellschaft | Verfahren zur Herstellung von Mikrostrukturen sowie Mikrostruktur |
FR2756847B1 (fr) * | 1996-12-09 | 1999-01-08 | Commissariat Energie Atomique | Procede de separation d'au moins deux elements d'une structure en contact entre eux par implantation ionique |
SG67458A1 (en) | 1996-12-18 | 1999-09-21 | Canon Kk | Process for producing semiconductor article |
FR2758907B1 (fr) | 1997-01-27 | 1999-05-07 | Commissariat Energie Atomique | Procede d'obtention d'un film mince, notamment semiconducteur, comportant une zone protegee des ions, et impliquant une etape d'implantation ionique |
JP3114643B2 (ja) | 1997-02-20 | 2000-12-04 | 日本電気株式会社 | 半導体基板の構造および製造方法 |
JPH10275752A (ja) * | 1997-03-28 | 1998-10-13 | Ube Ind Ltd | 張合わせウエハ−及びその製造方法、基板 |
US6013954A (en) * | 1997-03-31 | 2000-01-11 | Nec Corporation | Semiconductor wafer having distortion-free alignment regions |
US6251754B1 (en) * | 1997-05-09 | 2001-06-26 | Denso Corporation | Semiconductor substrate manufacturing method |
US6162705A (en) * | 1997-05-12 | 2000-12-19 | Silicon Genesis Corporation | Controlled cleavage process and resulting device using beta annealing |
US6033974A (en) * | 1997-05-12 | 2000-03-07 | Silicon Genesis Corporation | Method for controlled cleaving process |
US6150239A (en) * | 1997-05-31 | 2000-11-21 | Max Planck Society | Method for the transfer of thin layers monocrystalline material onto a desirable substrate |
US5877070A (en) * | 1997-05-31 | 1999-03-02 | Max-Planck Society | Method for the transfer of thin layers of monocrystalline material to a desirable substrate |
US6054369A (en) | 1997-06-30 | 2000-04-25 | Intersil Corporation | Lifetime control for semiconductor devices |
US6097096A (en) * | 1997-07-11 | 2000-08-01 | Advanced Micro Devices | Metal attachment method and structure for attaching substrates at low temperatures |
US6534380B1 (en) * | 1997-07-18 | 2003-03-18 | Denso Corporation | Semiconductor substrate and method of manufacturing the same |
US6103599A (en) * | 1997-07-25 | 2000-08-15 | Silicon Genesis Corporation | Planarizing technique for multilayered substrates |
US6255731B1 (en) | 1997-07-30 | 2001-07-03 | Canon Kabushiki Kaisha | SOI bonding structure |
FR2767416B1 (fr) | 1997-08-12 | 1999-10-01 | Commissariat Energie Atomique | Procede de fabrication d'un film mince de materiau solide |
FR2767604B1 (fr) | 1997-08-19 | 2000-12-01 | Commissariat Energie Atomique | Procede de traitement pour le collage moleculaire et le decollage de deux structures |
JP3697034B2 (ja) | 1997-08-26 | 2005-09-21 | キヤノン株式会社 | 微小開口を有する突起の製造方法、及びそれらによるプローブまたはマルチプローブ |
US5882987A (en) * | 1997-08-26 | 1999-03-16 | International Business Machines Corporation | Smart-cut process for the production of thin semiconductor material films |
US5981400A (en) | 1997-09-18 | 1999-11-09 | Cornell Research Foundation, Inc. | Compliant universal substrate for epitaxial growth |
US5920764A (en) * | 1997-09-30 | 1999-07-06 | International Business Machines Corporation | Process for restoring rejected wafers in line for reuse as new |
JP2998724B2 (ja) | 1997-11-10 | 2000-01-11 | 日本電気株式会社 | 張り合わせsoi基板の製造方法 |
FR2771852B1 (fr) | 1997-12-02 | 1999-12-31 | Commissariat Energie Atomique | Procede de transfert selectif d'une microstructure, formee sur un substrat initial, vers un substrat final |
JP4173573B2 (ja) * | 1997-12-03 | 2008-10-29 | 株式会社ナノテム | 多孔質砥粒砥石の製造方法 |
FR2773261B1 (fr) * | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
JP3501642B2 (ja) * | 1997-12-26 | 2004-03-02 | キヤノン株式会社 | 基板処理方法 |
US6071795A (en) * | 1998-01-23 | 2000-06-06 | The Regents Of The University Of California | Separation of thin films from transparent substrates by selective optical processing |
FR2774510B1 (fr) | 1998-02-02 | 2001-10-26 | Soitec Silicon On Insulator | Procede de traitement de substrats, notamment semi-conducteurs |
FR2774797B1 (fr) * | 1998-02-11 | 2000-03-10 | Commissariat Energie Atomique | Procede de realisation d'un ensemble a plusieurs tetes magnetiques et ensemble a tetes multiples obtenu par ce procede |
MY118019A (en) | 1998-02-18 | 2004-08-30 | Canon Kk | Composite member, its separation method, and preparation method of semiconductor substrate by utilization thereof |
US6156623A (en) * | 1998-03-03 | 2000-12-05 | Advanced Technology Materials, Inc. | Stress control of thin films by mechanical deformation of wafer substrate |
JPH11307747A (ja) * | 1998-04-17 | 1999-11-05 | Nec Corp | Soi基板およびその製造方法 |
US6057212A (en) * | 1998-05-04 | 2000-05-02 | International Business Machines Corporation | Method for making bonded metal back-plane substrates |
US5909627A (en) * | 1998-05-18 | 1999-06-01 | Philips Electronics North America Corporation | Process for production of thin layers of semiconductor material |
DE19840421C2 (de) * | 1998-06-22 | 2000-05-31 | Fraunhofer Ges Forschung | Verfahren zur Fertigung von dünnen Substratschichten und eine dafür geeignete Substratanordnung |
US6054370A (en) * | 1998-06-30 | 2000-04-25 | Intel Corporation | Method of delaminating a pre-fabricated transistor layer from a substrate for placement on another wafer |
US6118181A (en) | 1998-07-29 | 2000-09-12 | Agilent Technologies, Inc. | System and method for bonding wafers |
US6271101B1 (en) * | 1998-07-29 | 2001-08-07 | Semiconductor Energy Laboratory Co., Ltd. | Process for production of SOI substrate and process for production of semiconductor device |
FR2781925B1 (fr) * | 1998-07-30 | 2001-11-23 | Commissariat Energie Atomique | Transfert selectif d'elements d'un support vers un autre support |
EP0989593A3 (fr) | 1998-09-25 | 2002-01-02 | Canon Kabushiki Kaisha | Dispositif et procédé de séparation de substrat, et procédé de fabrication de susbtrat |
FR2784795B1 (fr) * | 1998-10-16 | 2000-12-01 | Commissariat Energie Atomique | Structure comportant une couche mince de materiau composee de zones conductrices et de zones isolantes et procede de fabrication d'une telle structure |
FR2784800B1 (fr) * | 1998-10-20 | 2000-12-01 | Commissariat Energie Atomique | Procede de realisation de composants passifs et actifs sur un meme substrat isolant |
CA2293040C (fr) | 1998-12-23 | 2006-10-24 | Kohler Co. | Systeme bicombustible pour moteur a combustion interne |
US6346458B1 (en) * | 1998-12-31 | 2002-02-12 | Robert W. Bower | Transposed split of ion cut materials |
JP3532788B2 (ja) | 1999-04-13 | 2004-05-31 | 唯知 須賀 | 半導体装置及びその製造方法 |
WO2000063965A1 (fr) | 1999-04-21 | 2000-10-26 | Silicon Genesis Corporation | Procede de traitement de couche clivee pour la fabrication de substrats |
US6310387B1 (en) | 1999-05-03 | 2001-10-30 | Silicon Wave, Inc. | Integrated circuit inductor with high self-resonance frequency |
US6664169B1 (en) | 1999-06-08 | 2003-12-16 | Canon Kabushiki Kaisha | Process for producing semiconductor member, process for producing solar cell, and anodizing apparatus |
US6362082B1 (en) * | 1999-06-28 | 2002-03-26 | Intel Corporation | Methodology for control of short channel effects in MOS transistors |
FR2796491B1 (fr) | 1999-07-12 | 2001-08-31 | Commissariat Energie Atomique | Procede de decollement de deux elements et dispositif pour sa mise en oeuvre |
US6323108B1 (en) * | 1999-07-27 | 2001-11-27 | The United States Of America As Represented By The Secretary Of The Navy | Fabrication ultra-thin bonded semiconductor layers |
US6287940B1 (en) | 1999-08-02 | 2001-09-11 | Honeywell International Inc. | Dual wafer attachment process |
FR2797347B1 (fr) | 1999-08-04 | 2001-11-23 | Commissariat Energie Atomique | Procede de transfert d'une couche mince comportant une etape de surfragililisation |
US6263941B1 (en) * | 1999-08-10 | 2001-07-24 | Silicon Genesis Corporation | Nozzle for cleaving substrates |
JP2003506883A (ja) | 1999-08-10 | 2003-02-18 | シリコン ジェネシス コーポレイション | 低打ち込みドーズ量を用いて多層基板を製造するための劈開プロセス |
KR100413789B1 (ko) | 1999-11-01 | 2003-12-31 | 삼성전자주식회사 | 고진공 패키징 마이크로자이로스코프 및 그 제조방법 |
DE19958803C1 (de) | 1999-12-07 | 2001-08-30 | Fraunhofer Ges Forschung | Verfahren und Vorrichtung zum Handhaben von Halbleitersubstraten bei der Prozessierung und/oder Bearbeitung |
US6306720B1 (en) | 2000-01-10 | 2001-10-23 | United Microelectronics Corp. | Method for forming capacitor of mixed-mode device |
JP3975634B2 (ja) * | 2000-01-25 | 2007-09-12 | 信越半導体株式会社 | 半導体ウェハの製作法 |
JP2003531492A (ja) * | 2000-04-14 | 2003-10-21 | エス オー イ テク シリコン オン インシュレータ テクノロジース | 特に半導体材料製の基板又はインゴットから少なくとも一枚の薄層を切り出す方法 |
FR2809867B1 (fr) | 2000-05-30 | 2003-10-24 | Commissariat Energie Atomique | Substrat fragilise et procede de fabrication d'un tel substrat |
US6407929B1 (en) * | 2000-06-29 | 2002-06-18 | Intel Corporation | Electronic package having embedded capacitors and method of fabrication therefor |
FR2811807B1 (fr) | 2000-07-12 | 2003-07-04 | Commissariat Energie Atomique | Procede de decoupage d'un bloc de materiau et de formation d'un film mince |
KR100414479B1 (ko) * | 2000-08-09 | 2004-01-07 | 주식회사 코스타트반도체 | 반도체 패키징 공정의 이식성 도전패턴을 갖는 테이프 및그 제조방법 |
US6600173B2 (en) * | 2000-08-30 | 2003-07-29 | Cornell Research Foundation, Inc. | Low temperature semiconductor layering and three-dimensional electronic circuits using the layering |
FR2818010B1 (fr) | 2000-12-08 | 2003-09-05 | Commissariat Energie Atomique | Procede de realisation d'une couche mince impliquant l'introduction d'especes gazeuses |
FR2819099B1 (fr) | 2000-12-28 | 2003-09-26 | Commissariat Energie Atomique | Procede de realisation d'une structure empilee |
FR2823373B1 (fr) * | 2001-04-10 | 2005-02-04 | Soitec Silicon On Insulator | Dispositif de coupe de couche d'un substrat, et procede associe |
FR2823596B1 (fr) * | 2001-04-13 | 2004-08-20 | Commissariat Energie Atomique | Substrat ou structure demontable et procede de realisation |
FR2823599B1 (fr) * | 2001-04-13 | 2004-12-17 | Commissariat Energie Atomique | Substrat demomtable a tenue mecanique controlee et procede de realisation |
US6759282B2 (en) * | 2001-06-12 | 2004-07-06 | International Business Machines Corporation | Method and structure for buried circuits and devices |
FR2830983B1 (fr) | 2001-10-11 | 2004-05-14 | Commissariat Energie Atomique | Procede de fabrication de couches minces contenant des microcomposants |
US6593212B1 (en) * | 2001-10-29 | 2003-07-15 | The United States Of America As Represented By The Secretary Of The Navy | Method for making electro-optical devices using a hydrogenion splitting technique |
US6953735B2 (en) * | 2001-12-28 | 2005-10-11 | Semiconductor Energy Laboratory Co., Ltd. | Method for fabricating a semiconductor device by transferring a layer to a support with curvature |
FR2834820B1 (fr) * | 2002-01-16 | 2005-03-18 | Procede de clivage de couches d'une tranche de materiau | |
US6607969B1 (en) * | 2002-03-18 | 2003-08-19 | The United States Of America As Represented By The Secretary Of The Navy | Method for making pyroelectric, electro-optical and decoupling capacitors using thin film transfer and hydrogen ion splitting techniques |
US6767749B2 (en) * | 2002-04-22 | 2004-07-27 | The United States Of America As Represented By The Secretary Of The Navy | Method for making piezoelectric resonator and surface acoustic wave device using hydrogen implant layer splitting |
EP1560642A4 (fr) * | 2002-10-09 | 2006-05-03 | Univ Illinois | Systemes et composants microfluidiques |
FR2847075B1 (fr) * | 2002-11-07 | 2005-02-18 | Commissariat Energie Atomique | Procede de formation d'une zone fragile dans un substrat par co-implantation |
FR2848336B1 (fr) | 2002-12-09 | 2005-10-28 | Commissariat Energie Atomique | Procede de realisation d'une structure contrainte destinee a etre dissociee |
FR2850487B1 (fr) * | 2002-12-24 | 2005-12-09 | Commissariat Energie Atomique | Procede de realisation de substrats mixtes et structure ainsi obtenue |
FR2856844B1 (fr) | 2003-06-24 | 2006-02-17 | Commissariat Energie Atomique | Circuit integre sur puce de hautes performances |
FR2857953B1 (fr) | 2003-07-21 | 2006-01-13 | Commissariat Energie Atomique | Structure empilee, et procede pour la fabriquer |
FR2861497B1 (fr) | 2003-10-28 | 2006-02-10 | Soitec Silicon On Insulator | Procede de transfert catastrophique d'une couche fine apres co-implantation |
US7772087B2 (en) | 2003-12-19 | 2010-08-10 | Commissariat A L'energie Atomique | Method of catastrophic transfer of a thin film after co-implantation |
FR2889887B1 (fr) | 2005-08-16 | 2007-11-09 | Commissariat Energie Atomique | Procede de report d'une couche mince sur un support |
FR2891281B1 (fr) | 2005-09-28 | 2007-12-28 | Commissariat Energie Atomique | Procede de fabrication d'un element en couches minces. |
FR2899378B1 (fr) | 2006-03-29 | 2008-06-27 | Commissariat Energie Atomique | Procede de detachement d'un film mince par fusion de precipites |
FR2910179B1 (fr) * | 2006-12-19 | 2009-03-13 | Commissariat Energie Atomique | PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART |
FR2922359B1 (fr) | 2007-10-12 | 2009-12-18 | Commissariat Energie Atomique | Procede de fabrication d'une structure micro-electronique impliquant un collage moleculaire |
FR2925221B1 (fr) * | 2007-12-17 | 2010-02-19 | Commissariat Energie Atomique | Procede de transfert d'une couche mince |
FR2947098A1 (fr) | 2009-06-18 | 2010-12-24 | Commissariat Energie Atomique | Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince |
-
2002
- 2002-12-09 FR FR0215550A patent/FR2848336B1/fr not_active Expired - Lifetime
-
2003
- 2003-12-08 US US10/538,482 patent/US20060205179A1/en not_active Abandoned
- 2003-12-08 JP JP2004566101A patent/JP4943656B2/ja not_active Expired - Lifetime
- 2003-12-08 WO PCT/FR2003/003622 patent/WO2004064146A1/fr active IP Right Grant
- 2003-12-08 DE DE60305067T patent/DE60305067T2/de not_active Expired - Lifetime
- 2003-12-08 AT AT03815088T patent/ATE325429T1/de not_active IP Right Cessation
- 2003-12-08 EP EP03815088A patent/EP1570516B1/fr not_active Expired - Lifetime
-
2009
- 2009-12-01 US US12/628,772 patent/US8389379B2/en not_active Expired - Lifetime
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4254590A (en) * | 1978-11-13 | 1981-03-10 | Bbc Brown Boveri & Company Limited | Method for the production of a disk-shaped silicon semiconductor component with negative beveling |
JPS644013A (en) * | 1987-06-26 | 1989-01-09 | Sony Corp | Formation of substrate |
EP0410679A1 (fr) * | 1989-07-25 | 1991-01-30 | Shin-Etsu Handotai Company Limited | Méthode pour préparer un substrat pour fabriquer des éléments semi-conducteurs |
US5400548A (en) * | 1992-07-23 | 1995-03-28 | Wacker-Chemitronic Gesellschaft Fur Elektronik-Grundstoffe Mbh | Process for manufacturing semiconductor wafers having deformation ground in a defined way |
WO2000048238A1 (fr) * | 1999-02-10 | 2000-08-17 | Commissariat A L'energie Atomique | Structure multicouche a contraintes internes controlees et procede de realisation d'une telle structure |
EP1050901A2 (fr) * | 1999-04-30 | 2000-11-08 | Canon Kabushiki Kaisha | Procédé de séparation d'un elément composé et procédé pour la fabrication d'un film mince |
Non-Patent Citations (1)
Title |
---|
PATENT ABSTRACTS OF JAPAN vol. 013, no. 173 (E - 748) 24 April 1989 (1989-04-24) * |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8609514B2 (en) | 1997-12-10 | 2013-12-17 | Commissariat A L'energie Atomique | Process for the transfer of a thin film comprising an inclusion creation step |
US8470712B2 (en) | 1997-12-30 | 2013-06-25 | Commissariat A L'energie Atomique | Process for the transfer of a thin film comprising an inclusion creation step |
US8389379B2 (en) | 2002-12-09 | 2013-03-05 | Commissariat A L'energie Atomique | Method for making a stressed structure designed to be dissociated |
US8048766B2 (en) | 2003-06-24 | 2011-11-01 | Commissariat A L'energie Atomique | Integrated circuit on high performance chip |
US8664084B2 (en) | 2005-09-28 | 2014-03-04 | Commissariat A L'energie Atomique | Method for making a thin-film element |
US8778775B2 (en) | 2006-12-19 | 2014-07-15 | Commissariat A L'energie Atomique | Method for preparing thin GaN layers by implantation and recycling of a starting substrate |
US8252663B2 (en) | 2009-06-18 | 2012-08-28 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method of transferring a thin layer onto a target substrate having a coefficient of thermal expansion different from that of the thin layer |
Also Published As
Publication number | Publication date |
---|---|
US8389379B2 (en) | 2013-03-05 |
JP2006509377A (ja) | 2006-03-16 |
ATE325429T1 (de) | 2006-06-15 |
DE60305067D1 (de) | 2006-06-08 |
US20060205179A1 (en) | 2006-09-14 |
FR2848336A1 (fr) | 2004-06-11 |
JP4943656B2 (ja) | 2012-05-30 |
EP1570516B1 (fr) | 2006-05-03 |
EP1570516A1 (fr) | 2005-09-07 |
FR2848336B1 (fr) | 2005-10-28 |
US20100167499A1 (en) | 2010-07-01 |
DE60305067T2 (de) | 2006-12-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP1570516B1 (fr) | Procede de realisation d'une structure contrainte destinee a etre dissociee | |
EP1570509B1 (fr) | Procede de realisation d' une structure complexe par assemblage de structures contraintes | |
EP0950257B1 (fr) | Procede de fabrication d'un film mince sur un support | |
EP1155442B1 (fr) | Procede de realisation d'une structure multicouche a contraintes internes controlees | |
EP0898307B1 (fr) | Procédé de traitement pour le collage moléculaire et le décollage de deux structures | |
EP1435111B1 (fr) | Procede de fabrication de couches minces contenant des microcomposants | |
EP2264742B1 (fr) | Procédé de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique différent de celui de la couche mince | |
EP1203403A1 (fr) | Procede de transfert d'une couche mince comportant une etape de surfragilisation | |
FR2889887A1 (fr) | Procede de report d'une couche mince sur un support | |
EP1378004A2 (fr) | Substrat demontable a tenue mecanique controlee et procede de realisation | |
EP1285461A1 (fr) | Substrat fragilise et procede de fabrication d'un tel substrat | |
FR2795866A1 (fr) | Procede de realisation d'une membrane mince et structure a membrane ainsi obtenue | |
EP2842155B1 (fr) | Procede de collage dans une atmosphere de gaz presentant un coefficient de joule-thomson negatif | |
EP1487012A2 (fr) | Procédé de réalisation de structure hétérogène et structure obtenue par un tel procédé | |
FR2943177A1 (fr) | Procede de fabrication d'une structure multicouche avec report de couche circuit | |
EP1520669B1 (fr) | Procédé de séparation de plaques collées entre elles pour constituer une structure empilée | |
FR2924273A1 (fr) | Procede de moderation de deformation | |
EP2302666A2 (fr) | Procédé de planarisation par ultrasons d'un substrat dont une surface a été libérée par fracture d'une couche enterrée fragilisée | |
EP1861873A1 (fr) | Procede de fabrication d'une hetero-structure comportant au moins une couche epaisse de materiau semi-conducteur | |
FR3111232A1 (fr) | Substrat temporaire demontable compatible avec de tres hautes temperatures et procede de transfert d’une couche utile a partir dudit substrat | |
FR2951869A1 (fr) | Procede de realisation d'une structure a couche enterree par implantation et transfert |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): JP US |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR |
|
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2003815088 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2004566101 Country of ref document: JP |
|
WWP | Wipo information: published in national office |
Ref document number: 2003815088 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 10538482 Country of ref document: US |
|
WWG | Wipo information: grant in national office |
Ref document number: 2003815088 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 10538482 Country of ref document: US |