WO2004059731A1 - Silicon on sapphire structure (devices) with buffer layer - Google Patents

Silicon on sapphire structure (devices) with buffer layer Download PDF

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Publication number
WO2004059731A1
WO2004059731A1 PCT/US2002/041183 US0241183W WO2004059731A1 WO 2004059731 A1 WO2004059731 A1 WO 2004059731A1 US 0241183 W US0241183 W US 0241183W WO 2004059731 A1 WO2004059731 A1 WO 2004059731A1
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WO
WIPO (PCT)
Prior art keywords
layer
silicon
sapphire
silicon oxide
interface
Prior art date
Application number
PCT/US2002/041183
Other languages
French (fr)
Inventor
Louis L Hsu
Leathen Shi
Li-Kong Wang
Original Assignee
International Business Machines Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corporation filed Critical International Business Machines Corporation
Priority to PCT/US2002/041183 priority Critical patent/WO2004059731A1/en
Priority to AU2002361847A priority patent/AU2002361847A1/en
Publication of WO2004059731A1 publication Critical patent/WO2004059731A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H01L29/6678—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates on sapphire substrates, e.g. SOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/86—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/78654—Monocrystalline silicon transistors
    • H01L29/78657—SOS transistors

Definitions

  • This invention relates to the field of integrated circuitry. More
  • the invention relates to the field of integrated circuits
  • CMOS devices built on the silicon on insulator (SOI) substrates can be any type of semiconductor material.
  • SOI silicon on insulator
  • Sapphire is a highly transparent
  • silicon and sapphire layer causes defects in the silicon device like
  • An object of this invention is an improved silicon on sapphire
  • An object of this invention is an improved a silicon on sapphire
  • An object of this invention is an improved silicon on sapphire
  • An object of this invention is an improved silicon on sapphire
  • An object of this invention is an improved a silicon on sapphire
  • An object of this invention is an improved silicon on sapphire
  • the present invention is an improved silicon on sapphire structure
  • the buffer layer is layer of silicon oxide material that
  • the buffer layer comprises two layers. A first
  • a second silicon oxide layer is formed between the silicon and the oxide layer.
  • oxide layers are then attached, e.g., by a wafer bonding technique.
  • This structure has no conductive paths beneath the oxide insulator(s)
  • Figure 1 is a block diagram perspective view of a silicon on sapphire
  • Figure 2 is a block diagram perspective view of a silicon on sapphire
  • passive components are built on sapphire
  • sapphire substrate is totally transparent to RF radiation and optical
  • silicate glass plastic, or any organic material like polyamide.
  • sapphire is a preferred embodiment because it has
  • the film structure of the silicon 107 on sapphire 103 is shown in
  • sapphire 103 are thermal grown oxide.
  • This layer 105 can provide improved adhesive property when the
  • substrate 103 is annealed during the device fabrication procedure.
  • oxide layer is designed to provide a viscous layer between the
  • CMOS FET devices 102 are fabricated on the sapphire
  • oxide 104 is either deposited or filled with a shallow trench isolation
  • the oxide layers serves
  • the silicon dioxide layer 105 is thermally grown from the silicon to preserve good interface property and device
  • a layer of silicon dioxide 105 is grown on the device wafer 107 to
  • layer can be as thin as 10-20 angstrom to 1 micron or greater.
  • silicon dioxide layer 105 is deposited on the device layer 107 by
  • silicon dioxide layer 105 and the device layer 107 may not be a
  • the silicon wafer and the sapphire 103 are bonded together and
  • CMP Chemical Mechanical Polishing
  • the material of the silicon device wafer can be remove to the thin final
  • the CMOS devices 102 can be fabricated using a conventional
  • the passive components 101 (capacitors, inductors, resistors, etc)
  • planar coil 101 is shown. Since there is no underlying
  • Figure 2 is a block diagram perspective view of an alternative
  • the upper silicon oxide layer 105 which directly
  • the upper oxide layer 105 a preferred embodiment, the
  • bottom silicon oxide layer 206 is a deposited oxide that is typically
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • This silicon oxide layer 206 is designed to
  • layer 105 can be
  • CMOS FET devices 102 are fabricated on the sapphire
  • isolation oxide 104 is either deposited or filled with a shallow trench
  • STI isolation
  • inductive coil component ( inductive coil ) is shown as 101.
  • oxide layers There two oxide layers
  • the thickness of layer 105 can be for 10-20 angstroms to 1 micron or
  • the thickness of the deposited oxide can be from 100-200
  • CMP Chemical Mechanical Polishing
  • the material of the silicon device wafer can be remove to the thin final
  • Shallow Trench Isolation process is used to form the isolation 104
  • this isolation structure 104 also can be used to make this isolation structure 104.
  • the isolation structure 104 is silicon oxide
  • the sapphire layer 103 are insulating layers that

Abstract

An improved silicon on sapphire structure and/or device has one or more buffer layers. In a first preferred embodiment, the buffer layer is layer of silicon oxide material that prevents the stress induced defects in the silicon layer. In an alternative embodiment, the buffer layer comprises two layers. A first silicon oxide layer attached to the silicon to insure a perfect interface between the silicon. A second silicon oxide layer then is attached to the sapphire layer. The first and second silicon oxide layers are then attached, e.g., by a wafer bonding technique. This structure has no conductive paths beneath the oxide insulator(s) and therefore enables improved performance in radio frequency applications.

Description

SILICON ON SAPPHIRE STRUCTURE (DEVICES) WITH BUFFER
LAYER
Field of the Invention
This invention relates to the field of integrated circuitry. More
specifically, the invention relates to the field of integrated circuits
used in radio frequency applications.
Background of the Invention
CMOS devices built on the silicon on insulator (SOI) substrates can
have enhanced performance due to reduction of parasitic
capacitance and increase of carrier mobility. This kind of high
performance device and circuit technology at present can be applied
to operate at GHz RF applications. Integration of RF passive
components with this kind of technology enables high performance,
high integration level, low cost RF integrated circuits. However most
of the chips today are built on silicon based substrate, including
those on SOI wafers. This becomes a major drawback in RF
applications because the conducting silicon substrate becomes a
lose path in the substrate when the circuit and passive components are switching at RF frequency. A typical example is the inductor
induced Eddy current in the substrate from the current flowing in the
coil. The reduction of the Q factor due to the energy loss in the
substrate can significantly downgrade the efficiency of the circuits.
Building devices and components on an insulating substrate can not
only reduce dissipation loss and but also the insulator substrate is
transparent to the RF wave signals. Sapphire is a highly transparent
material at RF frequency with excellent insulating property. To build
silicon devices on sapphire substrate has been successfully
demonstrated for many years.
The material mismatch between silicon device layer and the
underneath sapphire can greatly degrade the possibility to make high
quality devices. This is because the material mismatch between the
silicon and sapphire layer causes defects in the silicon device like
dislocations, cracks, and/or leakage currents. Also, the present
melting and re-crystallization approach to fabricate silicon on
sapphire substrates significantly increasing the defect density in the
silicon device layer. Objects of the Invention
An object of this invention is an improved silicon on sapphire
structure (device).
An object of this invention is an improved a silicon on sapphire
structure (device) with a reduced mismatch between the silicon and
the sapphire layers.
An object of this invention is an improved silicon on sapphire
structure (device) made without melting and re-crystallization of the
layers.
An object of this invention is an improved silicon on sapphire
structure (device) with an oxide layer in between the silicon and
sapphire layers.
An object of this invention is an improved a silicon on sapphire
structure (device) used in radio frequency applications. An object of this invention is an improved silicon on sapphire
structure (device) with two separate and adjacent oxide layers, one
on the silicon layer and one on the sapphire substrate
Summary of the Invention
The present invention is an improved silicon on sapphire structure
and/or device with one or more buffer layers. In a first preferred
embodiment, the buffer layer is layer of silicon oxide material that
prevents the stress induced defects in the silicon layer. In an
alternative embodiment, the buffer layer comprises two layers. A first
silicon oxide layer attached to the silicon to insure a perfect interface
between the silicon and the oxide layer. A second silicon oxide layer
then is attached to the sapphire layer. The first and second silicon
oxide layers are then attached, e.g., by a wafer bonding technique.
This structure has no conductive paths beneath the oxide insulator(s)
and therefore enables improved performance in radio frequency
applications. Brief Description of the Figures
Figure 1 is a block diagram perspective view of a silicon on sapphire
film structure with a one layer silicon oxide bonding interface.
Figure 2 is a block diagram perspective view of a silicon on sapphire
film structure with a dual layer silicon oxide bonding interface.
Detailed Description of the Invention
In the present invention passive components are built on sapphire
substrates. The silicon layer containing devices on the sapphire
substrate is defect free in contrast to the other structures, and the
sapphire substrate is totally transparent to RF radiation and optical
light. Although the sapphire is our choice at this point as the
substrate material, many other types of insulator substrates can also
substitute the sapphire substrate used here as well. For example,
silicate glass, plastic, or any organic material like polyamide.
However, sapphire is a preferred embodiment because it has
excellent thermal conductivity. The film structure of the silicon 107 on sapphire 103 is shown in
Figure 1. The buffer layer 105 between the silicon 107 and the
sapphire 103 are thermal grown oxide.
This layer 105 can provide improved adhesive property when the
substrate 103 is annealed during the device fabrication procedure.
Also, it 105 serves as a stress relieve layer to reduce the thermal
mismatch induced defects during annealing process. This silicon
oxide layer is designed to provide a viscous layer between the
device-layer 107 to the sapphire 103 to absorb the thermal induced
stress between the two layers (103, 107).
The CMOS FET devices 102 are fabricated on the sapphire
substrate 103 in the silicon layer 107. Between devices the isolation
oxide 104 is either deposited or filled with a shallow trench isolation
(STI) process or known equivalent. A representative passive
component ( inductive coil ) is shown as 101. The oxide layers serves
as the buffer layers 105 between the sapphire substrate 103 and the
silicon device layer 107. The silicon dioxide layer 105 is thermally grown from the silicon to preserve good interface property and device
characteristics.
A layer of silicon dioxide 105 is grown on the device wafer 107 to
make good oxide to device interface properties. The thickness of this
layer can be as thin as 10-20 angstrom to 1 micron or greater. By
growing the silicon dioxide layer 105 on the device wafer 107 a
perfect crystal interface is created between the silicon dioxide layer
105 and the silicon device layer 107. In alternative embodiments, the
silicon dioxide layer 105 is deposited on the device layer 107 by
known techniques. In these processes, the interface between the
silicon dioxide layer 105 and the device layer 107 may not be a
perfect crystal interface.
The silicon wafer and the sapphire 103 are bonded together and
annealed to promote the adhesiveness according to well known
techniques.
By using a Chemical Mechanical Polishing (CMP) process, most of
the material of the silicon device wafer can be remove to the thin final
layer 107 at the thickness desired. After that a patterned Shallow Trench Isolation process is used to form the isolation 104 between
devices as indicated. Of course, other methods such as local
oxidation also can be used to make this isolation structure.
The CMOS devices 102 can be fabricated using a conventional
processing.
The passive components 101 , (capacitors, inductors, resistors, etc)
can be fabricated together with the device interconnect process. An
example of planar coil 101 is shown. Since there is no underlying
conductive substrate, there is no Eddy current type of loss of RF
signal.
Figure 2 is a block diagram perspective view of an alternative
preferred embodiment with two oxide buffer layers. Components that
are the same as those in Figure 1 , have the same reference numbers
and description as that in Figure 1. These two layers (105, 206) can
provide improved adhesive property when the substrate is annealed
during the device fabrication procedure. Also, they (105, 206) serve
as a stress relieve buffer layer to reduce the thermal mismatch
induced defects during annealing process. In a preferred embodiment, the upper silicon oxide layer 105 which directly
interfaces with silicon layer 107 is thermally grown from the silicon
film 107 to provide good interface between the silicon device layer
107 to the upper oxide layer 105. In a preferred embodiment, the
bottom silicon oxide layer 206 is a deposited oxide that is typically
done in a Low Pressure Chemical Vapor Deposition (LPCVD)
process or a Plasma Enhanced Chemical Vapor Deposition (PECVD)
process, or equivalent. This silicon oxide layer 206 is designed to
provide a viscous layer between the silicon device-layer 107 and the
sapphire 103 to absorb the thermal induced stress between the two
layers (103, 107). In alternative embodiments, layer 105 can be
deposited.
The CMOS FET devices 102 are fabricated on the sapphire
substrate 103 in the silicon layer 107. Between devices 102 the
isolation oxide 104 is either deposited or filled with a shallow trench
isolation (STI) process or known equivalent. A representative passive
component ( inductive coil ) is shown as 101. There two oxide layers
(105, 206) serve as the buffer layers between the substrate 103 and
the silicon device layer 107. The thickness of layer 105 can be for 10-20 angstroms to 1 micron or
above. The thickness of the deposited oxide can be from 100-200
angstroms to several microns and above.
By using a Chemical Mechanical Polishing (CMP) process, most of
the material of the silicon device wafer can be remove to the thin final
layer 107 to produce the thickness desired. After that a patterned
Shallow Trench Isolation process is used to form the isolation 104
between devices as indicated. Of course, other methods, such as
local oxidation, also can be used to make this isolation structure 104.
In a preferred embodiment, the isolation structure 104 is silicon oxide
or other dielectric material as is commonly used in the art.
Therefore, in both the single layer buffer and the double layer buffer
embodiment the isolation sections 104, the silicon oxide layer(s) (105
or 105 and 206), and the sapphire layer 103 are insulating layers that
provide no electrical conductivity between the electrical components
(101 , 102). However, these layers (103, 104, 105, and 206) are
transparent to electromagnetic energy, particularly radio frequency
energy and still provide a defect free interface between the silicon
device layer 107 and the substrate 103. The method of making these structures is further described and
claimed in U.S. Patent application number XXX, entitled Method of
Fabricating Silicon Devices on Sapphire with Wafer Bonding to same
inventors, which is herein incorporated by reference in its entirety.
Given this disclosure other embodiments of the invention will become
apparent. These embodiments are also within the contemplation of
the inventors.

Claims

ClaimsWe claim:
1. A silicon on sapphire structure comprising:
a silicon layer;
a sapphire layer; and
an insulating layer sandwiched between the silicon and sapphire
layer.
2. A structure, as in claim 1 , where the insulating layer is a silicon
oxide-silicon interface between the silicon layer and the sapphire
layer that provides a crystal interface between the insulating layer
and the silicon.
3. A structure, as in claim 2, where the silicon oxide-silicon interface
is created by growing the silicon oxide layer on the silicon layer.
4. A structure, as in claim 1 , where the insulating layer is a silicon
oxide layer and the interface between the silicon oxide layer and the
silicon and the silicon layer is not a crystal interface.
5. A structure, as in claim 4, where the silicon oxide-silicon interface
is created by depositing the silicon oxide layer on the silicon layer.
6. A structure, as in claim 1 , where the silicon layer comprises one or
more component islands made of silicon and one or more isolation
sections between the silicon islands, the isolation sections being
made of silicon oxide.
7. A structure, as in claim 6, where at least one of the component
islands is used to form one or more electrical components that are
isolated by the silicon oxide layer and the sapphire layer.
8. A structure, as in claim 7, where at least one of the isolation
sections comprises the silicon oxide layer and the sapphire layer and
the isolation sections are insulating layers that are used to form
passive devices.
9. A structure, as in claim 8, where the passive devices comprise any
one or more of the following: a capacitor, an inductor, and a resistor.
10. A silicon on sapphire structure comprising:
a silicon layer;
a sapphire layer; and
a buffer layer sandwiched between the silicon and sapphire layer, the
buffer layer comprising a first dielectric layer attached to the silicon
layer and a second dielectric layer attached to the sapphire layer, the
first and second dielectric layers being attached to one another.
11. A structure, as in claim 9, where the first dielectric layer is a
silicon oxide-silicon layer providing a perfect crystal interface
between the silicon layer and the first dielectric layer.
12. A structure, as in claim 1 1 , where the silicon oxide of the first
dielectric layer is created by growing the silicon oxide layer on the
silicon layer.
13. A structure, as in claim 10, where the first dielectric layer is a
silicon oxide layer bound to the silicon layer as a crystal interface.
14. A structure, as in claim 13, where the interface between the
silicon oxide layer and the silicon layer is created by depositing the
silicon oxide layer on the silicon layer.
15. A structure, as in claim 10, where the silicon layer comprises one
or more component islands made of silicon and one or more isolation
sections between the silicon islands, the isolation section being made
of silicon oxide.
16. A structure, as in claim 15, where one or more of the component
islands is an electrical component and the isolation sections, the
silicon oxide layer, and the sapphire layer are insulating layers that
provide no electrical conductivity between the electrical components.
17. A structure, as in claim 16, where a radio frequency wave can
communicate with one or more of the electrical components through
the insulating layers.
18. A structure, as in claim 10, where the interface between the
second dielectric layer and the sapphire layer is not a crystal
interface.
19. A structure, as in claim 18, where the interface between the
second dielectric layer and the sapphire layer is created by
depositing the second dielectric layer on the sapphire layer.
20. A structure, as in claim 10, where the silicon layer comprises one
or more component islands made of silicon and one or more isolation sections between the silicon islands, the isolation sections being
made of silicon oxide.
21. A structure, as in claim 20, where at least one of the isolation
sections is used to form one or more passive electrical components.
22. A structure, as in claim 21 where the passive electrical
components include any one or more of the following: a resister, a
capacitor, and an inductor.
PCT/US2002/041183 2002-12-20 2002-12-20 Silicon on sapphire structure (devices) with buffer layer WO2004059731A1 (en)

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AU2002361847A AU2002361847A1 (en) 2002-12-20 2002-12-20 Silicon on sapphire structure (devices) with buffer layer

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Application Number Priority Date Filing Date Title
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9154678B2 (en) 2013-12-11 2015-10-06 Apple Inc. Cover glass arrangement for an electronic device
US9225056B2 (en) 2014-02-12 2015-12-29 Apple Inc. Antenna on sapphire structure
US9221289B2 (en) 2012-07-27 2015-12-29 Apple Inc. Sapphire window
US9232672B2 (en) 2013-01-10 2016-01-05 Apple Inc. Ceramic insert control mechanism
US9632537B2 (en) 2013-09-23 2017-04-25 Apple Inc. Electronic component embedded in ceramic material
US9678540B2 (en) 2013-09-23 2017-06-13 Apple Inc. Electronic component embedded in ceramic material
US10052848B2 (en) 2012-03-06 2018-08-21 Apple Inc. Sapphire laminates
US10406634B2 (en) 2015-07-01 2019-09-10 Apple Inc. Enhancing strength in laser cutting of ceramic components

Citations (1)

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Publication number Priority date Publication date Assignee Title
US20020167068A1 (en) * 2001-05-09 2002-11-14 International Business Machines Corporation Silicon on sapphire structure (devices) with buffer layer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020167068A1 (en) * 2001-05-09 2002-11-14 International Business Machines Corporation Silicon on sapphire structure (devices) with buffer layer

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10052848B2 (en) 2012-03-06 2018-08-21 Apple Inc. Sapphire laminates
US9221289B2 (en) 2012-07-27 2015-12-29 Apple Inc. Sapphire window
US9232672B2 (en) 2013-01-10 2016-01-05 Apple Inc. Ceramic insert control mechanism
US9632537B2 (en) 2013-09-23 2017-04-25 Apple Inc. Electronic component embedded in ceramic material
US9678540B2 (en) 2013-09-23 2017-06-13 Apple Inc. Electronic component embedded in ceramic material
US9154678B2 (en) 2013-12-11 2015-10-06 Apple Inc. Cover glass arrangement for an electronic device
US10324496B2 (en) 2013-12-11 2019-06-18 Apple Inc. Cover glass arrangement for an electronic device
US10386889B2 (en) 2013-12-11 2019-08-20 Apple Inc. Cover glass for an electronic device
US9225056B2 (en) 2014-02-12 2015-12-29 Apple Inc. Antenna on sapphire structure
US9461357B2 (en) 2014-02-12 2016-10-04 Apple Inc. Antenna on sapphire structure
US9692113B2 (en) 2014-02-12 2017-06-27 Apple Inc. Antenna on sapphire structure
US10406634B2 (en) 2015-07-01 2019-09-10 Apple Inc. Enhancing strength in laser cutting of ceramic components

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