WO2004059697B1 - Adaptive negative differential resistance device - Google Patents

Adaptive negative differential resistance device

Info

Publication number
WO2004059697B1
WO2004059697B1 PCT/US2003/040268 US0340268W WO2004059697B1 WO 2004059697 B1 WO2004059697 B1 WO 2004059697B1 US 0340268 W US0340268 W US 0340268W WO 2004059697 B1 WO2004059697 B1 WO 2004059697B1
Authority
WO
WIPO (PCT)
Prior art keywords
ndr
channel
adaptive
current
silicon
Prior art date
Application number
PCT/US2003/040268
Other languages
French (fr)
Other versions
WO2004059697A2 (en
WO2004059697A3 (en
Inventor
Tsu-Jae King
Original Assignee
Progressant Technologies Inc
Tsu-Jae King
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Progressant Technologies Inc, Tsu-Jae King filed Critical Progressant Technologies Inc
Priority to JP2004563703A priority Critical patent/JP2006511941A/en
Priority to EP03814122A priority patent/EP1584107A4/en
Priority to AU2003303431A priority patent/AU2003303431A1/en
Publication of WO2004059697A2 publication Critical patent/WO2004059697A2/en
Publication of WO2004059697A3 publication Critical patent/WO2004059697A3/en
Publication of WO2004059697B1 publication Critical patent/WO2004059697B1/en

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    • G11C11/39—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
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Abstract

A method of controlling a negative differential resistance (NDR) element is disclosed, which includes altering various NDR characteristics during operation to effectuate different NDR modes. By changing biasing conditions applied to the NDR element (such as a silicon based NDR FET) a peak-to-valley ratio (PVR) (or some other characteristic) can be modified dynamically to accommodate a desired operational change in a circuit that uses the NDR element. In a memory or logic application, for example, a valley current can be reduced during quiescent periods to reduce operating power. Thus an adaptive NDR element can be utilized advantageously within a conventional semiconductor circuit.

Claims

AMENDED CLAIMS [(received by the International Bureau on 21 April 2005 (21.04.05); new claims 26-53 added; remaining claims unchanged (13 pages)] 1. A method of operating an adaptive silicon based negative differential resistance (NDR) device in an integrated circuit, comprising the steps of: operating the adaptive silicon-based NDR device with a first current-voltage relationship during a first time period; and operating the adaptive silicon-based NDR device with a second current-voltage relationship during a second time period; and wherein said first current-voltage relationship and said second current-voltage relationship NDR characteristic are sufficiently different so as to permit the adaptive silicon based NDR device to have two distinct operational modes, including a first operational mode and a second operational mode respectively; switching the adaptive silicon-based NDR device between said first operational mode and said second operational mode in response to a control signal generated by a control circuit on the integrated circuit.
2. The method of claim 1, wherein said first current- voltage relationship and said second current-voltage relationship are caused by applying a first gate bias potential and a second gate bias potential respectively to a gate terminal of the silicon based NDR device.
3. The method of claim 1, wherein said first current- voltage relationship and said second current-voltage relationship are caused by applying a first gating signal at a first clocking frequency and a second gating signal at a second clocking frequency respectively to the adaptive silicon based NDR device.
4. The method of claim 1, wherein said control signal is based on a power consumption mode used in the integrated circuit, such that during said second operational mode said adaptive silicon based NDR device consumes less power than during said first operational mode.
5. The method of claim 1, wherein a first current used by the adaptive silicon based NDR device during said first operational mode for a given bias condition is greater than a second current used by the adaptive silicon based NDR device during said second operational mode.
6. The method of claim 1, wherein said control signal is based on a speed mode used in the integrated circuit, such that during said second operational mode the adaptive silicon based NDR device operates more slowly than during said first operational mode.
7. The method of claim 1, wherein in said first operational mode the adaptive silicon based NDR device switches between a first peak NDR current and a first valley NDR current faster than the adaptive silicon NDR device switches between a second peak NDR current and a second valley NDR current in said second operational mode.
8. The method of claim 1, wherein the adaptive silicon based NDR device is used in a memory cell, and said control signal is a read/write command such that said first operational mode is related to a read or write operation, and said second operational mode is related to a quiescent storage operation.
9. The method of claim 1, wherein the adaptive silicon based NDR device is used in a logic circuit, said first operational mode is related to a normal power mode operation, and said second operational mode is related to a low power mode operation.
10. A method of operating a circuit that includes an adaptive negative differential resistance (NDR) element, comprising the steps of : (a) operating the adaptive NDR element with a first peak-to-valley ratio (PVR) during a first period in which the circuit is performing a processing operation; and (b) operating the adaptive NDR element with a second PVR during a second period in which the circuit is not performing a processing operation, so as to reduce a current consumed by the adaptive NDR element, said first PVR being at least 50% greater than said second PVR; wherein a peak-to-valley ratio (PVR) characteristic of the adaptive NDR element is adaptable to an operational requirement of the circuit.
11. The method of claim 10 wherein the circuit is a logic circuit, and the processing operation is a BOOLEAN logic function.
12. The method of claim 10 wherein the circuit is a memory cell, and the processing operation is an access operation for a data value stored in said memory cell.
13. A method of making a semiconductor circuit comprising the steps of: forming a silicon-based adaptive NDR device which can operate with a first current-voltage relationship during a first time period and a second current-voltage relationship during a second time period; and wherein said first current-voltage relationship and said second current-voltage relationship are sufficiently different so as to permit said silicon based adaptive NDR device to have two distinct operational modes, including a first operational mode and a second operational mode respectively; forming a control circuit for switching said silicon-based adaptive NDR device between said first operational mode and said second operational mode.
14. The method of claim 13 , further including a step of forming a power regulator circuit which regulates power consumption of an integrated circuit in which said semiconductor circuit is formed, and coupling said control circuit to said power regulator circuit.
15. The method of claim 13, wherein a nominal peak-to- valley current ratio (PVR) is set in said silicon-based adaptive NDR device during a manufacturing procedure, and said nominal PVR can be adjusted by said control circuit.
16. The method of claim 13, further including a step of forming a second silicon-based
NDR device in a common substrate with said silicon-based adaptive NDR device, such that said silicon-based adaptive NDR device has a first peak-to-valley current ratio (PVR) that is substantially different from a second PVR of said second silicon-based NDR device.
17. The method of claim 16, wherein said second silicon- based NDR device is also adaptive and operates with different current-voltage relationships in response to control signals from said control circuit .
18. A semiconductor circuit comprising: an adaptive-silicon based NDR device which is adapted to operate with a first current-voltage relationship during a first time period and a second current-voltage relationship during a second time period; and wherein said first current-voltage relationship and said second current-voltage relationship NDR characteristic are sufficiently different so as to permit said adaptive silicon based NDR device to have two distinct operational modes, including a first operational mode and a second operational mode respectively; a control circuit for switching said adaptive silicon-based NDR device between said first operational mode and said second operational mode.
19. The semiconductor circuit of claim 18, wherein said control circuit controls a peak- to-valley current ratio (PVR) of said adaptive silicon-based NDR device.
20. The semiconductor circuit of claim 18, wherein said adaptive silicon-based NDR device is configured as part of a memory cell.
21. The semiconductor circuit of claim 18, wherein said adaptive silicon-based NDR device is configured as part of a logic gate.
22. The semiconductor circuit of claim 18, further including a second control circuit, and wherein said control circuit controls a peak-to-valley current ratio (PVR) of a plurality of a first type of said adaptive silicon-based NDR device used in a memory circuit, and said second control circuit controls a peak-to-valley current ratio (PVR) of a plurality of a second type of said adaptive silicon-based NDR device used in a logic circuit.
23. In a silicon-based negative differential resistance (NDR) device, the improvement comprising: the NDR device being configured to be self-adaptive such that a valley current decreases during a first time period to cause a corresponding increase in a peak-to- valley current ratio (PVR) during said first time period; wherein an external control signal is not required to modify said PVR for the NDR device.
24. The silicon based NDR device of claim 23, wherein said PVR for the device is adjusted by controlling a switching speed for the device, such that a slower switching speed can be used to increase said PVR for the device.
25. The silicon based NDR device of claim 23, wherein said PVR for the device exceeds ten (10) during at least part of said first time period.
26. A method of. forming a semiconductor device having a control gate, a source region, and a drain region comprising the steps of : (a) providing a substrate having a first type of conductivity; (b) forming a channel between the source and drain region for carrying said charge carriers between the source and drain regions, said channel being doped in two separate operations such that : i) during a first channel doping operation said channel is doped with first channel impurities that also have said first type of conductivity; and ii) during a second channel doping operation said channel is counter doped with second channel impurities that have a second type of conductivity; wherein said second type of conductivity is opposite to said first type of conductivity; and wherein as a result of said first channel doping operation and said second channel doping operation said channel region as formed has a net first type of conductivity; and (c) forming a charge trapping region that has an interface with said channel, said charge trapping region having charge trapping sites which temporarily trap charge carriers along said interface and permit the device to operate with a negative differential resistance characteristic; and wherein said charge trapping sites are derived at least in part from said first channel impurities forming a charge trap distribution that is substantially concentrated at said interface.
27. The method of claim 26, wherein Arsenic is used for said second channel doping operation.
28. The method of claim 26, wherein Boron is used for said first channel doping operation.
29. The method of claim 26, wherein said charge trapping region does not extend throughout an entire length of said interface with said channel .
30. The method of claim 29, wherein said charge trapping region extends from a source region to enhance source side trapping .
31. The method of claim 26, wherein said charge trapping region is formed as part of a gate insulator for the semiconductor device.
32. The method of claim 26, wherein trapping sites in said charge trapping region are formed from said first channel impurities .
33. The method of claim 26, wherein said first channel impurities have a concentration at said interface that is at least 1 order of magnitude larger than a net doping concentration of said channel region.
34. The method of claim 26, wherein said trapping sites are distributed unevenly along said interface to effectuate a variable trapping rate for said energetic carries along said interface .
35. The method of claim 34 wherein said variable trapping rate increases substantially proportional to a distance along said interface.
36. The method of claim 34 wherein said variable trapping rate near a source region associated is greater than that near a drain region.
37. The method of claim 26, wherein said charge trapping sites are formed in said charge trapping region in two separate processing operations, including an implant operation for introducing charge trapping sites, and a heat treatment operation for modifying said charge trapping sites.
38. A method of forming a transistor having a control gate, a source region, and a drain region comprising the steps of: (a) providing a substrate having a first type of conductivity; (b) forming a channel for the transistor between the source and drain region for carrying charge carriers between the source and drain regions; (c) forming a gate insulator for the transistor; and (d) implanting first impurities into and through said gate insulator after said gate insulator is formed, so that some of said first impurities form charge trapping sites with an energy level adapted for temporarily trapping charge carriers along said interface and other of said first impurities are distributed so as to increase an electrical field strength in said channel, wherein the transistor operates with a negative differential resistance characteristic.
39. The method of claim 38, further including a step of implanting second impurities into said channel to reduce a threshold voltage of the transistor, said second impurities having a conductivity type opposite to said first impurities.
40. The method of claim 39, wherein said channel has a net conductivity that is the same as said first impurities.
41. A method of forming a semiconductor device on a substrate having a first type of conductivity, the semiconductor device having a control gate, a source region, and a drain region coupled to the source region through a channel, the method comprising the steps of: (a) implanting impurities having a second type of conductivity into a channel region of the semiconductor device to form the channel; (b) performing a thermal oxidation reaction at least in said channel region to form a first dielectric layer forming an interface with the channel, wherein during step (b) said impurities are incorporated into said first dielectric layer to form charge trapping sites with an energy level adapted for temporarily trapping charge carriers along said interface; and (c) performing a deposition operation to form a second dielectric layer on said first dielectric layer, wherein said first dielectric layer and said second dielectric layer form part or all of a gate insulator for the semiconductor device, and further wherein the semiconductor device can operate with a negative differential resistance characteristic.
42. The method of claim 41, wherein two separate implant operations are performed in said channel, including a first type of impurities used in step (a) , and a second type of impurities used in a subsequent counter-doping step, said second type of impurities being opposite to said first type of impurities .
43. The method of claim 42, further including an anneal operation after said two separate implant operations are performed.
70
44. A method of forming a silicon based negative differential resistance (NDR) semiconductor device comprising the steps of: (a) providing a substrate; (b) forming a channel region for carrying a current of charge carriers for the silicon based NDR semiconductor device; (c) implanting first impurities into said channel region; (d) forming a first dielectric layer that has an interface with said channel; and (e) annealing said channel region to reduce implantation defects and distribute said first impurities so as to concentrate them along said interface with said channel, wherein said first impurities as distributed along said interface form charge trapping sites with an energy level adapted for temporarily trapping said charge carriers to effectuate an NDR characteristic.
45. The method of claim 44, wherein said first impurities have a first conductivity type that is the same as said substrate.
46. The method of claim 44, wherein the silicon based NDR semiconductor device is a field effect transistor (FET) .
47. The method of claim 46, further including a step of completing a gate insulator for the FET.
48. The method of claim 47, further including a step of performing another annealing operation after said gate insulator is formed.
71
49. The method of claim 44, wherein step (e) is performed before a gate is formed for the silicon based negative differential resistance (NDR) semiconductor device.
50. A method of forming a semiconductor structure comprising the steps of: (a) forming a trapping layer proximate to a transistor channel region, said trapping layer including a carrier trapping sites configured for trapping and de- trapping carriers from said channel region; and (b) performing a plurality of separate annealing operations on the semiconductor structure, wherein at least a first one of said separate annealing operations is adapted so as to distribute and concentrate said carrier trapping sites along an interface with said transistor channel region and with a reduced concentration in a bulk region of said trapping layer; wherein said trapping sites are formed to have a concentration and arrangement within said dielectric layer so that said transistor channel can exhibit negative differential resistance.
51. The method of claim 50, wherein a second one of said separate annealing operations is also adapted to alter at least one of a concentration and an arrangement of said charge trapping sites along said interface.
52. The method of claim 50, wherein only said first one of said separate annealing operations operates to distribute said carrier trapping sites.
53. The method of claim 50, wherein a net doping concentration of first impurities in said channel region is at least one order of magnitude less a concentration of carrier
72 trapping sites at said interface formed by said first impurities.
73
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CN1745472A (en) 2006-03-08
US20040110337A1 (en) 2004-06-10
KR20050084252A (en) 2005-08-26
US20050064645A1 (en) 2005-03-24
US7254050B2 (en) 2007-08-07
US6812084B2 (en) 2004-11-02
AU2003303431A8 (en) 2004-07-22
EP1584107A2 (en) 2005-10-12
JP2006511941A (en) 2006-04-06
EP1584107A4 (en) 2006-07-26
WO2004059697A2 (en) 2004-07-15
AU2003303431A1 (en) 2004-07-22
WO2004059697A3 (en) 2005-04-14

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