WO2004057660A3 - Method for producing a sublithographic gate structure for field effect transistors, and for producing an associated field effect transistor, an associated inverter, and an associated inverter structure - Google Patents

Method for producing a sublithographic gate structure for field effect transistors, and for producing an associated field effect transistor, an associated inverter, and an associated inverter structure Download PDF

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Publication number
WO2004057660A3
WO2004057660A3 PCT/DE2003/004046 DE0304046W WO2004057660A3 WO 2004057660 A3 WO2004057660 A3 WO 2004057660A3 DE 0304046 W DE0304046 W DE 0304046W WO 2004057660 A3 WO2004057660 A3 WO 2004057660A3
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WO
WIPO (PCT)
Prior art keywords
producing
field effect
inverter
associated inverter
gate structure
Prior art date
Application number
PCT/DE2003/004046
Other languages
German (de)
French (fr)
Other versions
WO2004057660A2 (en
Inventor
Helmut Tews
Rodger Fehlhaber
Original Assignee
Infineon Technologies Ag
Helmut Tews
Rodger Fehlhaber
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Helmut Tews, Rodger Fehlhaber filed Critical Infineon Technologies Ag
Priority to AU2003289828A priority Critical patent/AU2003289828A1/en
Publication of WO2004057660A2 publication Critical patent/WO2004057660A2/en
Publication of WO2004057660A3 publication Critical patent/WO2004057660A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/2815—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body

Abstract

The invention relates to a method for producing: a sublithographic gate structure; an associated field effect transistor; an associated inverter, and; an associated inverter structure. A sublithographic gate structure (SG) having slight variations in the critical dimensions thereof can be directly produced on the lateral walls of a lithographically structured mask (M0, 2) by the conformal formation of a gate insulation layer (3) and of a gate layer with subsequently executed anisotropic etching.
PCT/DE2003/004046 2002-12-20 2003-12-09 Method for producing a sublithographic gate structure for field effect transistors, and for producing an associated field effect transistor, an associated inverter, and an associated inverter structure WO2004057660A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003289828A AU2003289828A1 (en) 2002-12-20 2003-12-09 Method for producing a sublithographic gate structure for field effect transistors, and for producing an associated field effect transistor, an associated inverter, and an associated inverter structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2002160234 DE10260234A1 (en) 2002-12-20 2002-12-20 Method for producing a sublithographic gate structure for field effect transistors, an associated field effect transistor, an associated inverter and an associated inverter structure
DE10260234.4 2002-12-20

Publications (2)

Publication Number Publication Date
WO2004057660A2 WO2004057660A2 (en) 2004-07-08
WO2004057660A3 true WO2004057660A3 (en) 2005-03-31

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PCT/DE2003/004046 WO2004057660A2 (en) 2002-12-20 2003-12-09 Method for producing a sublithographic gate structure for field effect transistors, and for producing an associated field effect transistor, an associated inverter, and an associated inverter structure

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AU (1) AU2003289828A1 (en)
DE (1) DE10260234A1 (en)
TW (1) TWI264071B (en)
WO (1) WO2004057660A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070068087A1 (en) 2005-09-26 2007-03-29 Cabot Microelectronics Corporation Metal cations for initiating polishing
US7528065B2 (en) * 2006-01-17 2009-05-05 International Business Machines Corporation Structure and method for MOSFET gate electrode landing pad

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4358340A (en) * 1980-07-14 1982-11-09 Texas Instruments Incorporated Submicron patterning without using submicron lithographic technique
US4419809A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Fabrication process of sub-micrometer channel length MOSFETs
JPS6066861A (en) * 1983-09-22 1985-04-17 Toshiba Corp Manufacture of semiconductor device
US4597827A (en) * 1984-02-29 1986-07-01 Oki Electric Industry Co., Ltd. Method of making MIS field effect transistor having a lightly-doped region
EP0675544A1 (en) * 1994-03-31 1995-10-04 France Telecom Method of manufacturing a short channel insulated field effect transistor; and corresponding transistor
DE19536523A1 (en) * 1995-09-29 1997-04-03 Siemens Ag Method of manufacturing a gate electrode
US5950091A (en) * 1996-12-06 1999-09-07 Advanced Micro Devices, Inc. Method of making a polysilicon gate conductor of an integrated circuit formed as a sidewall spacer on a sacrificial material
US6097060A (en) * 1996-09-30 2000-08-01 Motorola, Inc. Insulated gate semiconductor device
US6124174A (en) * 1997-05-16 2000-09-26 Advanced Micro Devices, Inc. Spacer structure as transistor gate
US6225201B1 (en) * 1998-03-09 2001-05-01 Advanced Micro Devices, Inc. Ultra short transistor channel length dictated by the width of a sidewall spacer
US6392279B1 (en) * 1997-06-11 2002-05-21 Fujitsu Limited Semiconductor device having LDD structure adapted to lower parasitic capacitance and parasitic resistance
US20020086473A1 (en) * 2001-01-03 2002-07-04 Wen-Jer Tsai Process for fabricating CMOS transistor of IC devices employing double spacers for preventing short-channel effects

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6008087A (en) * 1998-01-05 1999-12-28 Texas Instruments - Acer Incorporated Method to form high density NAND structure nonvolatile memories

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4358340A (en) * 1980-07-14 1982-11-09 Texas Instruments Incorporated Submicron patterning without using submicron lithographic technique
US4419809A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Fabrication process of sub-micrometer channel length MOSFETs
JPS6066861A (en) * 1983-09-22 1985-04-17 Toshiba Corp Manufacture of semiconductor device
US4597827A (en) * 1984-02-29 1986-07-01 Oki Electric Industry Co., Ltd. Method of making MIS field effect transistor having a lightly-doped region
EP0675544A1 (en) * 1994-03-31 1995-10-04 France Telecom Method of manufacturing a short channel insulated field effect transistor; and corresponding transistor
DE19536523A1 (en) * 1995-09-29 1997-04-03 Siemens Ag Method of manufacturing a gate electrode
US6097060A (en) * 1996-09-30 2000-08-01 Motorola, Inc. Insulated gate semiconductor device
US5950091A (en) * 1996-12-06 1999-09-07 Advanced Micro Devices, Inc. Method of making a polysilicon gate conductor of an integrated circuit formed as a sidewall spacer on a sacrificial material
US6124174A (en) * 1997-05-16 2000-09-26 Advanced Micro Devices, Inc. Spacer structure as transistor gate
US6392279B1 (en) * 1997-06-11 2002-05-21 Fujitsu Limited Semiconductor device having LDD structure adapted to lower parasitic capacitance and parasitic resistance
US6225201B1 (en) * 1998-03-09 2001-05-01 Advanced Micro Devices, Inc. Ultra short transistor channel length dictated by the width of a sidewall spacer
US20020086473A1 (en) * 2001-01-03 2002-07-04 Wen-Jer Tsai Process for fabricating CMOS transistor of IC devices employing double spacers for preventing short-channel effects

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 0092, no. 04 (E - 337) 21 August 1985 (1985-08-21) *

Also Published As

Publication number Publication date
DE10260234A1 (en) 2004-07-15
AU2003289828A1 (en) 2004-07-14
TW200416900A (en) 2004-09-01
TWI264071B (en) 2006-10-11
WO2004057660A2 (en) 2004-07-08
AU2003289828A8 (en) 2004-07-14

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