WO2004051905B1 - Cross-connect switch for synchronous network - Google Patents
Cross-connect switch for synchronous networkInfo
- Publication number
- WO2004051905B1 WO2004051905B1 PCT/US2003/037159 US0337159W WO2004051905B1 WO 2004051905 B1 WO2004051905 B1 WO 2004051905B1 US 0337159 W US0337159 W US 0337159W WO 2004051905 B1 WO2004051905 B1 WO 2004051905B1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- pointer
- input
- output
- cross
- data signal
- Prior art date
Links
- 230000001360 synchronised effect Effects 0.000 title claims abstract 10
- 239000000872 buffer Substances 0.000 claims abstract 21
- 239000003550 marker Substances 0.000 claims 9
- RGNPBRKPHBKNKX-UHFFFAOYSA-N hexaflumuron Chemical compound C1=C(Cl)C(OC(F)(F)C(F)F)=C(Cl)C=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F RGNPBRKPHBKNKX-UHFFFAOYSA-N 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
- H04J3/0623—Synchronous multiplexing systems, e.g. synchronous digital hierarchy/synchronous optical network (SDH/SONET), synchronisation with a pointer process
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
- H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
- H04J2203/0003—Switching fabrics, e.g. transport network, control network
- H04J2203/0005—Switching elements
- H04J2203/0007—Space switch details
Abstract
A cross-connect switch (1000) is adapted for a plurality of input channels in a synchronous network. Each input channel has a pointer processor (800) including a pointer interpreter (802), an elastic store buffer (804), and a pointer generator (806). The cross-connect switch (1000) further comprises a memory-less space switch (1020) interposed between a plurality of pointer interpreters (1010) and a plurality of elastic store buffers (1030). The space switch (1020) switches selected outputs of the plurality of pointer interpreters (1010) to inputs of each elastic store buffer (1000) in response to a switching control signal.
Claims
1. In a cross-connect switch ( 1000) of a synchronous network for a plurality of input channels at a predetermined level of a digital multiplex hierarchy and a plurality of output channels at the predetermined level of the digital multiplex hierarchy, each input channel having a pointer processor (800) including a pointer interpreter (802) coupled to a corresponding input channel, each output channel having an elastic store buffer (804), and a pointer generator (806), wherein the cross-connect switch ( 1000) further comprises: a memory-less space switch ( 1020) inteφosed between a plurality of pointer interpreters (1010) and a plurality of elastic store buffers (1030), the space switch (1020) switching selected outputs of said plurality of pointer interpreters (1010) to inputs of each elastic store buffer (1000) in response to a switching control signal.
2. The cross-connect switch (1000) of claim 1 wherein the memory-less space switch (1020) comprises a plurality of multiplexers (1022, 1024), each multiplexer having data inputs coupled to data outputs of each of said plurality of pointer interpreters (1010), control inputs for receiving a switching control signal, and an output coupled to a corresponding one of a plurality of elastic store buffers (1032, 1034).
3. The cross-connect switch (1000) of claim 1 wherein each of said plurality of pointer interpreters (1012, 1014) has an input for receiving a corresponding input clock signal, a corresponding input pointer, and a corresponding input data signal, and an output for providing a corresponding payload start marker.
4. The cross-connect switch ( 1000) of claim 3 wherein each of said plurality of pointer interpreters (1012, 1014) further provides, for each input channel, an enable signal that is active to indicate when said data signal represents payload data and is inactive to indicate when said input data signal represents
22 overhead, and wherein said elastic buffer portion ( 1030) stores data for each output channel only when a corresponding enable signal selected by said memory-less space switch (1030) is valid.
5. The cross-connect switch ( 1000) of claim 1 wherein each of said plurality of elastic store buffers ( 1032, 1034) has an input coupled to corresponding outputs of said memory-less space switch ( 1020) for storing a selected input data signal in response to an input clock signal, and an output for reading data stored therein at an output clock rate.
6. The cross-connect switch (1000) of claim 1 further comprising a plurality of pointer generators (1042, 1044) each having an input coupled to a corresponding one of said plurality of elastic store buffers (1032, 1034) for receiving an output data signal and a corresponding payload start maker, and an output coupled to a corresponding one of a plurality of output channels for providing said output data signal and said corresponding output pointer at said output clock rate for one of said plurality of output channels.
7. A cross-connect switch (1000) for a synchronous network comprising: a pointer interpreter portion (1010) having inputs coupled to each of a plurality of input channels at a predetermined level of a digital multiplex hierarchy for receiving, for each input channel, an input data signal and an input pointer, and having outputs for providing, for each input channel, a payload start marker that is active when said input data signal represents a start of a payload portion of a frame; a memory-less space switch ( 1020) coupled to said pointer interpreter portion ( 1010), having inputs for receiving said input data signal and said payload start marker of each input channel, and outputs for providing, for each of a plurality of output channels at said predetermined level of said digital multiplex hierarchy, a selected input data signal and a corresponding selected payload start marker from any one of said plurality of input channels in response to a switching control signal; an elastic buffer portion 1 1030) coupled to said memory-less space switch (1020) 
ing inputs for storing data from corresponding outputs of said memory-less space switch ( 1020) at an input clock rate, and outputs for providing an output data signal and a corresponding payload start marker at an output clock rate for each of a plurality of output channels; and a pointer generator portion ( 1040) coupled to said elastic buffer portion (1030) for receiving, for each output channel, said output data signal and said corresponding payload start maker and for providing, for each output channel, said output data signal and a corresponding output pointer indicating an alignment of said output data signal in an output frame.
8. The cross-connect switch (1000) of claim 7 wherein said memory-less space switch (1020) comprises a plurality of multiplexers (1022, 1024) each corresponding to one of said plurality of output channels, each multiplexer having inputs corresponding to each output of said pointer interpreter portion (1010), and outputs, each multiplexer selecting one of said inputs in response to a switching control signal.
9. The cross-connect switch (1000) of claim 7 wherein said pointer interpreter portion (1010) comprises a plurality of pointer interpreters (1012, 1014) each having an input for receiving a corresponding input clock signal, a corresponding input pointer, and a corresponding input data signal, and an output for providing a corresponding payload start marker.
10. The cross-connect switch ( 1000) of claim 9 wherein each of said plurality of pointer interpreters (1012, 1014) further provides, for each input channel, an enable signal that is active to indicate when said data signal represents~payload data and is inactive to indicate when said input data signal represents overhead, and wherein said elastic buffer portion (1030) stores data for each output channel only when a corresponding enable signal selected by said memory-less space switch (1030) is valid.
24 I I . The cross-connect switch ( 1000) of claim 7 wherein said elastic store buffer portion ( 1030) comprises a plurality of elastic store buffers (1032, 1034), each having an input coupled to corresponding outputs of said memory-less space switch (1020) for storing a selected input data signal in response to said input clock signal, and an output for reading data stored therein at said output clock rate.
12. The cross-connect switch (1000) of claim 7 wherein said pointer generator portion (1040) comprises a plurality of pointer generators ( 1042, 1044) each having an input coupled to said elastic store buffer portion ( 1030) for receiving an output data signal and said corresponding payload start maker, and an output coupled to a corresponding one of said plurality of output channels for providing said output data signal and said corresponding output pointer at said output clock rate for one of said plurality of output channels.
13. The cross-connect switch (1000) of claim 7 wherein the synchronous network comprises a SONET network.
14. The cross-connect switch (1000) of claim 13 wherein said pointer within said frame comprises H I and H2 bytes, and said memory-less space switch (1020) switches synchronous transport signal (STS) payloads.
15. The cross-connect switch (1000) of claim 13 wherein said pointer within said frame comprises V I and V2 bytes, and said memory-less space switch (1020) switches virtual tributary (VT) payloads.
16. The cross-connect switch ( 1000) of claim 7 wherein the synchronous network comprises an SDH network.
17. The cross-connect switch ( 1000) of claim 16 wherein said pointer within said frame comprises H I and H2 bytes, and said memory-less space switch (1020) switches synchronous transport module (STM) payloads.
25
18. The cross-connect switch ( 1000) of claim 16 wherein said pointer within said frame comprises VI and V2 bytes, and said memory-less space switch ( 1020) switches tributary unit (TU) payloads.
19. A method for performing cross-connect switching in a synchronous network between a plurality of input channels at a predetermined level of a digital multiplex hierarchy and a plurality of output channels at the predetermined level of the digital multiplex hierarchy network, comprising the steps of: receiving, for each of the plurality of input channels, an input data signal, an input clock signal, and an input pointer indicating a start of a payload portion of a frame; interpreting said pointer of each of the plurality of input channels to provide a pointer start marker that is active when said input data signal represents said start of said payload portion of said frame; space switching said input data signal of each of the plurality of input channels to the plurality of output channels, wherein each of the plurality of output channels transmits a selected data signal, a selected pointer start marker, and a selected clock signal of one of the plurality of input channels selected in response to a switching control signal; translating said selected data signal from an input clock domain based on said input clock signal to an output clock domain based on an output clock signal; and generating a pointer representing a location of said translated data signal in an output frame using said selected pointer start marker.
20. The method of claim 19 further comprising the step of: interpreting said pointer of each of said plurality of input channels to provide an enable signal that is active when said input data signal represents payload data and is inactive when said input data signal represents overhead.
26
21. A cross-connect switch ( 1000) of a synchronous network comprising: a plurality of pointer processors (1010) each including a pointer interpreter coupled to a corresponding input channel at a predetermined level of a digital multiplex hierarchy; a plurality ol elastic store buffers (1030) for each of a plurality of output channels at the predetermined level of the digital multiplex hierarchy; and a memory-less space switch ( 1020) inteφosed between said plurality of pointer processors ( 1010) and said plurality of elastic store buffers ( 1030), the space switch (1020) switching selected outputs of said plurality of pointer processors (1010) to inputs of each elastic store buffer in response to a switching control signal.
22. The cross-connect switch ( 1000) of claim 21 further comprising: a plurality of pointer generators (1040) corresponding to and coupled to said plurality of elastic store buffers (1030) for providing outputs of the cross-connect switch (1000).
23. The cross-connect switch (1000) of claim 21 wherein each said plurality of elastic store buffers (1030) has an input for receiving data using an input clock signal and an output for providing data using output clock signal.
27
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| AU2003294402A AU2003294402A1 (en) | 2002-11-27 | 2003-11-21 | Cross-connect switch for synchronous network |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/306,232 | 2002-11-27 | ||
| US10/306,232 US7177328B2 (en) | 2002-11-27 | 2002-11-27 | Cross-connect switch for synchronous network |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| WO2004051905A2 WO2004051905A2 (en) | 2004-06-17 |
| WO2004051905A3 WO2004051905A3 (en) | 2004-11-25 |
| WO2004051905B1 true WO2004051905B1 (en) | 2005-02-03 |
Family
ID=32325625
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2003/037159 WO2004051905A2 (en) | 2002-11-27 | 2003-11-21 | Cross-connect switch for synchronous network |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US7177328B2 (en) |
| AU (1) | AU2003294402A1 (en) |
| WO (1) | WO2004051905A2 (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IL151796A0 (en) * | 2002-09-18 | 2003-04-10 | Lightscape Networks Ltd | Method for protection of ethernet traffic in optical ring networks |
| US7697445B2 (en) * | 2003-06-05 | 2010-04-13 | Tellabs Operations, Inc. | Autonomous data path verification in multi-module shelf configuration |
| FR2855930B1 (en) * | 2003-06-06 | 2005-08-19 | Eads Telecom | SYNCHRONIZATION AT THE MULTI-FRAME LEVEL OF A MOBILE TERMINAL OF A RADIOCOMMUNICATION SYSTEM |
| US7542484B2 (en) * | 2003-09-30 | 2009-06-02 | Nortel Networks Limited | Managing payload specific latencies in a cross-connect system |
| US7042913B2 (en) * | 2003-09-30 | 2006-05-09 | Nortel Networks Limited | Method and system for writing data to memory elements |
| US7978736B2 (en) * | 2003-09-30 | 2011-07-12 | Ciena Corporation | Efficient provisioning of a VT/TU cross-connect |
| US7246215B2 (en) * | 2003-11-26 | 2007-07-17 | Intel Corporation | Systolic memory arrays |
| US7436824B2 (en) * | 2004-02-17 | 2008-10-14 | Silicon Laboratories Inc. | Distributed switch architecture including a growth input/output bus structure |
| US7639678B2 (en) * | 2004-12-02 | 2009-12-29 | Nortel Networks Limited | Multimodal data switch |
| US8194662B2 (en) * | 2006-06-08 | 2012-06-05 | Ilnickl Slawomir K | Inspection of data |
| US8830993B1 (en) * | 2010-05-27 | 2014-09-09 | Ciena Corporation | Extensible time space switch systems and methods for high capacity multi-service applications |
| US9825883B2 (en) * | 2010-05-27 | 2017-11-21 | Ciena Corporation | Extensible time space switch systems and methods |
| US8717925B2 (en) * | 2011-12-22 | 2014-05-06 | Ixia | Testing TCP connection rate |
| CN114337899B (en) * | 2021-11-30 | 2023-12-19 | 北京恒光信息技术股份有限公司 | Method, device and system for crossing signal time slots based on packet switching |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4998242A (en) | 1988-12-09 | 1991-03-05 | Transwitch Corp. | Virtual tributary cross connect switch and switch network utilizing the same |
| US4967405A (en) * | 1988-12-09 | 1990-10-30 | Transwitch Corporation | System for cross-connecting high speed digital SONET signals |
| US5189410A (en) | 1989-12-28 | 1993-02-23 | Fujitsu Limited | Digital cross connect system |
| JPH03207197A (en) | 1990-01-09 | 1991-09-10 | Fujitsu Ltd | Digital cross-connecting device |
| US5323390A (en) | 1992-10-20 | 1994-06-21 | At&T Bell Laboratories | Multirate, sonet-ready, switching arrangement |
| KR0161759B1 (en) | 1995-12-23 | 1998-12-01 | 양승택 | Cross connecting apparatus of terminal unit |
| US6502197B1 (en) * | 1998-11-23 | 2002-12-31 | Cypress Semiconductor Corp. | Method and architecture for synchronizing a transport and path overhead generator and/or extractor to an path overhead transport and path processor |
| US6317439B1 (en) | 1999-06-03 | 2001-11-13 | Fujitsu Network Communications, Inc. | Architecture for a SONET line unit including optical transceiver, cross-connect and synchronization subsystem |
| US6870831B2 (en) * | 2000-05-04 | 2005-03-22 | Pmc-Sierra, Inc. | Flexible, self-aligning time and space switch fabrics |
| US6631130B1 (en) * | 2000-11-21 | 2003-10-07 | Transwitch Corporation | Method and apparatus for switching ATM, TDM, and packet data through a single communications switch while maintaining TDM timing |
-
2002
- 2002-11-27 US US10/306,232 patent/US7177328B2/en not_active Expired - Lifetime
-
2003
- 2003-11-21 WO PCT/US2003/037159 patent/WO2004051905A2/en not_active Application Discontinuation
- 2003-11-21 AU AU2003294402A patent/AU2003294402A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| AU2003294402A1 (en) | 2004-06-23 |
| US7177328B2 (en) | 2007-02-13 |
| WO2004051905A2 (en) | 2004-06-17 |
| AU2003294402A8 (en) | 2004-06-23 |
| US20040100994A1 (en) | 2004-05-27 |
| WO2004051905A3 (en) | 2004-11-25 |
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