WO2004049339A2

WO2004049339A2 - Sample & hold circuit

Info

Publication number: WO2004049339A2
Application number: PCT/IB2003/005330
Authority: WO
Inventors: Edwin J. Schapendonk
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2002-11-25
Filing date: 2003-11-21
Publication date: 2004-06-10
Also published as: AU2003280128A1; WO2004049339A3; AU2003280128A8

Abstract

A sample & hold circuit comprising a plurality of sample & hold sub-circuits. In order to cope with timing inequalities in the clock-phases that switch the sample & hold sub-circuits, the input signal is applied to the plurality of sub-circuits through a clock-controlled master switch that is open when each of the sub-circuits is switched into its hold mode.

Description

Sample & hold circuit

The invention relates to a sample & hold circuit comprising a plurality of sample & hold sub-circuits each of said sub-circuits having a signal input connected to a common input for receiving a signal to be sampled, a switching input for receiving clock- controlled switch signals for switching the sample & hold subcircuit between a sample mode and a hold mode and a signal output for delivering samples of the input signal during the hold mode.

The invention also relates to an analog-to-digital conversion arrangement comprising a sample & hold circuit for sampling an input signal operatively connected to quantizing means for quantizing samples of the input signal, the sample-and-hold circuit having a plurality of sample-and-hold sub-circuits each sample-and-hold sub-circuit having a signal input connected to a common input for receiving a signal to be sampled, a switch for receiving clock-controlled switch signals for switching the sample-and-hold sub-circuit between a sample mode and a hold mode and a signal output for delivering samples of the input signal to the quantizing means during the hold mode. The invention also relates to a method of sampling an input signal comprising a step of sampling the input signal by means of a sample-and-hold circuit comprising a plurality of sample-and-hold sub-circuits whereby each of the sample-and-hold sub-circuits is connected to a common input where the input signal is received, has a switch to switch the sample-and-hold sub-circuit between a sample mode and a hold mode, and has a signal output for delivering samples of the input signal during the hold mode.

The invention also relates to a method for analog-to-digital conversion comprising a step of sampling an input signal by means of a sample-and-hold circuit followed by a step of quantizing samples of the input signal, whereby a sample-and-hold circuit samples the input signal and quantizing means quantize the samples of the input signal, whereby the sample-and-hold circuit has a plurality of sample-and-hold sub-circuits whereby each sample-and-hold sub-circuit is connected to a common input where the input signal is received, has a switch to switch the sample-and-hold sub-circuit between a sample mode and a hold mode, and has a signal output to deliver samples of the input signal to the quantizing means during the hold mode. Such sample & hold circuit is e.g. known from "A 2.5-N 12-b 54-Msample/s 0.25um CMOS ADC in 1-mm² Mixed-Signal Chopping and Calibration", IEEE J. Solid-State Circuits, vol. 36, pp 1859-1867, December 2001.

Sample & hold circuits comprising a plurality of sample & hold sub-circuits are well known in the art. In such circuits the sample & hold operation is divided over a plurality of sub-circuits, which therefore each have to perform only a part of the task. The main object is that with relatively slow sub-circuits faster sample & hold operations with more samples per second can be executed. For instance from the above mentioned prior art it is known that during the sample period of one of the sub-circuits, another subcircuit operates in the hold mode. It is also possible to evaluate the sample generated by one subcircuit simultaneously with the evaluation of another sample generated by another subcircuit. Another sample & hold circuit with a plurality of sample & hold sub-circuits is disclosed in European patent application EP 1160797. hi this document the sample mode of one of the sample & hold sub-circuits is executed simultaneously with the successive hold modes of the other of the sample & hold sub-circuits.

A problem with the above-defined type of sample & hold circuits is that frequency dependent spurious components appear in the sampled signal. The sub-circuits require perfectly matched different clock phases to switch the respective sub-circuits and the spurious components occur when the clock phases are not sufficiently matched with each other. Another cause is that the input signal arrives at the sub-circuits at different instants. These imperfections in the time matching are hard to avoid because they originate from differences in the layout of the clock lines and of the signal lines to the respective sub- circuits.

The above mentioned European patent application solves this problem by introducing a calibration mode, applying during said calibration mode a well-defined signal to the signal inputs of the sub-circuits, measuring the errors in the outputs of the sub-circuits during said calibration mode and using the measured errors to shift the clock phases so as to reduce the errors. The so measured shift in the clock phase for each individual subcircuit is preserved and subsequently used for the error reduction during the normal sample & hold operation. A drawback of this prior art solution, however, is that it requires quite complex circuitry. Moreover, it requires the introduction of a calibration mode, which, moreover, has to be repeated from time to time in order to cope with the variations in the clock phase shifts originating from temperature variations.

It is an object of the present invention to provide a sample & hold circuit that substantially reduces the spurious signal components with a small and simple circuit and without the necessity of a calibration mode. The sample & hold circuit according to the present invention is therefore characterized in that a clock controlled master switch is connected between the common input and the signal inputs of the plurality of sub-circuits and that said master switch is open when each of the sub-circuits is switched into its hold mode. An analog-to-digital arrangement as described in the opening paragraph is characterized in that a clock controlled master switch is connected between the common input and the signal inputs of the plurality of sub-circuits and that said master switch is open when each of the sub-circuits is switched into its hold mode.

A method of sampling an input signal as described in the opening paragraph is characterized in that a clock controlled master switch connects the common input and the signal inputs of the plurality of sub-circuits and that said master switch is opened when each of the sub-circuits is switched into its hold mode.

A method for analog-to-digital conversion as described in the opening paragraph is characterized in that a clock controlled master switch connects the common input and the signal inputs of the plurality of sub-circuits and that said master switch is opened when each of the sub-circuits is switched into its hold mode.

Further advantages and embodiments of the invention will now be described with reference to the accompanying drawings. Herein: Fig. 1 shows circuit diagram of a prior art sample & hold circuit,

Fig. 2 shows timing diagrams to explain the operation of the prior art sample & hold circuit of Fig. 1,

Fig. 3 shows circuit diagram of a sample & hold circuit according to the invention and Fig. 4 shows timing diagrams to explain the operation of the sample & hold circuit of Fig. 3. The sample & hold circuit of Fig. 1 comprises a plurality of sub-circuits Si ...S_n, each of which has a signal input Ii ...I_n, a switching input ]χ ... J_n and a sample output Oi ...O_n. The signal inputs Ii ...I_n are connected to a common input I for receiving the input signal Nj to be sampled. The sample & hold sub-circuits are well known per se and each of them basically comprises a sampling-switch between the signal input and the sample-output and a hold-capacitance between the sample-output and a reference voltage, in this example ground. The switches of the sample & hold sub-circuits are controlled through the respective switching input Ji ... J_n by clock-phases C_\ ...C_n. These clock phases are generated from a master-clock C_L in a clock-phase generator G. The sample-outputs of the sub-circuits are connected to n-1 sample-handling stages Ν ...N_n through a switch matrix M whose operation will be explained hereafter.

In operation, during a first clock period τ_ls the sample & hold subcircuit Si samples the input signal Vj. During the next clock period τ₂ the signal value, hold in the sample & hold subcircuit Si, is applied by the switch matrix to the sample handling stage N₂ that performs e.g. a course evaluation of the sample for providing the coarse (i.e. most significant) bits of the converted digital signal. During the same clock period τ a new sample of the input signal Vj is taken by the sample & hold subcircuit S₂. During the third clock period τ₃ the signal hold in the sample & hold subcircuit Si is applied, through the switch matrix M to the sample-handling stage N₃, which may be an AD-converter for deriving bits of intermediate significance. In the mean time the sample hold in the sample & hold subcircuit S₂ is applied to the coarse sample-handling stage N₂ and the sample & hold subcircuit S₃ takes a new sample from the input signal Vj. This operation cyclically continues with the further sample-handling stages N ...N_n performing increasingly finer AD- conversion operations. After the last subcircuit S_n has sampled the input signal, the operation continues with the sampling of the input signal by the first subcircuit in a cyclic manner. An important advantage of the arrangement of Fig. 1 is that for the successive operations on one sample the input signal Ni need not to be resampled.

The above-described operation is clarified in the timing diagram of Fig. 2 that shows the n clock phases for switching the n sample & hold sub-circuits. Herein clock-phase Ci switches the subcircuit Si, clock phase C₂ switches the subcircuit S₂ etcetera. This Figure also shows, by shaded areas, the time uncertainties of the edges of the different clock phases. These time uncertainties mainly originate from the asymmetrical circuit layout in the clock- phase generator G and of the connections between the clock-phase generator and the sample & hold sub-circuits Si ...S_n. It will be apparent that these time uncertainties will cause incorrect signal samples and therefore amplitude errors in the digital output of the converter.

To overcome this problem the AD converter of Fig. 3 comprises a master switch P before the circuit i.e. in the input lead that applies the input signal Nj to the plurality of sample & hold subcircuit inputs Ii ...I_n. The master switch P is controlled by the master- clock C . Moreover, the clock-phase generator G is arranged such that the switch P is opened prior to the opening of each of the sampling switches of the sample & hold sub-circuits and closed after the opening of each of these switches. This measure is based on the recognition that the critical moment of a sample & hold circuit is the sampling moment that occurs when the sampling-switch of the sample & hold circuit opens and that, with two switches in series, the switch that opens first defines the sampling moment. Consequently, with the master switch P of Fig. 3, the sampling moment of the input signal is always defined by the same clock signal and mismatches between the clock phases to the individual sub-circuits, are not critical anymore. For the same reason any mismatch in the delay of the input signal to the individual sub-circuits, is also not critical anymore either. Fig. 4 shows the timing diagram of the arrangement of Fig. 3. The vertical dashed lines indicate the new sampling moments, which are now equal for all the sub-circuits.

From the timing diagram of Fig. 4 it may be seen that the master switch P prolongs the time that the sample & hold sub-circuits are in the hold mode and consequently shortens the time that they are in the sample mode. In order to preserve sufficient time for the sampling of the input signal by the sample & hold sub-circuits, it is therefore of importance to keep the time that the master switch P is open, as short as possible. For this reason the time inequalities between the various clock-phases C_\ ...C_n have to be kept as small as reasonably possible. It may be noted that the individual sampling switches in the sub-circuits

Si ...S_n could be considered to be part of the switch matrix M and that, consequently, the sub- circuits Si ...S_n only contain the required hold capacitances. The input signal Nj is then applied, through a stage Νi (not shown), to said sampling switches and the master switch P is included in the stage Νi. It will be apparent that the sampling switches in the matrix M and the hold capacitances in the units Si ...S_n, still together constitute sample & hold sub-circuits in accordance with the scope of the present invention.

Claims

CLA S:

1. A sample & hold circuit comprising a plurality of sample & hold sub-circuits

(Si ...S_n) each of said sub-circuits having a signal input (Ii ...I_n) connected to a common input (I) for receiving a signal to be sampled, a switching input (Ji ... J_n) for receiving clock- controlled switch signals for switching the sample & hold subcircuit between a sample mode and a hold mode and a signal output (O_t ...O_n) for delivering samples of the input signal during the hold mode, characterized in that a clock controlled master switch (P) is connected between the common input (I) and the signal inputs (I_\ ...I_n) of the plurality of sub-circuits and that said master switch (P) is open when each of the sub-circuits is switched into its hold mode.

2. An analog-to-digital conversion arrangement comprising a sample & hold circuit for sampling an input signal operatively connected to quantizing means for quantizing samples of the input signal, the sample-and-hold circuit having a plurality of sample-and- hold sub-circuits each sample-and-hold sub-circuit having a signal input connected to a common input for receiving a signal to be sampled, a switch for receiving clock-controlled switch signals for switching the sample-and-hold sub-circuit between a sample mode and a hold mode and a signal output for delivering samples of the input signal to the quantizing means during the hold mode, characterized in that a clock controlled master switch is connected between the common input and the signal inputs of the plurality of sub-circuits and that said master switch is open when each of the sub-circuits is switched into its hold mode.

3. An analog-to-digital conversion arrangement as claimed in claim 2, characterized in that the quantizing means are arranged for quantizing said samples in a predetermined order.

4. A method of sampling an input signal comprising a step of sampling the input signal by means of a sample-and-hold circuit comprising a plurality of sample-and-hold sub- circuits whereby each of the sample-and-hold sub-circuits is connected to a common input where the input signal is received, has a switch to switch the sample-and-hold sub-circuit between a sample mode and a hold mode, and has a signal output for delivering samples of the input signal during the hold mode, characterized in that a clock controlled master switch connects the common input and the signal inputs of the plurality of sub-circuits and that said master switch is opened when each of the sub-circuits is switched into its hold mode.

5. A method for analog-to-digital conversion comprising a step of sampling an input signal by means of a sample-and-hold circuit followed by a step of quantizing samples of the input signal, whereby a sample-and-hold circuit samples the input signal and quantizing means quantize the samples of the input signal, whereby the sample-and-hold circuit has a plurality of sample-and-hold sub-circuits whereby each sample-and-hold sub- circuit is connected to a common input where the input signal is received, has a switch to switch the sample-and-hold sub-circuit between a sample mode and a hold mode, and has a signal output to deliver samples of the input signal to the quantizing means during the hold mode, characterized in that a clock controlled master switch connects the common input and the signal inputs of the plurality of sub-circuits and that said master switch is opened when each of the sub-circuits is switched into its hold mode.