WO2004040439A3 - Method and apparatus for parallel shift right merge of data - Google Patents

Method and apparatus for parallel shift right merge of data Download PDF

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Publication number
WO2004040439A3
WO2004040439A3 PCT/US2003/033086 US0333086W WO2004040439A3 WO 2004040439 A3 WO2004040439 A3 WO 2004040439A3 US 0333086 W US0333086 W US 0333086W WO 2004040439 A3 WO2004040439 A3 WO 2004040439A3
Authority
WO
WIPO (PCT)
Prior art keywords
data
data elements
parallel shift
shift right
shifted
Prior art date
Application number
PCT/US2003/033086
Other languages
French (fr)
Other versions
WO2004040439A2 (en
Inventor
Julien Sebot
William Macy
Eric Debes
Huy Nguyen
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to AU2003301718A priority Critical patent/AU2003301718A1/en
Publication of WO2004040439A2 publication Critical patent/WO2004040439A2/en
Publication of WO2004040439A3 publication Critical patent/WO2004040439A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G06F17/147—Discrete orthonormal transforms, e.g. discrete cosine transform, discrete sine transform, and variations therefrom, e.g. modified discrete cosine transform, integer transforms approximating the discrete cosine transform
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/15—Correlation function computation including computation of convolution operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G06F9/30014—Arithmetic instructions with variable precision
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30025—Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30109—Register structure having multiple operands in a single register
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30112—Register structure comprising data of variable length
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/3013—Organisation of register space, e.g. banked or distributed register file according to data content, e.g. floating-point registers, address registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units

Abstract

A method for a parallel shift right merge of data. The method of one embodiment comprises receiving a shift count of M. A first operand having a first set of L data elements is shifted left by `L - M' data elements. A second operand having a second set of L data elements is shifted right by M data elements. The shifted first set is merged with the shifted second set to generate a resultant having L data elements.
PCT/US2003/033086 2002-10-25 2003-10-16 Method and apparatus for parallel shift right merge of data WO2004040439A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003301718A AU2003301718A1 (en) 2002-10-25 2003-10-16 Method and apparatus for parallel shift right merge of data

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/280,511 2002-10-25
US10/280,511 US7272622B2 (en) 2001-10-29 2002-10-25 Method and apparatus for parallel shift right merge of data

Publications (2)

Publication Number Publication Date
WO2004040439A2 WO2004040439A2 (en) 2004-05-13
WO2004040439A3 true WO2004040439A3 (en) 2004-12-16

Family

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Family Applications (1)

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Country Status (4)

Country Link
US (1) US7272622B2 (en)
CN (1) CN100338570C (en)
AU (1) AU2003301718A1 (en)
WO (1) WO2004040439A2 (en)

Families Citing this family (82)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7631025B2 (en) * 2001-10-29 2009-12-08 Intel Corporation Method and apparatus for rearranging data between multiple registers
US7818356B2 (en) 2001-10-29 2010-10-19 Intel Corporation Bitstream buffer manipulation with a SIMD merge instruction
US7624138B2 (en) * 2001-10-29 2009-11-24 Intel Corporation Method and apparatus for efficient integer transform
US7685212B2 (en) * 2001-10-29 2010-03-23 Intel Corporation Fast full search motion estimation with SIMD merge instruction
US7725521B2 (en) * 2001-10-29 2010-05-25 Intel Corporation Method and apparatus for computing matrix transformations
US7739319B2 (en) * 2001-10-29 2010-06-15 Intel Corporation Method and apparatus for parallel table lookup using SIMD instructions
US20040054877A1 (en) 2001-10-29 2004-03-18 Macy William W. Method and apparatus for shuffling data
US20050050120A1 (en) * 2003-08-29 2005-03-03 Yang-Ming Shih Method of developing a fast algorithm for double precision shift operation
GB2411976B (en) * 2003-12-09 2006-07-19 Advanced Risc Mach Ltd A data processing apparatus and method for moving data between registers and memory
GB2411978B (en) * 2004-03-10 2007-04-04 Advanced Risc Mach Ltd Inserting bits within a data word
TWI273388B (en) * 2004-06-08 2007-02-11 Mediatek Inc Method and apparatus for processing multiple decomposed data for calculating key equation polynomials in decoding error correction code
US7630585B2 (en) * 2004-06-25 2009-12-08 Intel Corporation Image processing using unaligned memory load instructions
US20060031272A1 (en) * 2004-08-05 2006-02-09 International Business Machines Corporation Alignment shifter supporting multiple precisions
US7590828B2 (en) * 2004-09-08 2009-09-15 Nokia Corporation Processing a data word in a plurality of processing cycles
US20060101105A1 (en) * 2004-11-10 2006-05-11 Roy Glasner Double shift mechanism and methods thereof
US7509602B2 (en) * 2005-06-02 2009-03-24 Eve S.A. Compact processor element for a scalable digital logic verification and emulation system
US8212823B2 (en) 2005-09-28 2012-07-03 Synopsys, Inc. Systems and methods for accelerating sub-pixel interpolation in video processing applications
US9794593B1 (en) * 2005-12-09 2017-10-17 Nvidia Corporation Video decoder architecture for processing out-of-order macro-blocks of a video stream
US20070233767A1 (en) * 2006-03-31 2007-10-04 Jeremy Anderson Rotator/shifter arrangement
US7836134B2 (en) * 2006-06-09 2010-11-16 Sony Ericsson Mobile Communications Ab E-mail address inspection
US7761694B2 (en) * 2006-06-30 2010-07-20 Intel Corporation Execution unit for performing shuffle and other operations
JP4374363B2 (en) * 2006-09-26 2009-12-02 Ｏｋｉセミコンダクタ株式会社 Bit field operation circuit
US7536532B2 (en) 2006-09-27 2009-05-19 International Business Machines Corporation Merge operations of data arrays based on SIMD instructions
JP4686435B2 (en) * 2006-10-27 2011-05-25 株式会社東芝 Arithmetic unit
JP2010515336A (en) * 2006-12-27 2010-05-06 インテル コーポレイション Method and apparatus for decoding and encoding video information
US8041755B2 (en) 2007-06-08 2011-10-18 Apple Inc. Fast static rotator/shifter with non two's complemented decode and fast mask generation
JP5068597B2 (en) * 2007-08-01 2012-11-07 ルネサスエレクトロニクス株式会社 Processor and data reading method by processor
US8078836B2 (en) 2007-12-30 2011-12-13 Intel Corporation Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of per-lane control bits
US7870368B2 (en) * 2008-02-19 2011-01-11 International Business Machines Corporation System and method for prioritizing branch instructions
US8095779B2 (en) * 2008-02-19 2012-01-10 International Business Machines Corporation System and method for optimization within a group priority issue schema for a cascaded pipeline
US7865700B2 (en) * 2008-02-19 2011-01-04 International Business Machines Corporation System and method for prioritizing store instructions
US20090210677A1 (en) * 2008-02-19 2009-08-20 Luick David A System and Method for Optimization Within a Group Priority Issue Schema for a Cascaded Pipeline
US7996654B2 (en) * 2008-02-19 2011-08-09 International Business Machines Corporation System and method for optimization within a group priority issue schema for a cascaded pipeline
US8108654B2 (en) * 2008-02-19 2012-01-31 International Business Machines Corporation System and method for a group priority issue schema for a cascaded pipeline
US7877579B2 (en) * 2008-02-19 2011-01-25 International Business Machines Corporation System and method for prioritizing compare instructions
US20090210672A1 (en) * 2008-02-19 2009-08-20 Luick David A System and Method for Resolving Issue Conflicts of Load Instructions
US20090210669A1 (en) * 2008-02-19 2009-08-20 Luick David A System and Method for Prioritizing Floating-Point Instructions
US7984270B2 (en) * 2008-02-19 2011-07-19 International Business Machines Corporation System and method for prioritizing arithmetic instructions
US7882335B2 (en) * 2008-02-19 2011-02-01 International Business Machines Corporation System and method for the scheduling of load instructions within a group priority issue schema for a cascaded pipeline
US20090210666A1 (en) * 2008-02-19 2009-08-20 Luick David A System and Method for Resolving Issue Conflicts of Load Instructions
US8755515B1 (en) 2008-09-29 2014-06-17 Wai Wu Parallel signal processing system and method
US9785462B2 (en) 2008-12-30 2017-10-10 Intel Corporation Registering a user-handler in hardware for transactional memory event handling
US8627017B2 (en) * 2008-12-30 2014-01-07 Intel Corporation Read and write monitoring attributes in transactional memory (TM) systems
KR101274112B1 (en) * 2009-09-15 2013-06-13 한국전자통신연구원 Video encoding apparatus
US8359433B2 (en) 2010-08-17 2013-01-22 Intel Corporation Method and system of handling non-aligned memory accesses
US9378019B2 (en) 2011-04-07 2016-06-28 Via Technologies, Inc. Conditional load instructions in an out-of-order execution microprocessor
US8880857B2 (en) * 2011-04-07 2014-11-04 Via Technologies, Inc. Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor
US9898291B2 (en) 2011-04-07 2018-02-20 Via Technologies, Inc. Microprocessor with arm and X86 instruction length decoders
US9146742B2 (en) 2011-04-07 2015-09-29 Via Technologies, Inc. Heterogeneous ISA microprocessor that preserves non-ISA-specific configuration state when reset to different ISA
US9292470B2 (en) 2011-04-07 2016-03-22 Via Technologies, Inc. Microprocessor that enables ARM ISA program to access 64-bit general purpose registers written by x86 ISA program
US9176733B2 (en) 2011-04-07 2015-11-03 Via Technologies, Inc. Load multiple and store multiple instructions in a microprocessor that emulates banked registers
US9317288B2 (en) 2011-04-07 2016-04-19 Via Technologies, Inc. Multi-core microprocessor that performs x86 ISA and ARM ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline
US9043580B2 (en) 2011-04-07 2015-05-26 Via Technologies, Inc. Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA)
US9032189B2 (en) 2011-04-07 2015-05-12 Via Technologies, Inc. Efficient conditional ALU instruction in read-port limited register file microprocessor
US9128701B2 (en) 2011-04-07 2015-09-08 Via Technologies, Inc. Generating constant for microinstructions from modified immediate field during instruction translation
US9274795B2 (en) 2011-04-07 2016-03-01 Via Technologies, Inc. Conditional non-branch instruction prediction
US8880851B2 (en) 2011-04-07 2014-11-04 Via Technologies, Inc. Microprocessor that performs X86 ISA and arm ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline
US8924695B2 (en) 2011-04-07 2014-12-30 Via Technologies, Inc. Conditional ALU instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor
US9244686B2 (en) 2011-04-07 2016-01-26 Via Technologies, Inc. Microprocessor that translates conditional load/store instructions into variable number of microinstructions
US9141389B2 (en) 2011-04-07 2015-09-22 Via Technologies, Inc. Heterogeneous ISA microprocessor with shared hardware ISA registers
US9645822B2 (en) 2011-04-07 2017-05-09 Via Technologies, Inc Conditional store instructions in an out-of-order execution microprocessor
US9336180B2 (en) 2011-04-07 2016-05-10 Via Technologies, Inc. Microprocessor that makes 64-bit general purpose registers available in MSR address space while operating in non-64-bit mode
US8972469B2 (en) 2011-06-30 2015-03-03 Apple Inc. Multi-mode combined rotator
CN102388385B (en) * 2011-09-28 2013-08-28 华为技术有限公司 Data processing method and device
US9823928B2 (en) * 2011-09-30 2017-11-21 Qualcomm Incorporated FIFO load instruction
US9292286B2 (en) 2011-10-18 2016-03-22 Panasonic Intellectual Property Management Co., Ltd. Shuffle pattern generating circuit, processor, shuffle pattern generating method, and instruction sequence
CN108681465B (en) * 2011-12-22 2022-08-02 英特尔公司 Processor, processor core and system for generating integer sequence
WO2013095661A1 (en) * 2011-12-23 2013-06-27 Intel Corporation Systems, apparatuses, and methods for performing conversion of a list of index values into a mask value
EP2798429A4 (en) * 2011-12-30 2016-07-27 Intel Corp Reconfigurable device for repositioning data within a data word
US20130235926A1 (en) * 2012-03-07 2013-09-12 Broadcom Corporation Memory efficient video parameter processing
US8767252B2 (en) 2012-06-07 2014-07-01 Xerox Corporation System and method for merged image alignment in raster image data
US9386326B2 (en) 2012-10-05 2016-07-05 Nvidia Corporation Video decoding error concealment techniques
US9442731B2 (en) * 2014-03-13 2016-09-13 Intel Corporation Packed two source inter-element shift merge processors, methods, systems, and instructions
US10013258B2 (en) * 2014-09-29 2018-07-03 International Business Machines Corporation Single instruction array index computation
TWI626498B (en) * 2014-11-10 2018-06-11 友達光電股份有限公司 Display panel
CN104579565A (en) * 2014-12-31 2015-04-29 曙光信息产业(北京)有限公司 Data processing method and device for transmission system
US9996361B2 (en) * 2015-12-23 2018-06-12 Intel Corporation Byte and nibble sort instructions that produce sorted destination register and destination index mapping
CN110770722B (en) * 2017-06-29 2023-08-18 北京清影机器视觉技术有限公司 Two-dimensional data matching method, device and logic circuit
CN108304217B (en) * 2018-03-09 2020-11-03 中国科学院计算技术研究所 Method for converting long bit width operand instruction into short bit width operand instruction
CN111813722B (en) * 2019-04-10 2022-04-15 北京灵汐科技有限公司 Data read-write method and system based on shared memory and readable storage medium
CN110147252A (en) * 2019-04-28 2019-08-20 深兰科技（上海）有限公司 A kind of parallel calculating method and device of convolutional neural networks
WO2021165733A1 (en) * 2020-02-18 2021-08-26 Zeku Inc. Smooth transition for data streams with adjusted gain

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0130380A2 (en) * 1983-06-30 1985-01-09 International Business Machines Corporation Mechanism for implementing one machine cycle executable mask and rotate instructions in a primitive instruction set computing system
EP0363176A2 (en) * 1988-10-07 1990-04-11 International Business Machines Corporation Word organised data processors
US5909572A (en) * 1996-12-02 1999-06-01 Compaq Computer Corp. System and method for conditionally moving an operand from a source register to a destination register
US5933650A (en) * 1997-10-09 1999-08-03 Mips Technologies, Inc. Alignment and ordering of vector elements for single instruction multiple data processing
WO2003038601A1 (en) * 2001-10-29 2003-05-08 Intel Corporation Method and apparatus for parallel shift right merge of data

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5487159A (en) * 1993-12-23 1996-01-23 Unisys Corporation System for processing shift, mask, and merge operations in one instruction
US5781457A (en) * 1994-03-08 1998-07-14 Exponential Technology, Inc. Merge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectored mux on a dual-ALU
US6643765B1 (en) * 1995-08-16 2003-11-04 Microunity Systems Engineering, Inc. Programmable processor with group floating point operations
US6211892B1 (en) * 1998-03-31 2001-04-03 Intel Corporation System and method for performing an intra-add operation
US6115812A (en) * 1998-04-01 2000-09-05 Intel Corporation Method and apparatus for efficient vertical SIMD computations
US6263426B1 (en) * 1998-04-30 2001-07-17 Intel Corporation Conversion from packed floating point data to packed 8-bit integer data in different architectural registers
US6430684B1 (en) * 1999-10-29 2002-08-06 Texas Instruments Incorporated Processor circuits, systems, and methods with efficient granularity shift and/or merge instruction(s)
US6745319B1 (en) * 2000-02-18 2004-06-01 Texas Instruments Incorporated Microprocessor with instructions for shuffling and dealing data
WO2001069938A1 (en) * 2000-03-15 2001-09-20 Digital Accelerator Corporation Coding of digital video with high motion content
KR100446235B1 (en) * 2001-05-07 2004-08-30 엘지전자 주식회사 Merging search method of motion vector using multi-candidates
US7818356B2 (en) * 2001-10-29 2010-10-19 Intel Corporation Bitstream buffer manipulation with a SIMD merge instruction
US7340495B2 (en) * 2001-10-29 2008-03-04 Intel Corporation Superior misaligned memory load and copy using merge hardware
US6914938B2 (en) * 2002-06-18 2005-07-05 Motorola, Inc. Interlaced video motion estimation

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0130380A2 (en) * 1983-06-30 1985-01-09 International Business Machines Corporation Mechanism for implementing one machine cycle executable mask and rotate instructions in a primitive instruction set computing system
EP0363176A2 (en) * 1988-10-07 1990-04-11 International Business Machines Corporation Word organised data processors
US5909572A (en) * 1996-12-02 1999-06-01 Compaq Computer Corp. System and method for conditionally moving an operand from a source register to a destination register
US5933650A (en) * 1997-10-09 1999-08-03 Mips Technologies, Inc. Alignment and ordering of vector elements for single instruction multiple data processing
WO2003038601A1 (en) * 2001-10-29 2003-05-08 Intel Corporation Method and apparatus for parallel shift right merge of data

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US20030131030A1 (en) 2003-07-10
CN1506807A (en) 2004-06-23
WO2004040439A2 (en) 2004-05-13
AU2003301718A1 (en) 2004-05-25
CN100338570C (en) 2007-09-19
US7272622B2 (en) 2007-09-18

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