WO2004036416A1

WO2004036416A1 - Processor having multi-bank register and processor control method

Info

Publication number: WO2004036416A1
Application number: PCT/JP2002/010832
Authority: WO
Inventors: Yuko Matsumoto
Original assignee: Tops Systems Corporation
Priority date: 2002-10-18
Filing date: 2002-10-18
Publication date: 2004-04-29
Also published as: AU2002344110A1; JP3958320B2; JPWO2004036416A1

Abstract

It is possible to handle a plenty of registers without increasing the instruction length and eliminate stalls in the pipeline processing. A processor (100) includes an instruction decoder, a calculation unit (12), memory access means (13, etc.) for inputting/outputting data to/from an external memory (19), a plurality of register banks (11) each having the calculation unit and a register accessible from the memory access means, and bank switch means for controlling which of the register banks is accessed by the calculation unit and which of the register banks is accessed by the memory access means according to a register bank specification control signal from the instruction decoder based on the register bank specification instruction. A multi-processor system using the processor (100) and a method for controlling the processor (100) are also disclosed.

Description

Processor having multi-bank register and method of controlling processor

Technical field

The present invention relates to a computing device for computer equipment such as a CPU (Central Processing Unit) or a D

Details on processor architecture such as SP (Digital Signal Processor)

More particularly, the present invention relates to a microprocessor implementing an instruction set architecture and a control method thereof.

Background art

Processors used in various devices, especially microprocessors, have been improved in arithmetic processing capacity by techniques such as increasing the clock frequency, with the progress of semiconductor fine processing technology in recent years. On the other hand, the transfer speed between the external memory acting as the main storage device and the processor has also been improved by using various technologies, but due to physical limitations such as the number of connection pins and the response speed of the memory, It has not kept pace with processor performance improvements. As a result, the processor consumes an extra number of clocks (usually called latency) when accessing the memory compared to accessing the internal registers. Cache memory is often used in modern processors to bridge this gap in data transfer bandwidth between the processor's internal bus and the bus between memories.

In addition, a multiprocessor system is known as a method of operating a plurality of processors in cooperation with each other to obtain a high arithmetic processing capability. In this multi-processor system, in order to coordinate the operations of the processors, it is necessary to guarantee the coherency (consistency) of the data between the cache memories contained in each processor. When a multiprocessor system is constructed with a plurality of processors each having a cache memory, the coherency is controlled by snubbing (bus snoop) in which the other processors monitor access to the memory of each processor. Methods to guarantee one are known. However, this snubbing has the effect of reducing the data transfer node width of the bus between the processor and the memory. Therefore, even with a multiprocessor system, it is difficult to improve the computational performance of the entire system in proportion to the number of processors used.

In a multiprocessor system, there is a method of guaranteeing data coherency by using a shared memory system in which memory is shared between processors. However, in a shared memory system, the data transfer bandwidth of the bus between the shared memory and the processor is a factor that limits the performance of the multiprocessor system.

As methods for increasing the processing power of a single processor using parallel processing, methods such as a super pipeline, a super scaler, and a VLIW (Very Long Instruction Word) are known. The Super Pipeline @ Superscaler is a method to improve the computational performance by performing parallel processing at the implementation (implementation) level. VLIW is a technique that improves the processing power by performing parallel processing at the instruction level in a processor that has multiple processing units inside. In any parallel processing method, in order to execute programs that are originally executed sequentially in parallel, inevitably dependencies in terms of instructions, operands, and control are inevitable. For example, there is a strong dependency between a load instruction that is a data transfer instruction from a memory to a register and an operation instruction that uses the register as an operand to which the data is loaded. In this load instruction, when there is no data to be loaded into the cache (when a cache miss occurs), access to the external memory is involved. As in this example, the dependencies described above can have significant latencies. In that case, the instruction execution pipeline stalls, and the original operation performance of parallel processing cannot be obtained. There is a problem of getting burned.

In order to solve this problem of parallel processing, dynamic scheduling using a rio-ordering buffer that dynamically schedules instructions to be executed may be used. However, even in this case, the effect is generally limited to the range of 10 instructions. Therefore, if a cache miss occurs, the instruction execution pipeline will not be able to fill the stall and the benefits of parallel processing will not be fully realized. In addition, dynamic scheduling has the problem that the hardware is complicated and the circuit scale becomes enormous. The variables required by the processor to execute the desired software are stored in a register in the processor or in memory on the system. The access to the memory is slower than the access to the registry even if there is a variable for accessing the cache memory, in addition to the cache miss described above.

The number of variables required for one program depends on the program, but is generally several tens to one hundred and several tens. Conventional processors often have eight to thirty-two registers, due to limitations in physical implementation and limitations on instruction length in the instruction set architecture that operates the processor. For example, in the case of a two-operand instruction set architecture using 32 registers and two operation targets, 5 bits are used to specify each register and operand among the bits constituting one instruction. Requires 10 bits. Similarly, in the case of a 3-operand that uses 32 registers and stores the operation result in a register different from the operation target, a total of 15 bits are required to specify the operand. An instruction length is obtained by adding a bit indicating an operation code indicating an operation type or the like to these.

Here, as the instruction length increases, it becomes necessary to increase both the memory size for the program and the bus bandwidth used for executing the program between the memory and the processor. Therefore, in general, from the point of implementation inside the processor, it is effective to shorten the instruction length to improve arithmetic performance. is there.

On the other hand, by increasing the number of registrations, it is possible to reduce access to cache memory and external memory. Further, since the number of load instructions and store instructions for performing an overnight transfer between the external memory and the register can be reduced, the number of program steps is reduced. Thus, increasing the number of registers that can be handled also has the effect of preventing the performance of the computation from deteriorating, but the instruction length increases because the registers are specified.

In the actual processor architecture, the instruction length is appropriately set in consideration of these conflicting relationships and the purpose of use. Typically, the instruction length is set to 16 bits when the number of register evenings is set small, and the instruction length is set to 32 bits when the number of register evenings is set large.

“Register renaming” is also known as a technique for increasing the number of virtual registers without changing the number of registers in the instruction set.

Further, for the purpose of making effective use of a registry evening, for example, Patent Literature 1 discloses a method of switching each registry evening.

Patent Document 1: Japanese Patent Application Laid-Open No. 7-847885 Disclosure of the invention.

Problems the invention is trying to solve

The present invention provides a processor architecture capable of suppressing the occurrence of latency due to memory access while shortening the instruction length as much as possible and improving arithmetic performance when used alone. The task is to solve at least some of the above problems.

In addition to this, the present invention also ensures that the data transfer bandwidth between the processor and the memory can be reduced while guaranteeing memory coherency even in a multiprocessor configuration.

—Processor technology that can prevent degradation due to ping The task is to solve at least some of the above problems by providing chars. Means for solving the problem

In the present invention, the registry in the processor is composed of a plurality of registry banks. The processor architecture is realized by realizing a mechanism in which an arithmetic unit and a memory access device provided in the processor are dynamically connected to the different registry banks. In the present invention, in general, the use of a switch for the register bank and a register for bank designation command such as a register for bank setting or a command for modifying the bank for bank setting are used to provide, for example, 16 bits. With a short instruction length, it is possible to handle many regis- ter evenings.

Specifically, in the present invention, an instruction decoder that decodes an instruction including a register bank designation instruction and a normal instruction to generate a control signal, and performs an arithmetic process based on the control signal from the instruction decoder A computing unit for performing data input / output to / from an external memory based on a signal from the computing unit; and a register accessible from the computing unit and the memory access unit. A bank switch means controlled by a register bank designation control signal generated by the instruction decoder based on the register bank designation command, wherein the arithmetic unit accesses any of the register banks. Puncturing switch means for determining which register bank the memory access means accesses. By controlling the bank switch means, the register assignment bank designation instruction is used to execute a normal instruction after the register sunset puncture designation instruction by using an operand. A processor having a multi-bank register, which is an instruction to switch the evening bank, is provided. The instruction decoder receives a fetched instruction from an instruction storage device provided outside the processor, decodes the instruction, and generates a control signal. The memory access means is a means for providing access to an external memory, and provides access between the memory and the processor by means well known in the art such as an external bus, a cache memory, and an address generator. Any technology that can transfer data can be used. This memory access means provides access between the processor's registry and external memory.

Each Regis evening bank contains a number of Regis evenings organized into appropriate unit banks. Each registry bank is distinguished by a bank identifier that is, for example, an appropriate number of bits. In the present invention, since a processor including a plurality of register banks is used, a bank identifier and a register address are specified to specify an arbitrary register. However, in each instruction executed by this processor, as will be described in detail later, by using a bank setting instruction for switching banks and a bank setting modifying instruction, other instructions (normal instructions) are used. There is no need to specify a bank identifier.

The Registrar Bank Designation Instruction contains some form of bank identifier that explicitly designates the bank. For example, this register designation instruction is an instruction having a bank identifier that designates a bank of a source operand / a destination operand of an instruction having two operands (hereinafter referred to as a “bank setting instruction”). can do. The register evening bank designation instruction does not designate only individual registry evenings, for example, those having a general-purpose registry evening, but registers each operand location such as a source operand used together with an opcode, a destination operand, etc. Bank assignment may be specified. This register setting instruction signal is used as a register setting signal by the instruction decoder to operate the arithmetic unit.

Instructions to be executed by this processor other than the register instruction Does not include the bank identifier. Such instructions are distinguished from the Registrar Bank designation instructions and are referred to as "ordinary instructions." Ordinary instructions can use operands. Basically, the operand of the ordinary instruction executed by this processor is assumed to be assigned the registry bank explicitly specified by the register bank instruction until the instruction is reached. Can be. For example, bank 0 is assigned to the source operand, bank 3 to the destination operand, and so on. For this reason, the instruction length of a normal instruction does not need to be particularly long just because the register bank is used.

The allocation of the register banks is realized by bank switch means. The bank switch means is controlled by a resister bank designation control command based on a resister bank designation command. The bank switch means is, for example, a register for designating a bank of source operands and destination operands used for all subsequent instructions. This specification may be changed for each operand, or may be the same. The operation of the bank switch means when the register bank designation instruction is not explicitly included can be based on an appropriate default value. The register bank designation instruction is not limited to the instruction that designates the register bank in subroutine units.

As in the present invention, when a plurality of register banks are used by switching with additional instructions as needed, a large number of register banks are used while keeping the instruction length used for ordinary instructions short. be able to. Since a large number of registry keys can be used in this way, it is possible to reduce the frequency of memory access using locality of data, as has been done with cache memory. In addition, the transfer bandwidth can be larger in the case of the registry than in the case of the cache memory. The more regis- ters are used, the faster the operation that uses more cache memory becomes.

In the present invention, the bank switch means controls the register bank designation. Two

8 to determine whether the arithmetic unit accesses any of the register banks and to determine whether the memory access means accesses any of the other register banks. Simultaneous access to the registry by the arithmetic unit and access to the registry by the memory access means can be enabled.

With this configuration, it is possible to connect a register bank different from a register bank connected to the arithmetic unit to the memory access device. With this configuration, data transfer between the memory and the register by the operation instruction and the memory access instruction can be performed in parallel. The processor reads data from the memory for another registry bank while processing an operation using a registry bank in one registry bank, or reads data from a memory in the registry bank where the calculation results are stored. The process of storing in a memory can be explicitly performed by software. As a result, with a simple hardware configuration, it is possible to easily suppress a decrease in the processing performance of the processor due to the pipeline stall caused by the data dependency between the executed instruction and the operation instruction. Note that the memory access means can provide access between the external memory and the register based on an instruction from the instruction decoder.

In the processor according to the present invention, the register bank setting instruction is a register bank setting modifying instruction, and the register bank setting modifying instruction is controlled by controlling the bank switch means. In order to execute the ordinary instruction immediately following the operand using the operand, the instruction may be a bank instruction that switches a register bank to be assigned to a register for the operand of the ordinary instruction immediately after the instruction.

In this case, the register bank to be assigned to the register for the operand of only the instruction immediately following the register bank setting modifier instruction is switched. In other words, a register setting modifier instruction is a modifier that affects only the immediately following instruction. This is an instruction for designating a registry bank having an effect. This Registrar evening bank setting modifier command is also called the Registrar evening bank setting prefix. The register bank setting modifier instruction makes it possible to specify the register bank flexibly in a program, and to secure the flexibility of programming while reducing the instruction length.

In the present invention, when the register setting instruction is immediately before, the instruction length is extended from the instruction length of the normal instruction, and the register setting instruction and the normal instruction immediately after the instruction are extended. One instruction having the specified instruction length can be obtained. Here, when the register setting instruction is a register setting modifying instruction, the register setting instruction and the normal instruction are combined to form one unit of the instruction. Registrar bank setting qualification instructions alone are not a unit. The reason is that the register setting modifier instruction modifies the register setting for the operand of the next ordinary instruction, and is not an executable instruction by itself.

Extending the instruction length means that the operation of the instruction immediately following the register setting instruction can be recognized as an executable instruction that can be executed by modifying it according to the register setting instruction. To construct an instruction set architecture, or to construct a decoder that can decode such an instruction set architecture, rather than merely formally changing the delimiter between instructions. Nor does it correspond directly to putting assembler code on one line.

In these processors of the present invention, the register bank setting instruction is a register bank setting instruction. In a normal instruction subsequent to the register bank setting instruction, it is not necessary to explicitly specify the register bank. The assignment of the register bank based on the register bank designation instruction can be applied to the register bank used by the operand. Regis Evening Bank Setting Instruction, Regis Evening A type of bank specification instruction that specifies the bank assignment of operands in a subsequent normal instruction. In the normal instructions that follow, the Registrar Bank assigned by the Registrar Bank Set instruction is used without specifying the Registrar Bank.

When such a register bank setting instruction is used, the instruction length of a normal instruction is set to a short instruction length similar to that of a processor architecture in which the register bank is not configured as a register bank, and the register bank is set as required. Configuration instructions can be used. This makes it possible to handle a large number of registers while keeping the average instruction length of the entire program composed of multiple instructions short.

According to another aspect of the present invention, there is provided a multiprocessor system including at least an instruction storage unit, a first processor, a second processor, and an external memory, wherein the first processor An instruction decoder that decodes an instruction including a register bank designation instruction from the instruction storage means and an ordinary instruction to generate a control signal; and the control signal from the instruction decoder. An arithmetic unit for performing an arithmetic process based on the data, a memory access unit for performing input / output with the external memory based on a signal from the arithmetic unit, and accessible from the arithmetic unit and the memory access unit A plurality of register banks each including a register bank; and a register bank specifying control signal generated by the instruction decoder based on the register bank specifying instruction. Bank switch means to be controlled, the bank switch means determining which register bank the arithmetic unit accesses, and the bank switch means determining which register bank the memory access means accesses. The register bank designation instruction is used by the operand to control the bank switch means to execute a normal instruction following the register bank designation instruction by using an operand. An instruction for switching a register bank to be assigned to the register, wherein the external memory includes the memory access unit of the first processor and the memory access unit of the second processor. A multiprocessor system is provided that is connected to and accessible from any of the above.

This external memory is accessed from at least two processors included in the multiprocessor system. This makes it possible to realize, for example, a multiprocessor system having an SMP (Symmetrical Multiprocessor) configuration, and a multiprocessor configuration in which the CPU and DSP cores are linked. This feature makes it possible to use a registry bank for each processor in a multiprocessor system. A large number of local registers can make up for the gap in data transfer bandwidth due to the bus between the processor and the memory. In addition, since the registers in each bank can be observed and controlled from software, there is no problem with coherency. Thus, the data transfer bandwidth of the bus between the processor and the memory is not lost due to snubbing. For this reason, it is possible to improve the arithmetic performance by increasing the number of processors in the SMP configuration, and to enhance the capability of cooperative processing between the DSP and the CPU incorporating a specific-purpose signal processing arithmetic circuit.

In such a multiprocessor system, the bank switch means is controlled by the register bank designation control signal, and determines whether the arithmetic unit accesses any of the register banks, and the memory access means is It is determined whether any of the other registry banks is to be accessed, and simultaneous access of the arithmetic unit to the registry bank and access to the register bank by the memory access means is possible. can do. When simultaneous access is used, not only does the processing capability of each processor constituting a multiprocessor system improve, but it often causes a problem when performing arithmetic processing by linking multiple processors. The number of installed stalls is reduced.

The present invention provides such a multiprocessor system, wherein the external memory T JP2002 / 010832

At least part of the memory area accessed by the first processor and the memory area accessed by the second processor may be shared.

Even in the case of using a so-called shared memory, increasing the number of registrations is required between the processor and the memory with the same effect as data caching using locality of data. Data transfer can be reduced. As a result, even when the shared memory is used in the multiprocessor system, the operation performance is improved as compared with the case where the memory bank is not used.

According to another aspect of the present invention, there is provided an instruction decoder for generating a control signal by decoding an instruction including a register bank designation instruction and a normal instruction, and performing arithmetic processing based on the control signal from the instruction decoder. An arithmetic unit, a memory access unit for performing data input / output with an external memory based on a signal from the arithmetic unit, and a register accessible from the arithmetic unit and the memory access unit. A method of controlling a port processor comprising a plurality of register banks and bank switch means for determining which register bank the arithmetic unit and the memory access means respectively access, wherein the instruction decoder comprises: Generating a register bank designation control signal based on the register bank designation command; By controlling the switch means, the register bank assigned to the register used by the operand of the normal instruction after the register bank designation instruction is switched, so that the arithmetic unit accesses any register bank. Controlling the bank switch means by the register bank designation control signal, thereby switching the register bank to be allocated to the register used by the operand, and A method of controlling a processor having a multi-bank register, comprising the steps of: controlling whether to access a memory; and executing the normal instruction using an operand. The processor of the present invention switches the registry bank to be accessed by the arithmetic unit and the memory access means according to the register bank designation control signal, and executes the instruction. In order to appropriately perform this, a control method including the above steps can be performed. As a result, the register puncture assigned to the register of the operand of the subsequent instruction is determined, so that such a control method can handle a large number of registers while keeping the instruction length short.

The above steps need not always be performed in this order. The program can be executed in various orders as a result of the arrangement of the instructions. Also, some steps may be performed simultaneously, and the frequency of execution of each step may be significantly different.

In this control method, the step of executing the normal instruction using an operand includes accessing the register of a certain register bank by the arithmetic unit and the memory accessing means of a register of another register bank. And a step in which access by and is performed simultaneously.

When the arithmetic unit accesses a certain registry bank, the memory access means can access another registry bank. Both of these accesses are included in the instruction execution step. The range of the execution steps can be defined by time, for example, from the first clock to the last clock required to execute a normal instruction in units of a clock at which the processor operates. In this range, the arithmetic unit and the memory access means can access the registers used by each of the separate register banks in parallel. In the conventional processor, it was necessary to use a multi-port register file in order for the arithmetic unit to access the register and the memory in parallel. However, by dividing the registry window, which is a feature of the present invention, into banks, it is possible to access in parallel in this way using a normal registry file. This increases memory access latency. Other operations can be performed even during the time when the execution of the instruction is temporarily stopped, thereby improving the operation processing capability. In addition, the frequency and time of stalls in pipeline processing are reduced.

In the processor control method according to the present invention, the register bank setting instruction is a register bank setting modifying instruction, and the register bank setting modifying instruction is controlled by controlling the bank switch means. In order to execute the normal instruction immediately after the setting modification instruction using the operand, the instruction may be a switch that switches a register bank assigned to the operand register of the operand of the normal instruction immediately following the normal instruction. it can.

The Registrar bank setting modifier instruction is the above-described instruction for designating the Registrar bank which has a modifying effect which affects only the immediately following instruction. Also in the processor control method, the register bank setting modifier instruction enables the register bank to be specified flexibly in the program, and the degree of freedom in programming can be secured while suppressing the instruction length.

In the control method of the processor according to the present invention, the instruction length is extended from the instruction length of a normal instruction when the register setting instruction is immediately before, and the instruction setting is immediately followed by the normal instruction immediately after the register setting instruction. May be one instruction having the extended instruction length.

In this control method, the register bank designation instruction is a register bank setting instruction, and a normal instruction subsequent to the register bank designation instruction does not require explicit designation of the register bank designation instruction. In addition, a control method is provided in which the assignment of the registry bank based on the register puncture designation instruction is applied to the registry used by the operand.

By having a register bank designation instruction, it is possible to maintain a short instruction length without including a bank identifier in ordinary instructions. By matching the register length instruction to this instruction length, the maximum instruction length of the entire architecture can be kept short and many Will be able to handle the Regis evening.

As another mode, the control method of the processor of the present invention can be a control method having a conditional execution switching modifier instruction for controlling an operation of whether or not to execute a later instruction depending on a determination condition.

This conditional execution switching modifier instruction may be called a conditional execution prefix. The conditional execution switching qualification instruction is a qualification instruction (prefix) that can switch whether or not to execute a subsequent instruction according to the judgment condition without a branch instruction. The use of this qualifying instruction can reduce the number of branches in the program itself, and has the effect of avoiding stalls caused by branch instructions during parallel processing.

Further, the control method of the processor of the present invention can be a control method using a register bank designation instruction and the conditional execution switching modification instruction.

When the conditional execution prefix is used in combination with the register designation instruction of the present invention, it is possible to write a program that can be processed in parallel with almost no stall, so that the instruction speed can be reduced while suppressing the instruction length. However, a fast processor can be realized.

Furthermore, in the control method according to the present invention, the register instruction specifying the register bank and the instruction for conditional execution switching are decoded by a prefix decoder that prefetches the instruction executed by the instruction decoder, and the prefix decoupling is performed based on the instruction. In accordance with the instruction decoder control signal generated by the instruction decoder, the decoding operation of the instruction decoder can be changed. Each qualifying instruction by itself does not constitute an instruction that the instruction decoder recognizes as an instruction. If the modified instruction read ahead is combined with the instruction immediately following the qualifying instruction to execute the instruction execution step as one instruction, the intended operation can be performed without increasing the execution steps of the instruction. This operation can be performed properly by using a prefix decoder that prefetches instructions. Note that the expression “simultaneous” is used throughout the present application, but this is substantially the same in a step consisting of a unit of time by a clock pulse generally used in the computer field, and a step composed of several clocks. This means that two or more events have occurred or overlapped within the range that can be said. Even if it is performed at a shifted timing, the two events of interest are performed by the next clock pulse.The two events of interest occur and end between the start and end of a certain step. , And that there is an overlap in the periods of the events. In these senses, if both events are considered to be substantially simultaneous, they shall be considered "simultaneously." BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a configuration diagram schematically showing a processor according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing assembler code including a bank designation instruction according to the embodiment of the present invention. '

FIG. 3 is an explanatory diagram showing how banks are switched by the assembler code of FIG.

FIG. 4 is an explanatory diagram showing an example of realizing a bank designation instruction according to the embodiment of the present invention.

FIG. 5 is a functional block diagram showing the configuration of the instruction fetch stage in the example of the processor configuration according to the embodiment of the present invention.

FIG. 6 is a functional block level configuration diagram showing the configuration of an instruction decode stage and an instruction execution stage in a processor configuration example according to an embodiment of the present invention.

FIG. 7 is a configuration diagram of a function block level showing a configuration of a write-back stage in a processor configuration example according to an embodiment of the present invention.

FIG. 8 shows a bank switch in a processor configuration example according to an embodiment of the present invention. FIG. 4 is a configuration diagram of a function block level showing a configuration of a switch unit. BEST MODE FOR CARRYING OUT THE INVENTION

[Embodiment of the architecture]

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an outline of the processor of the present invention. In the present invention, the registers used by the arithmetic unit are grouped into a plurality of units called, for example, n register banks from bank 0 to bank n-1. The bank identifier is used to specify which of these Regis evening banks. The bank identifier is a number having an appropriate number of bits, for example, having a sufficient number of bits to represent n. To specify an arbitrary register in the processor, specify a bank identifier and a register address.

The operation unit performs an operation based on the instruction decoded by an instruction decoder (not shown). This instruction roughly includes two types of instructions. The first type of instruction is an instruction similar to an instruction in a normal processor. For example, there are instructions well-known in the processor field, such as a load instruction for loading data from an external memory (a moniker: L D), an addition for performing an addition (A D D), and a subtraction (S U B). This instruction is referred to herein as a "normal instruction".

The second type of instruction is an instruction for switching the register bank to be accessed. These are instructions unique to the present invention, and are called "registration bank designation instructions". With this instruction, it is possible to determine which register bank the arithmetic unit accesses based on the subsequent normal instruction. For example, when the architecture of the processor uses two operands, it is possible to independently specify which register accesses the first operand and the second operand. The format of the Registrar Bank designation instruction for switching the Registrar Bank is not particularly limited. Through 10832

18 Normal stored-program instructions include, for example, an instruction that has an explicit bank identifier as an operand (bank setting instruction) and a prefix that switches the bank indicated by the operand of the immediately following instruction (bank setting modifier instruction). It can also be.

Figure 2 shows an example of an instruction in this assembler code for bank switching. Line 202 is one of bank setting instructions, and is a bank set instruction (21st moniker: B S) for specifying a bank to be used in a program thereafter. The first and second operands B0 and B1 of this bank set instruction represent Bank 0 and Bank 1, respectively. In other words, line 202 is an instruction that sets the first operand (destination operand) to “bank 0” and sets the second operand (source operand) to “bank 1” in the subsequent program. . As described above, the bank set instruction exemplified in the row 202 is an instruction constituted by the operation code corresponding to the two-monitor BS and the operand. The bank setting instruction represented by the bank setting instruction allocates a register bank until the next bank setting instruction is explicitly specified. In addition, what kind of register bank is set in the instruction line until the bank setting instruction explicitly appears in the program is arbitrary. The bank may not accept such an instruction because the bank is indefinite, assign a certain default value to the bank (for example, all banks are set to 0), perform processing on all the banks in parallel, , And the destination and source operands can be assigned separately.

Line 204 in FIG. 2 is a bank setting prefix (mnemonic: BP) that is valid only for the immediately following instruction. The bank setting prefix in this example includes the bank identifier in the opcode itself, not as an operand. The bank setting prefix "BP10" affects only the instruction immediately following it (line 206) and places the destination operand in bank 1, This instruction sets the source operand to bank 0. That is, assuming that i and j are subscripts representing the bank identifier, “BP ij” sets the destination operand of the following instruction to punk i and the source operand to bank j. Of course, like the bank set instruction described above, an operation code and an operand indicating a bank identifier may be used, and may affect only the immediately following instruction line. Since this bank setting prefix affects only the immediately following instruction, it temporarily only overwrites the bank assignment specified by the bank setting instruction described above. In the instruction line where the link setting prefix has no effect (line 2◦8), the specification of the bank specification instruction becomes valid again.

For the bank setting instruction, prepare a register called the bank select register (not shown) that holds the current bank setting, and use B0 and B1 as those registers. Can be. The value of the bank select register can be referred to by specifying the program with an explicit instruction. The contents of the backselect registry may be shared as global variables between subroutines, for example, in a program having a subroutine configuration, or may be rewritten as a local variable for each subroutine. If it is a local variable, it can be written out and held in any general-purpose register or external memory configured in the memory bank by an appropriate data transfer instruction. In the architecture of the present invention, instructions for realizing this transfer can be included.

FIG. 3 schematically shows the operation of the register bank designation instruction in the program shown in FIG. The instruction in line 206 (ADD) is affected by the bank setting prefix BP10 in the previous line 204; therefore, R1 in bank 1 is used as the source operand, and the bank is used as the destination operand. Using R 21 in 0, write the result of the sum of R 1 and R 21 back to R 21. The instruction in line 208 (SUB) is, as specified by the bank setting instruction in line 202, Using R 2 in bank 0 as the source operand and R 19 in bank 1 as the destination operand, subtract 1 19 from 112 and write the result back to R 19. Row 208 is not affected by the bank setting prefix of row 204. Note that in FIG. 3, the “source register bank” and “destination register bank” indicating the source operand are separately shown on the left and right sides of the figure for understanding, but the register bank having the same register identifier is shown. May point to the same registry bank.

As described above, it is possible to switch the bank pointed by the source operand to the destination operand with a small number of instructions in an arbitrary program composed of a sequence of instructions using the bank designation instruction. In addition, by using a bank setting prefix that is valid only for the immediately following instruction, it is possible to switch banks flexibly.

Also, the case where the operands are two 2-operand instructions is taken as an example, but when there is only one operand, only the destination operand can be used. In addition, a bank setting instruction and a bank setting prefix can be similarly defined even in a three-operand architecture using three operands.

The banks that can be switched in this way can be accessed from the arithmetic unit shown in Fig. 1 by switching the banks to be accessed. The external memory is a data transfer device 13 that is a memory access means, an internal bus 14, and an external bus 1. 5 can be accessed. The operation of the data transfer device 13 can be changed by a control signal based on a command.

Next, the instruction length of the present invention will be described. Hereinafter, the 16 bits may be particularly referred to as one word.

FIG. 4 shows the instruction configuration of the present invention in a bit array. The normal instruction 402 in FIG. 4 is, for example, an instruction such as addition (ADD) or subtraction (SUB) described in FIG. This is a normal instruction described earlier as the first type of instruction, and corresponds to row 208 in FIG. For example, the instruction 412 is composed of an 8-bit operation code and two operands of four bits each, and has an instruction length of 16 bits.

The instruction with a bank setting modifier 404 in FIG. 4 includes a puncture setting prefix 414 as a bank setting modifier instruction and an instruction 415 following the puncture setting prefix. Instructions 4 15 are normal instructions. In FIG. 2, the instruction with a bank setting modification 404 is represented by two lines, a row 204 and a row 206. The instruction length is 16 bits for both the bank setting prefix 414 and the instruction 415. The instruction 404 with the bank setting modification is 32 bits (2 words) as a whole. Based on this instruction with bank setting modification 404, a bank designation instruction is issued by the instruction decoder. The bank setting instruction 406 in FIG. 4 is, for example, a 16-bit bank setting instruction 416, and corresponds to the row 202 in FIG. For example, like a normal instruction, it contains a 4-bit bank setting instruction opcode and two 6-bit bank identifier operands. Based on the bank setting instruction 406, a bank designation instruction is issued by the instruction decoder.

The setting of the instruction length of the bank setting instruction and the bank setting modification instruction as described above is particularly suitable when the majority of the operations that do not require the bank specification instruction. In other words, when a bank designation instruction is issued, the instruction length is increased to 2 words, etc., and usually a short instruction such as 1 word (16 bits) is executed. The instruction length can be shortened in cases other than the case where As a result, it is possible to handle a large number of registers while reducing the program code and the area for implementing the processor.

It should be noted that there is no particular limitation on what kind of bank allocation should be performed when an instruction is executed before a bank setting instruction explicitly appears. Banks may not accept such orders as indeterminate, nor may default banks For example, it is possible to assign all the banks 0 using the link assignment, to process all the banks in parallel, to assign the destination operand and the source operand separately.

The present invention is not limited to the above one-word and two-word instructions. For example, the maximum instruction length can be three words. In this case, the second word can be a bank setting prefix and the third word can be a normal instruction, but the first word can be another prefix. The prefix can be, for example, a conditional ediction prefix. The conditional execution prefix is a prefix that does not involve a branch instruction and can switch whether or not to execute a subsequent instruction according to a determination condition. This prefix alone has the effect of reducing branch instructions and avoiding stalls caused by branch instructions during parallel processing. When the conditional execution prefix is used in combination with the register designation command of the present invention, it is possible to write a program that can be processed in parallel with almost no stalls. In addition, it is possible to realize a port processor with a high processing speed. Note that if the maximum instruction length is 2 or 3 words and the last word is a register setting prefix, it is recognized as a general illegal instruction and will not be processed.

As described above, according to the present invention, while keeping the instruction length of the entire program short, a long instruction length can be assigned only to the instruction related to the register designation instruction to handle many registers.

[Processor configuration example]

5 to 8 show configuration examples 101 of a processor that implements the architecture of the present invention. FIG. 5 shows the instruction fetch stage, FIG. 6 shows the instruction decode stage and the instruction execution stage, and FIG. 7 shows the write back stage and the memory access stage included therein. I have.

The instruction fetch stage of FIG. 5 includes an instruction fetch buffer 54 from an instruction storage means (not shown), an instruction fetch unit 52 for loading instructions, and a program counter 5 for counting the number of programs to be executed. And a fetch address unit 56 for generating an address for accessing the instruction storage means based on the value of 8.

The instruction decode stage in FIG. 6 includes a main decoder 62 that decodes an instruction loaded as an instruction fetch buffer 54 into microcode (microinstruction) that is a control signal, and a prefix for the main decoder 62. And a prefix decoder 60 that decodes and outputs the same. In this configuration example, each instruction having an instruction length of 16 bits is sent to the decoder in 96-bit units. When the main decoder is decoding an instruction, the instruction following the instruction is decoded by the prefix decoder 60. That is, the prefix decoder 60 pre-reads the instruction in advance, so that the prefix decoder 60 detects whether the instruction includes the prefix. When the prefix decoder 60 detects the prefix, it outputs a control signal to the main decoder 62 according to the content of the prefix. With this control signal, the main decoder 60 switches the decoding operation for the instruction after the prefix. As described above, the prefix decoder and the main decoder cooperate to implement the prefix operation. If the prefix is the bank setting prefix of the present invention, the main decoder 62 switches the register bank used for the operand included in the instruction to be decoded immediately thereafter. As a result, the registry that holds the bank allocation of the registry file (bank select registry 66, Fig. 8) is changed. This register is the bank switch means of the present invention. As described above, by using the bank setting prefix, the register bank to which the operand of the following instruction is pointed is switched. In other words, the prefix decoder and the main decoder can generate a MIC instruction which becomes a bank designation instruction.

When a bank setting instruction such as a bank set instruction is used instead of the bank setting prefix, the main decoder decodes the bank setting instruction, rewrites the bank select register, and changes the bank assignment of the register file. As a result, the register bank indicated by the destination operand and the source operand in the subsequent instruction is switched.

The instruction decode stage further includes a register file 64 containing a plurality of register banks of the present invention. In the present embodiment, the registry evening bank is described as a nighttime processing registry evening arranged in four banks. Each register bank has 16 data register banks each having a length of 64 bits that can be specified in a 6-bit field in a normal instruction.

The instruction decode stage includes the bank select register 66 as described above (Fig. 8). The bank select register holds the status of the current bank allocation by, for example, a bank set instruction.

The instruction execution stage includes a microcode (microinstruction) control unit 610 that specifically executes the instruction decoded in the instruction decode stage, an arithmetic logic unit (ALU), and a multiply-accumulate operation unit (MAU). ) And a data processing unit (DPU). Arithmetic unit 68 executes an arithmetic process specified for the immediate value, the register evening value in any of the register evening banks, etc., based on the micro instruction, and transfers the result to the write-back stage. The instruction decode stage and the instruction execution stage further include the characteristic elements of the present invention. The output from the register file is the source register SRC 0 and SRC 1 and the destination registers DST 0 and DST 1 which are part of the signal 601. Of these ports, the ports of the registry file connected to the registers SRC0 and DST0 are used by ordinary processors. It is connected to the computing unit via the registers SRC0 and DST0. On the other hand, the port of the registry file connected to the registry SRC 1 and DST 1 is a characteristic port of the present invention, and is connected to an external memory (not shown) via the registry SRC 1 and DST 1. Is connected to the store instruction execution device 620 which outputs the data. In the present configuration example, two registrations of SRC 1 and DST 1 are described, but the present invention only needs to have at least one such registration. The store instruction execution device 620 forms a part of the memory access device of the present invention in cooperation with a memory output device 74 (FIG. 7) described later. As a result, the arithmetic unit accesses some register banks of the register file having the register bank configuration via the register SRC0 and DST0, and at the same time, accesses the register banks of the other sections. On the other hand, external memory can be accessed via the registers SR C1 and DST 1. In the above description, the processor configuration using the microinstruction has been described. However, a hardwired configuration can also be realized.

The write-back stage shown in Fig. 7 has a write-back device 72 that writes the output of the arithmetic unit 68 back to the registry file, and writes the output of the arithmetic unit 68 to an external memory (not shown) as data. It has a memory output device 74 including a driver, and a memory input device 76 for reading data from the external memory and loading it into the registry file 64. At this time, since the banks are different, the memory input device 76 can write data to the register file 64 in parallel with the write-back stage. '

FIG. 8 shows an example of the configuration of the bank switch means not shown in FIGS. 5 to 7 but used in the processor of the present invention. The bank switch means in this configuration example includes a bank select register 66 and a register SRCB (84) which holds the register puncture assigned to the source operand register included in the SSR (system status register) 82. ) And the destination operand register And a Registrar DSTB (86) that holds the Registrar Bank assigned to the Scanner. The bank select register 66 is a register that holds the registers that are assigned to the source and destination operands in the instruction decode stage. ID.SRCB (84a) and ID.DSTB (86a) Consists of

First, the operation of these bank switch means when the bank designation instruction is a bank setting instruction will be described. The register ID.SRCB (84a) and ID.DSTB (86a) that can be directly rewritten from the main decoder 62 can be rewritten without going through the instruction execution stage. Therefore, they hold the latest register bank and are used for register and read. The same registry bank assignments are subsequently written to SRCB (84) and DSTB (86) in SSR 82 in the control registry file. With this operation, at the end of the instruction decode stage, the assignment of the register bank included in the instruction is already reflected, so the register bank can be allocated in a short time, for example, one clock. This register assignment is also valid for the immediately following instruction, and it is possible to determine which registry evening punk register in the registry evening file 64 to access for each source operand and destination operand. . This is also written to SSR82 in the registry file at the end of the write-back stage, so that the registry bank allocation as the system status can be retained.

Next, a case will be described in which the bank specification instruction is a bank setting modification instruction and is combined with the immediately following ordinary instruction to form one instruction. In this case, it is not necessary to write the temporary assignment of the register bank to the SSR 82 'because the bank setting modification instruction only affects the instruction immediately following it. Therefore, the bank select register 66 is rewritten in the instruction decode stage. 2002/010832

There is no mention of the 27 command execution stage or the writeback stage. In this way, a temporary bank assignment that is valid only for the normal instruction immediately after the bank setting modification instruction is realized.

With the configuration of the processor as described above, it is possible to use the registry bank configured as the registry bank of the present invention. In other words, a processor capable of implementing a register evening switch operation by a register evening bank setting instruction and an operation of switching an operand point destination register of a subsequent instruction by a register evening bank setting prefix is provided as specific hardware. . In addition, the external memory can be accessed even during the arithmetic operation of the arithmetic unit, and the stagnation of the processing due to the latency of the memory can be prevented.

Although not shown in the figure, a known cache memory can be used for the memory output device 74 and the memory input device 76 to reduce the latency caused by the external memory. A multi-processor configuration can be realized using a plurality of single processors described with reference to FIGS. At this time, the individual processors to be cooperated are connected to the instruction storage means. The instruction storage means stores instructions for cooperating the respective multiprocessors. Each processor fetches only the instructions required by each processor at the fetch stage according to the program count of each processor. The instructions of each processor may be the same as those used in the single processor of the present invention, such as a register bank setting instruction or a register bank bank multi-decorative instruction.

Also, the external memory may be accessed by several processors. In other words, the external memory can be configured as a shared memory system, and a certain data area in the external memory can be shared by a plurality of processors so that the processors can share a register. In this configuration, the external memory with high latency For example, the registry evening of each processor is assigned to a separate registry evening bank, a registry evening sharing values with other processors (hereinafter referred to as a “shared registry evening”) and a registry evening used only by each processor. be able to. For example, each processor accesses the register bank including the shared register as a destination operand or a source operand only when performing an operation on the shared register, and accesses the other register banks in other operations, for example. I do. Then, the shared memory is accessed only when the shared registry is rewritten. When the processors constituting the multiprocessor operate as described above, only the rewriting result of the register to be shared by the processors is accessed via the shared memory having a large latency. Then, even during the access to the shared memory, the arithmetic unit of each processor can execute an instruction that does not handle the shared register. As described above, in the multiprocessor system according to the present invention including a plurality of processors, while ensuring data coherency, the multiprocessor system in which operations in each processor are not easily affected by latency due to external memory access. System is realized. Industrial potential

With the processor configuration of the present invention, many registers can be used while keeping the instruction length short. In addition, it is possible to prevent stagnation of processing due to memory latency.

In the multiprocessor system including a plurality of processors according to the present invention, it is possible to realize a multiprocessor system in which operations in each processor are hardly affected by latency due to external memory access while guaranteeing data coherency.

Claims

The scope of the claims

1. an instruction decoder for decoding an instruction including a register instruction and a normal instruction to generate a control signal;

An arithmetic unit that performs arithmetic processing based on the control signal from the instruction decoder; a memory access unit that performs data input / output with an external memory based on the signal of the arithmetic unit;

A plurality of register banks each provided with a register accessible from the arithmetic unit and the memory access means;

Bank switch means controlled by a register bank designation control signal generated by the instruction decoder based on the register bank designation command, wherein the arithmetic unit determines which register bank to access, and Bank switch means for determining which register bank the memory access means accesses.

The register setting command is executed by controlling the bank switch means to execute a normal instruction following the register setting instruction using an operand. A processor with a multi-bank register, which is an instruction to switch banks.

2. The bank switch means is controlled by the register bank designation control signal, determines whether the arithmetic unit accesses one of the register banks, and sets the memory access means to any one of the other registers. It decides whether to access Evening Bank,

2. The processor according to claim 1, wherein access to the register by the arithmetic unit and access to the register by the memory access unit can be performed simultaneously.

3. The register setting command is a register setting command, and the register setting command is for controlling the bank switch means. The instruction for switching the register bank assigned to the register for the operand of the normal instruction immediately following the ordinary instruction immediately following the register setting instruction for the operand using the operand. The processor according to claim 1 or 2, wherein

4. If the register setting instruction is immediately before, the instruction length is extended from the instruction length of the normal instruction, and the register setting modifying instruction and the immediately following normal instruction are extended. The processor according to claim 3, wherein the processor has one instruction length. ·

5. The register bank setting instruction is a register bank setting instruction. In a normal instruction subsequent to the register bank setting instruction, the operand does not need to be explicitly specified and the operand is set. 3. The processor according to claim 1 or 2, wherein the allocation of a registry bank based on the registry bank designation instruction is applied to a registry bank to be used.

6. A multiprocessor system comprising at least an instruction storage means, a first processor, a second processor, and an external memory,

The first processor and the second processor include:

An instruction decoder for decoding an instruction including a register instruction from the instruction storage means and an instruction including a normal instruction to generate a control signal;

An arithmetic unit for performing arithmetic processing based on the control signal from the instruction decoder; memory access means for performing input / output with the external memory based on a signal from the arithmetic unit;

Bank switch means controlled by a register / bank designation control signal generated by the instruction decoder based on the register / bank designation instruction, wherein the arithmetic unit determines which register / bank to access, and Memory access hand Bank switching means for determining which registry bank the dan will access,

By controlling the bank switch means, the register bank designation instruction is used to execute a normal instruction subsequent to the register bank designation instruction using an operand. Command to switch between

The multiprocessor system, wherein the external memory is connected so as to be accessible from both the memory access unit of the first processor and the memory access unit of the second processor.

7. The bank switch means is controlled by the register bank designation control signal, and determines whether the arithmetic unit accesses one of the register banks, and the memory access means determines whether to access any of the other banks. Determines whether to access the Regis Evening Bank,

7. The multiprocessor system according to claim 6, wherein an access to the register by the arithmetic unit and an access to the register by the memory access unit can be performed simultaneously.

8. The multiprocessor system according to claim 6, wherein the external memory has a memory area accessed by the first processor and a memory area accessed by the second processor. A multiprocessor system in which at least part of is shared.

9. An instruction decoder for decoding an instruction including a register instruction and a normal instruction to generate a control signal, and an operation for performing an arithmetic operation based on the control signal from the instruction decoder Unit, memory access means for inputting / outputting data to / from an external memory based on a signal from the arithmetic unit, and a plurality of registers each including registers accessible from the arithmetic unit and the memory access means A bank, and the arithmetic unit and the memory access means are accessed by each of the registry banks. A processor control method comprising: a bank switch means for determining whether to perform

A step in which the instruction decoder generates a register setting control signal based on the register setting instruction;

By controlling the bank switch means with the register bank designation control signal, the register bank assigned to the register bank used by the operand of the normal instruction after the register bank designation instruction is switched, and Controlling whether to access the registry bank;

By controlling the bank switch means with the register setting signal, the register bank assigned to the register used by the operand is switched to control which register bank the memory access means accesses. Steps

Executing the normal instruction using the operands;

A method of controlling a processor having a multi-bank register including the following.

1 0. The step of executing the normal instruction using an operand includes:

10. The method according to claim 9, further comprising the step of simultaneously performing access by a computing unit to a registry evening of a certain registry evening bank and access by a memory access unit to a registry evening of another registry evening bank. A method for controlling a processor having the multi-bank credit card described in the above.

11. The register bank designating instruction is a register bank setting modifying instruction, and the register bank setting modifying instruction is provided immediately after the register bank setting modifying instruction by controlling the bank switch means. 10. The instruction according to claim 9, wherein the instruction for switching the register bank assigned to the register of the operand of the operand of the ordinary instruction immediately after the instruction is executed in order to execute the instruction using the operand. 10. The method for controlling a processor according to item 10.

1 2. If the register bank setting modifier instruction is immediately before, the instruction length is usually 11. The instruction according to claim 11, wherein the instruction length of the register instruction is extended from the instruction length of the instruction, and the register instruction for setting the register bank and the ordinary instruction immediately after become one instruction having the extended instruction length. How to control the processor.

1 3. The 3rd Registrar Bank Designating Instruction is a Registrar Evening Bank Setting Instruction, and the normal instruction after the above Registrar Evening Bank Specifying Instruction does not require explicit designation of the Registrar Evening Bank, 10. The processor control method according to claim 9, wherein the register bank assignment based on the register bank designation instruction is applied to a register bank used by the operand.