WO2004021159A1

WO2004021159A1 - A wireless communication host controller interface device

Info

Publication number: WO2004021159A1
Application number: PCT/SG2002/000197
Authority: WO
Inventors: Kiong Hua Chua; Guopei Qiao
Original assignee: Laboratories For Information Technology
Priority date: 2002-08-30
Filing date: 2002-08-30
Publication date: 2004-03-11
Also published as: AU2002330833A1

Abstract

A host controller interface device (19) for interfacing a wireless communication device (18) with a host (80) is described. The host controller interface device (19) comprises a parallel peripheral interface for providing parallel data transfer from and to the host (80), a serial peripheral interface for providing serial data transfer from and to the host (80), a peripheral interface selector for selecting one of the parallel and serial peripheral interfaces; a host interface for providing data transfer from and to the wireless communication device (18), a data stream transformer for performing at least one of parallel-to-serial and serial-to-parallel data stream transformation when the data stream type of the selected one of the parallel and serial peripheral interfaces is dissimilar with the data stream type of the host interface; and a transfer protocol transformer for performing transformation of the transfer protocol of the selected one of the parallel and serial peripheral interfaces to the transfer protocol of the host interface.

Description

A WIRELESS COMMUNICATION HOST CONTROLLER INTERFACE DEVICE

FIELD OF INVENTION

The invention relates generally to wireless communication devices. In particular, the invention relates to a wireless communication host controller interface device for portable devices having interfaces incompatible with wireless communication devices facilitating wireless communication.

BACKGROUND There has been a substantial growth in the market for portable devices such as Moving Picture Experts Group-I Audio Layer III (MP3) players, digital cameras, personal digital assistants (PDAs) and smart phones. At the same time, the demand for portable memory has resulted in the emergence of various proprietaiy storage technologies, namely Compact Flash, Smartmedia, Multimediacard, Memory Stick and Secure Digital.

Flash memory cards based on Compact Flash, Smartmedia, Multimediacard, Memory Stick and Secure Digital technologies are typically used in various portable devices for peripheral storage purposes. For example, Compact Flash, Smartmedia and Multimediacard cards are usually used for digital cameras, MP3 players and PDAs. Memory Stick card interfaces are mostly provided in Sony Corporation's hand-held products. Secure Digital, a recent storage format that complies with a new standard for protecting sensitive data and multimedia properties, is typically implemented in PDAs and audio players for receiving the respective flash memory card.

As a result of miniaturisation, a portable device usually provides or supports a single interface compatible only with the respective flash memory card used for that portable device. The choice of flash memory card and hence specificity of interface provided for the flash memory card is therefore dependent on the manufacturer of the portable device. Bluetooth technology is among the fastest growing wireless communication technologies in the market, and is a radio solution characterised by small form-factor, low cost and low power intended for replacing cables interconnecting electronic devices. Bluetooth, a term herein generally referring to Bluetooth technology or Bluetooth related devices, can support peer-to-peer connections as well as provide wireless access for Local Area Networks (LANs), mobile phone networks and the Internet. Bluetooth uses Frequency Hopping Spread Spectrum (FHSS) technology and operates in the license-free 2.4GHz Industry Scientific and Medical (ISM) band at a range of 10 meters. With improved transmission power and sensitivity the range is extendable up to 100 meters.

There is a growing number of Bluetooth peripheral devices providing Bluetooth wireless access in the market, including Personal Computer Memory Card Interface Adapter (PCMCIA) cards, Compact Flash cards, and Universal Serial Bus (USB) and RS232 dongles. Portable devices, as host systems, connected to or interfaced with these Bluetooth peripheral devices are thereby enabled with Bluetooth communication capabilities. To this end, a number of semiconductor chip manufacturers produce and sell Bluetooth semiconductor chips to facilitate Bluetooth integration into Bluetooth peripheral devices. However, many of such Bluetooth semiconductor chips provide only host interfaces based on Universal Asynchronous Receiver Transmitter (UART) or USB ports, both of which are generally intended for facilitating communication with host systems such as PCs and notebooks. Since there is an increasing demand to incorporate Bluetooth communication capabilities into existing and new portable devices while in most cases these portable devices do not have the appropriate host interfaces, interfacing Bluetooth peripheral devices with such portable devices is therefore a problem.

Figure 1 is a block diagram illustrating the functional modules of a conventional Bluetooth semiconductor chip 1 which provides a host interface based on UART or USB. The Bluetooth semiconductor chip 1 generally consists of functional modules such as a Radio Frequency (RF) module 2, a Baseband processing (BB) module 3, and a Micro-controller (uC) module 4 for providing Bluetooth communication to a host system 5. As shown in Figure 1, the host system 5 is required to communicate via a conventional UART- or USB-based host interface 6 with the Bluetooth semiconductor chip 1. However, most existing portable devices do not support any type of card interface for providing connectivity via UART or USB. These portable devices usually provide one of the five flash memory card interfaces, namely Compact Flash, Smartmedia, Multimediacard, Memory Stick or Secure Digital.

A conventional Bluetooth peripheral device implemented using the Bluetooth semiconductor chip of Figure 1 is described in detail with reference to Figure 2, in which the hardware components of the conventional Bluetooth peripheral device are shown using a block diagram. Specifically, the hardware components consist of a Radio 12, a Link Controller 13, a CPU Core (Link Manager) 14 and a Host Interface module 15 based on USB or UART. The Link Controller 13, the CPU Core 14, and the Host Interface module 15 form a conventional Bluetooth Host Controller 16.

The Radio 12 operates in the 2.4GHz ISM band and typically consists of an antenna interface, amplifiers, digital phase lock loop (PLL) synthesizer, and modulation and demodulation circuitry (all not shown).

The Link Controller 13 executes baseband protocols and other low-level routines. The Link Controller 3 performs forward error correction (FEC) encoding and decoding, data whitening (scrambling), header error check (HEC), encryption and decryption, cyclic redundancy check (CRC) and audio coding.

The CPU Core 14 implements a Link Manager Protocol (LMP) which handles low-level control functions such as link set-up between devices, control and negotiation of packet sizes, management of power modes, and the generation, exchange and control of encryption keys. From a study of conventional Bluetooth semiconductor chips it is observed that a substantial number of such semiconductor chips provide a UART or USB interface for communicating with a host system through a conventional Bluetooth host controller. Therefore if the host system has a UART or USB port, it is easy to enable the host system with Bluetooth wireless access. If the host system has other types of ports, however, then the host system cannot be easily enabled with Bluetooth wireless access.

There is therefore a need to address the foregoing problem of interfacing Bluetooth or the like wireless communication products with host systems incompatible with interfaces of such products for providing Bluetooth or the like wireless communication.

SUMMARY

For providing Bluetooth or the like wireless communication to a host system such as a portable device without a UART or USB interface, an interface device or the like glue logic is provided and disclosed hereinafter for interfacing a conventional Bluetooth semiconductor chip having a UART or USB interface and the host system. An example of this glue logic is a Field Programmable Gate Array (FPGA) device implemented as a host controller interface device. Such an FPGA device is preferably implemented to support multiple card interfaces and is therefore appropriate for enabling existing portable devices with Bluetooth.

Preferably, the host controller interface device as glue logic is configured and disposed between the host controller of the conventional Bluetooth semiconductor chip and the card interface of the host system, in which the conventional Bluetooth semiconductor chip and the host controller interface form a Bluetooth peripheral device for enabling the host system with Bluetooth.

Since various different card interfaces can be found in portable devices, it is also advantageous to support multiple card interfaces for allowing easy incorporation of Bluetooth into the various portable devices. The host controller interface device is therefore preferably implemented to support different card interfaces.

The host controller interface device is preferably implemented using the FPGA device. Although the FPGA device can be designed to implement either a USB or UART host interface, the UART host interface is preferably implemented because it is simple and requires minimal resources. Furthermore, a number of conventional Bluetooth semiconductor chips include UART host interfaces that can transfer data at a rate of up to 1.5Mbps. Therefore, it is further preferred that the host controller interface device have high performance and be capable of supporting data at a transfer rate of 1.5Mbps to ensure that maximum system performance of the conventional Bluetooth semiconductor chip is achieved.

Therefore in accordance with a first aspect of the invention, a host controller interface device for interfacing a wireless communication device with a host is described. The host controller interface device comprises a parallel peripheral interface for providing parallel data transfer from and to the host; a serial peripheral interface for providing serial data transfer from and to the host; a peripheral interface selector for selecting one of the parallel and serial peripheral interfaces; a host interface for providing data transfer from and to the wireless communication device; a data stream transformer for performing at least one of parallel-to-serial and serial-to-parallel data stream transformation when the data stream type of the selected one of the parallel and serial peripheral interfaces is dissimilar with the data stream type of the host interface; and a transfer protocol transformer for performing transformation of the transfer protocol of the selected one of the parallel and serial peripheral interfaces to the transfer protocol of the host interface.

BRIEF DESCRIPTION OF DRAWINGS

Embodiments of the invention are described hereinafter with reference to the drawings, in which:

Figure 1 is a block diagram illustrating the functional modules of a conventional Bluetooth semiconductor chip interfaced with a host system;

Figure 2 is a block diagram illustrating the hardware components of a Bluetooth peripheral device implemented using the conventional Bluetooth semiconductor chip of Figure 1;

Figure 3 is a block diagram illustrating the functional modules of a Bluetooth Host Controller Interface Device according to a preferred embodiment of the invention for providing an interface between a conventional Bluetooth semiconductor chip and a host system;

Figure 4 is a block diagram illustrating the components of the Bluetooth Host Controller Interface Device of Figure 3;

Figure 5 is a block diagram of a mode selector in the Bluetooth Host Controller Interface Device of Figure 3;

Figure 6 is a block diagram illustrating the components of a UART Core in the Bluetooth Host Controller Interface Device of Figure 3;

Figure 7 is a block diagram illustrating the internal architecture of the UART Core of Figure 6;

Figure 8 is a block diagram of a data converter in the Bluetooth Host Controller Interface Device of Figure 3; Table 1 shows the pin assignments of a connector for a Compact Flash card interface in the Bluetooth Host Controller Interface Device of Figure 3;

Table 2 shows the pin descriptions of a connector for a Secure Digital card interface in the Bluetooth Host Controller Interface Device of Figure 3;

Table 3 shows the pin descriptions of a connector for a Memory Stick card interface in the Bluetooth Host Controller Interface Device of Figure 3; and

Table 4 shows the logic levels used to determine the card interface type in the Bluetooth Host Controller Interface Device of Figure 3.

DETAILED DESCRIPTION

Embodiments of the invention are described hereinafter which address the foregoing problem of interfacing Bluetooth or the like wireless communication devices with host systems incompatible with interfaces of such devices for providing Bluetooth or the like wireless communication through a peripheral device.

Figure 3 shows a conventional Bluetooth semiconductor chip 18 which through a Bluetooth Host Controller Interface Device 19 is interfaced with a Host 80. The Bluetooth semiconductor chip 18 is connected to the Bluetooth Host Controller Interface Device 19 using a UART interface or the like host interface typically provided by the conventional

Bluetooth semiconductor chip 18 for forming a Bluetooth peripheral device for the Host

80. The Host 80 is connected to the Bluetooth Host Controller Interface Device 19 via a Compact Flash, Smartmedia, Multimediacard, Memory Stick or Secure Digital card interface. The Bluetooth Host Controller Interface Device 19 essentially performs interface transformation of the host interface and the card interface according to an embodiment of the invention so that the Bluetooth semiconductor chip 18 is interfaced with the Host 80 for incorporating Bluetooth into the Host 80. The host interface is an interface between the Bluetooth semiconductor chip 18 and the Bluetooth Host Controller Interface Device 19 and the card interface is an interface between the Bluetooth Host Controller Interface Device 19 and the Host 80.

With reference to Figure 4, the architecture of the Bluetooth Host Controller Interface Device 19 according to a preferred embodiment is described in detail.

The Bluetooth Host Controller Interface Device 19 is preferably^' implemented using a FPGA device which consists of a number of modules. The Bluetooth Host Controller Interface Device 19 supports three types of card interfaces, namely Compact Flash (CF) 20, Secure Digital (SD) 23 and Memory Stick (MS) 25 card interfaces. The Compact Flash 20, Secure Digital 23 and Memory Stick 25 card interfaces are implemented because these three types of flash memory card interfaces can support expansion features in addition to the original memory storage feature of the Host 80. Expansion features include input-output (I O) devices such as a voice, data and fax modem, a network interface card and a wireless communication device such as the Bluetooth peripheral device. Other card interfaces such as Smartmedia and Multimediacard card interfaces are not implemented in the preferred embodiment because Smartmedia and Multimediacard cards are used only as memory storage cards and do not provide I/O support in accordance with the respective specification. However, further implementation of Bluetooth into Smartmedia and Multimediacard cards according to alternative embodiments of the invention is possible if the Host 80 supports the I/O feature in relation to Smartmedia and Multimediacard card interfaces, respectively. One way is to use a memory-mapped I/O technique to map the I/O address into the Host 80 memory space.

The various modules of the Bluetooth Host Controller Interface Device 19 include a CF Interface and Control module 30, a Mode Select module 50, a Data Converter 40, and an Internal UART Core 60. The Bluetooth Host Controller Interface Device 19 also includes an Internal Data/Control Bus 45 which provides internal data and control communication between all these modules therefore interconnecting all these modules. The Bluetooth Host Controller Interface Device 19 further includes the Compact Flash (CF) card interface 20, the Secure Digital card interface 23, and the Memory Stick card interface 25 for providing the respective card interfaces with the Host 80.

The Compact Flash (CF) card interface 20 requires a 50-pin connector (not shown) and can support data transfer in either the 8-bit or 16-bit parallel data transfer format. Since the Bluetooth Host Controller Interface Device 19 provides a dedicated UART interface, the data transfer format chosen is the 8-bit parallel data transfer format. Table 1 shows the pin assignments of the connector for the Compact Flash card interface 20. When the Compact Flash card interface 20 is selected, the Data Converter 40 is disabled and the Host 80 is connected directly to the CF Interface and Control module 30. The CF Interface and Control module 30 contains a set of registers to allow the Host 80 to configure a Bluetooth Compact Flash card embodying the Bluetooth semiconductor chip 18 and Bluetooth Host Controller Interface Device 19 to access the Internal UART Core 60. The CF Interface and Control module 30 also performs all address and select decoding functions and allows information exchange between the Host 80 and the Internal UART Core 60 through the Internal Data/Control Bus 45.

The Secure Digital card interface 23 requires a 9-ρin connector (not shown) and the pin descriptions of the connector for the Secure Digital card interface 23 are shown in Table 2. When the Secure Digital card interface 23 is used,- serial data transfer is performed through a single data I/O pin. When the Secure Digital card interface 23 is selected and a Secure Digital card embodying the Bluetooth semiconductor chip 18 and Bluetooth Host Controller Interface Device 19 is inserted into and detected by the Host 80, the Data Converter 40 is enabled and performs serial-to-parallel conversion of data from the Host 80.

The Memory Stick card interface 25 requires a 10-pin serial data transfer connector (not shown). The pin descriptions of the connector for the Memory Stick card interface 25 are shown in Table 3. When the Memory Stick card interface 25 is selected, the Data Converter 40 is enabled and performs serial-to-parallel conversion of data from the Host 80.

The Mode Select module 50 is used to determine the type of card interface to be used for interfacing the Bluetooth Host Controller Interface Device 19 with the Host 80. The Mode Select module 50 is configured through two external pins MIO[l :0] 55. A user may select the card interface type to use by setting the logic levels on the two pins MIO[l :0] 55. The selection method is described in detail hereinafter.

The Data Converter 40 is used to perform serial-to-parallel conversion of data from the Host 80 through either the Secure Digital card interface 23 or the Memory Stick card interface 25, as well as parallel-to-serial conversion of data from the Internal UART Core 60. The data transfer between the Host 80 and the Data Converter 40 occurs in serial format, while the data transfer between the Internal UART Core 60 and the Data Converter 40 occurs in parallel format. The Data Converter 40 allows the Host 80 comiected to the Bluetooth Host Controller Interface Device 19 either via the Secure Digital card interface 23 or the Memory Stick card interface 25 to access and communicate with the Internal UART Core 60 through the Internal Data/Control Bus 45.

The Internal UART Core 60 is interfaced to an External Bluetooth UART module 88, which is the Host Interface module of the Bluetooth semiconductor chip 18, to perform serial communication. The Internal UART Core 60 uses four signals 85, namely RTS (Request-to-Send), RXD (Receive Data), CTS (Clear-to-Send), and TXD (Transmit Data) signals to communicate with the External Bluetooth UART module 88. Preferably, the Internal UART Core 60 is made up of a transmit section, a receive section, a baud rate generator and a bus interface.

The Internal Data/Control Bus 45 is the information exchange channel between the individual modules. For example, the Host 80 through the Data Converter 40 can communicate with the Internal UART Core 60 by sending data across the Internal Data/Control Bus 45.

Selection of Card Interface Type The selection of the card interface type is done by the user through two external pins MIO[1:0] 55 of the Mode Select module 50 as shown in Figure 5. The logic levels on these two pins determine the type of card interface to use for connecting the Bluetooth Host Controller Interface Device 19 with the Host 80. The Mode Select module 50 interprets the input from the two external pins MIO[1:0] 55 and activates an active-low signal (0) on one of three chip enable signals (#CE0, #CE1, #CE2). The two pins MIO[1:0] 55 allow four possible signals or logic states to be selected (Low-Low, Low- High, High-Low, and High-High) but since only three card interfaces are available, one of the logic states (High-High) is unused. This selection method allows only one card interface to be supported at any time. Table 4 shows the logic levels used to determine the card interface type.

Internal UART Core

UART is widely used in serial communication and uses asynchronous transmission. Asynchronous transmission allows data to be transmitted without a sender having to send a clock signal to a receiver. Instead, the sender and the receiver agree on the timing parameters in advance and special bits such as 'Start Bit' and 'Stop Bit' are added to synchronize the sending and receiving units.

The Internal UART Core 60 is preferably a high performance UART module that provides data transfer rates of at least 921 Kbps by using larger transmitter and receiver First-In- First-Out registers (FIFOs). Larger FIFOs reduce Central Processing Unit (CPU) or processing overhead and allow utilisation of higher data transfer rates. The higher data transfer rate requirement is necessary to ensure that Bluetooth communication is performed at the maximum data transfer rate. Figure 6 illustrates a block diagram of the Internal UART Core 60, in which the Internal UART Core 60 provides serial-to-parallel conversion of data characters received from the Bluetooth UART 88 and parallel-to-serial conversion of data characters received from the Host 80. Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmitted data to form a data character. Data integrity is ensured by adding a parity bit to each data character for control and monitoring. The parity bit is checked by the receiver for any transmission bit errors.

As shown in Figure 6, the Internal UART core 60 consists of a Transmit Block, a Receive Block, and Internal Control and Status Registers 77. Additionally, the Internal UART core 60 includes a Clock and Baud Rate Generator 76 and the Internal Data/Control Bus 45.

The Transmit Block consists generally of a Transmitter Shift Register 62, a Transmitter FIFO 61 and Transmitter Control Logic module (not shown). The Internal Data/Control Bus 45 reads parallel data from the Host 80 and writes the data directly in the Transmitter FIFO 61. The data in the Transmitter FIFO 61 is immediately transferred into the Transmitter Shift Register 62 where it is shifted out in serial form. The Transmitter Control Logic module provides the timing for the desired baud rate and the flow of the data.

The Receive Block consists generally of a Receiver Shift Register 65, a Receiver FIFO 67 and Receiver Control Logic module (not shown). The Receiver Shift Register 65 receives serial data and transfers the data directly to the Receiver FIFO 67. The Host 80 reads the data in parallel from the Receiver FIFO 67 through the Internal Data/Control Bus 45.

The Clock and Baud Rate Generator 76 is programmable and is capable of dividing the timing reference clock input and producing different baud rates according to the user's requirement. Figure 7 is a block diagram illustrating the internal architecture of the Internal UART Core 60. The Internal UART Core 60 specifically includes a Transmitter Buffer section, which forms the Transmit Block, a Receiver Buffer section, which forms the Receive Block, and the Internal Control & Status Registers 77 consisting of a Line Control Register 68, a Line Status Register 69, a Modem Control Register 70, a Modem Status Register 71, a Modem Control Logic 71a, a FIFO Control Register 64, an Interrupt Enable Register 73, and an Interrupt Identification Register 72. The Transmitter Buffer section, the Receiver Buffer section, Transmitter Internal Control & Status Registers 77 are described in detail hereinafter with reference to Figure 7.

The communication between the Host 80 and the Internal UART Core 60 is controlled using the Internal Control & Status Registers 77 that can be read or written to for changing and controlling UART interface operations, including transmission and reception of data. Each register is preferably 8 bits wide.

Transmitter Buffer Section

The Transmitter Buffer section includes a Transmitter Holding Register (THR) 61 and a Transmitter Shift Register (TSR) 62. Parallel data from the Internal Data/Control Bus 45 is first fed to the THR 61 and the contents in the THR 61 are transferred to the TSR 62 once the TSR 62 is empty. The TSR 62 is controlled by a TX Timing and Control 75 that receives a clock input from the Baud Rate Generator 76. The contents in the TSR 62 are shifted out, via a serial TXD signal, at a rate determined by the TX Timing and Control 75.

A TX FIFO 63 can be selected and set so that more data characters are stored in the TX FIFO 63 and can be transferred out when the Host 80 receives a TX interrupt signal.

Receiver Buffer Section

The Receiver Buffer section includes a Receiver Holding Register (RHR) 67 and a Receiver Shift Register (RSR) 65. Serial data via a serial RXD signal is received by the RSR 65, which is controlled by an RX Timing and Control 74. As the RSR 65 is filled, the contents in the RSR 65 are transferred to the RHR 67. The Host 80 can read parallel data from the RHR 67.

A RX FIFO 66 can be selected and set so that the RX FIFO 66 continues to receive data until the number of bytes is equal to the FIFO level selected. Once the Host 80 receives an RX interrupt signal, the Host 80 reads and empties the RX FIFO 66.

Line Control Register The Line Control Register (LCR) 68 is used to specify the data communication format such as parity bit, stop bits and word length.

Line Status Register

The Line Status Register (LSR) 69 provides information on the status of the data transfers between the Internal UART Core 60 and the Host 80. The Line Status Register 69 includes line status such as Data Ready, Overrun Error, Parity Error and^'Framing Error.

Modem Control Register

The Modem Control Register (MCR) 70 controls the interface lines with the External Bluetooth UART module 88.

Modem Status Register

The Modem Status Register (MSR) 71 provides the current status of the modem control lines between the External Bluetooth UART module 88 and the Host 80.

Modem Control Logic

The Modem Control Logic 71a consists of buffers and control logic for processing the modem control lines CTS and RTS. The Host 80 sets bits in the MCR 70 whenever it wishes to transmit data to the External Bluetooth UART module 88. The Modem Control Logic 71a reads these bits in the MCR 70 and performs handshaking with the External Bluetooth UART module 88 via the RTS line. The Modem Control Logic 71a monitors changes in the CTS line and sets corresponding bits in the MSR 71 from which the Host 80 reads for determining when to transmit data.

FIFO Control Register

The FIFO Control Register (FCR) 64 is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels and select the type of Direct Memory Access (DMA) mode.

Interrupt Enable Register

The Interrupt Enable Register (IER) 73 selects from various interrupts available in the Interrupt Identification Register (IIR) 72. Each interrupt can individually activate an internal interrupt signal to the Host 80.

Interrupt Identification Register

The Intermpt Identification Register (IIR) 72 provides the source of interrupt from four levels of prioritised intermpt conditions in order to minimize the Host 80 overhead during data transfers.

The single baud rate Baud Rate Generator 76 produces the bit clocks, which are used for serial transmission. To optimise the performance of the Bluetooth Host Controller Interface Device 19, a data rate of up to 1.5 Mbps is supported.

Internal Data/Control Bus The Intemal Data/Control Bus 45 provides a communication channel between the various modules in the Bluetooth Host Controller Interface Device 19. The Internal Data/Control Bus 45 allows data transfers over an 8-bit bi-directional parallel data bus. The Host 80 communicates with the Internal UART Core 60 by sending data and control signal through the Intemal Data/Control Bus 45. Data Converter

Figure 8 is a block diagram of the Data Converter 40. The Data Converter 40 contains a Controller 41 that is programmed to read and write to input-output (I/O) pins of the connector for either the Secure Digital card interface 23 or the Memory Stick card interface 25 and the Internal Data/Control Bus 45 that is connected to the Internal UART Core 60.

The Controller 41 first needs to determine which card interface to support by sensing the logic level on the #CE1 and #CE2 signals. If #CE1 is active, the Secure Digital card interface 23 is selected and if #CE2 is active, Memory Stick card interface 25 is selected. If both #CE1 and #CE2 are inactive, the Controller 41 is disabled and shut down.

A number of different control and transfer routines are written and programmed into a RAM/ROM 42. The Controller 41 first interprets the control signals from the Host 80 or the Internal UART Core 60 and then executes the various routines required.

The Data Converter 40 interfaces with the card interfaces through a general purpose I/O Control 43. The I/O Control 43 includes registers or I/O ports that drive or read the external I/O pins of the Data Converter 40. The Controller 41 can read the registers in the I/O Control 43. A Timer 44 is included for asserting the control signals according to a specific amount of time.

A Data Shifter 46 is connected to the data and clock signals from the card interfaces. When serial data is sent from the Host 80, the Data Shifter 46 clocks in the data on each clock pulse. The clocked data can then be stored in a register or a buffer in RAM/ROM where the Controller 41 can subsequently execute a routine to transfer the data to the Internal UART Core 60. Similarly, when parallel data is sent from the Internal UART Core 60, the Controller 41 stores the data in a register or memory location. When the data is ready, the Data Shifter 46 shifts out the parallel data in serial form to the Host 80. Compact Flash Interface and Control

The Compact Flash (CF) Interface and Control module 30 preferably implements a CF+ Compliant (Revision 1.4) 8-bit card interface. The CF Interface and Control module 30 provides the Host 80 with master access to the External Bluetooth UART module 88 through the Internal UART Core 60 interface. The CF Interface and Control module 30 includes a fixed memory space known as attribute memory where default Card Information Structure (CIS) is stored. The CIS is data used to define the nature of a CF card and any possible configuration of the CF card. An optional Electrical Erasable Programmable Read-Only Memory (EEPROM) interface can be implemented to modify the CIS from the default values. The CF Interface and Control module 30 implements a set of configuration registers that allow the Host 80 to configure and assign the CF Interface and Control module 30 to the CF card.

In the foregoing manner, an interface component or the like glue logic for interfacing a Bluetooth module having a UART or USB interface and a host system without a UART or USB interface is disclosed for providing Bluetooth wireless communication to the host system. Although only a number of embodiments are described, it will be apparent to one skilled in the art in view of this disclosure that numerous changes and/or modifications can be made without departing from the scope and spirit of the invention.

Claims

1. A host controller interface device for interfacing a wireless communication device with a host, the host controller interface device comprising: a parallel peripheral interface for providing parallel data transfer from and to the host; a serial peripheral interface for providing serial data transfer from and to the host; a peripheral interface selector for selecting one of the parallel and serial peripheral interfaces; a host interface for providing data transfer from and to the wireless communication device; a data stream transformer for performing at least one of parallel-to-serial and serial-to-parallel data sfream transformation when the data stream type of the selected one of the parallel and serial peripheral interfaces is dissimilar with the data stream type of the host interface; and a transfer protocol transformer for performing transformation of the transfer protocol of the selected one of the parallel and serial peripheral interfaces to the transfer protocol of the host interface.

2. The host controller interface device as in claim 1, wherein the host interface provides serial data transfer from and to the wireless communication device.

3. The host controller interface device as in claim 2, wherein the host interface is a UART.

4. The host controller interface device as in claim 3, wherein the data sfream transformer is based on a UART.

5. The host controller interface device as in claim 4, wherein the data stream transformer comprises: a controller for providing a communication link between the host and the transfer protocol transformer; a data shifter that converts the data stream during data transfer between the host and the transfer protocol transformer; and a memory for storing codes executable by the controller; and a timer that controls the timing requirement of the communication link.

6. The host controller interface device as in claim 3, wherein the transfer protocol transformer is based on a UART.

7. The host controller interface device as in claim 6, wherein the transfer protocol transformer is programmable to transfer data at different baud rates up to 1.5Mbps.

8. The host controller interface device as in claim 1, wherein the parallel peripheral interface is a Compact Flash interface.

9. The host controller interface device as in claim 8, wherem the Compact Flash interface comprises an attribute memory that stores a CIS value.

10. The host controller interface device as in claim 9, wherein the CIS value is a default CIS value.

11. The host controller interface device as in claim 10, wherein the Compact Flash interface further comprises an EEPROM interface that allows different CIS values to be set.

12. The host controller interface device as in claim 11, wherein the Compact Flash interface further comprises a set of configuration registers for configuring the Compact Flash interface.

13. The host controller interface device as in claim 1, wherein the serial peripheral interface is one of Secure Digital and Memory Stick interfaces.

14. The host controller interface device as in claim 1, wherein the wireless communication device is a Bluetooth communication device.

15. The host controller interface device as in claim 1, wherein the peripheral interface selector is configurable by external pins for selecting the one of the parallel and serial peripheral interfaces.