WO2004021129A3 - Method and system for controlling memory accesses to memory modules having a memory hub architecture - Google Patents

Method and system for controlling memory accesses to memory modules having a memory hub architecture Download PDF

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Publication number
WO2004021129A3
WO2004021129A3 PCT/US2003/027003 US0327003W WO2004021129A3 WO 2004021129 A3 WO2004021129 A3 WO 2004021129A3 US 0327003 W US0327003 W US 0327003W WO 2004021129 A3 WO2004021129 A3 WO 2004021129A3
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WO
WIPO (PCT)
Prior art keywords
memory
modules
memory modules
hub controller
requests
Prior art date
Application number
PCT/US2003/027003
Other languages
French (fr)
Other versions
WO2004021129A2 (en
Inventor
Joseph M Jeddeloh
Terry R Lee
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to AU2003265819A priority Critical patent/AU2003265819A1/en
Priority to JP2004531860A priority patent/JP4284621B2/en
Priority to EP03791913A priority patent/EP1540482A4/en
Publication of WO2004021129A2 publication Critical patent/WO2004021129A2/en
Publication of WO2004021129A3 publication Critical patent/WO2004021129A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers

Abstract

A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.
PCT/US2003/027003 2002-08-29 2003-08-27 Method and system for controlling memory accesses to memory modules having a memory hub architecture WO2004021129A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU2003265819A AU2003265819A1 (en) 2002-08-29 2003-08-27 Method and system for controlling memory accesses to memory modules having a memory hub architecture
JP2004531860A JP4284621B2 (en) 2002-08-29 2003-08-27 Method and system for controlling memory access to a memory module having a memory hub architecture
EP03791913A EP1540482A4 (en) 2002-08-29 2003-08-27 Method and system for controlling memory accesses to memory modules having a memory hub architecture

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/232,473 US6820181B2 (en) 2002-08-29 2002-08-29 Method and system for controlling memory accesses to memory modules having a memory hub architecture
US10/232,473 2002-08-29

Publications (2)

Publication Number Publication Date
WO2004021129A2 WO2004021129A2 (en) 2004-03-11
WO2004021129A3 true WO2004021129A3 (en) 2004-04-29

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/027003 WO2004021129A2 (en) 2002-08-29 2003-08-27 Method and system for controlling memory accesses to memory modules having a memory hub architecture

Country Status (8)

Country Link
US (6) US6820181B2 (en)
EP (1) EP1540482A4 (en)
JP (1) JP4284621B2 (en)
KR (1) KR100919386B1 (en)
CN (1) CN100580639C (en)
AU (1) AU2003265819A1 (en)
TW (1) TWI249671B (en)
WO (1) WO2004021129A2 (en)

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