WO2004015672A1

WO2004015672A1 - Integrated sequential color liquid crystal displays

Info

Publication number: WO2004015672A1
Application number: PCT/US2003/025164
Authority: WO
Inventors: Howard V. Goetz; Steven H. Linn; David L. Keith; Philip Odom
Original assignee: Iljin Diamond Co., Ltd.
Priority date: 2002-08-12
Filing date: 2003-08-11
Publication date: 2004-02-19
Also published as: TW200419497A; AU2003258175A1

Abstract

A sequential color display includes a display driver die (104-107) mounted on a polysilicon or other active matrix display substrate (100). The driver die (104-107) are configured to control column FETs associated with the columns of the display. Row scanners (112) are provided on the polysilicon substrate. The display is mounted on a circuit board carrier that includes an aperture configured to be optically transmissive.

Description

INTEGRATED SEQUENTIAL COLOR LIQUID CRYSTAL DISPLAYS

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Patent Application 60/402,958, filed August 12, 2002, that is incorporated herein by reference.

TECHNICAL FIELD

The disclosure pertains to color-sequential liquid crystal displays.

BACKGROUND

Prior art projection display systems using three panels suffer from a need for accurate alignment (convergence) of the three displays. They also require complex, expensive optical systems to combine the images from the three displays into a focused, converged image. In addition, three channels of electronics are typically required to drive the three displays. In view of these shortcomings, improved projection display systems and methods are needed.

SUMMARY

Sequential color displays comprise a display substrate and at least one video driver die mounted to the display substrate. In some examples, the display substrate includes a plurality of pixels arranged in rows and columns. Each column is associated with a column conductor and a column FET, and the at least one video driver die is configured to communicate pixel values to the column FETs. h additional examples, at least a first video driver die and a second video driver die are mounted to the display substrate. The first video driver die is associated with a first set of pixel columns and the second video driver die is associated with a second set of pixel columns. In other examples, the first set of pixel columns are interleaved with the second set of pixel columns, hi additional representative examples, four video driver die are attached to the display substrate, and each of the driver die is associated with a respective set of pixel columns. In representative examples, a first through fourth video driver die are bonded to the display substrate. The first video driver die and the second video driver die are configured to provide image data to a first set of column conductors, and the third video driver die and the fourth video driver die are configured to provide image data to a second set of column conductors. In other examples, the column conductors of the first set and the second set are interleaved. In other representative examples, interconnect conductors on the display substrate are configured to electrically connect the video driver die to the column conductors. In still other examples, row scanners are situated on the display substrate.

Display substrates comprise a set of row conductors and a set of column conductors, wherein intersections of the row conductors and the column conductors are associated with pixel locations. At least one bond pad is configured to receive a display driver die.

Display methods comprise directing a video signal to at least one video processor die mounted on a display substrate. The video signal is processed with the video processor to determine pixel values for at least a row of display pixels. A row scanner signal is produced on the display substrate and pixel values for the row of display pixels are established based on the row scanner signal and the determined pixel values, hi other examples, the video signal is processed to identify pixel values for the row of display pixels associated with red, blue, and green color components, and row scanner signals are configured to sequentially establish the pixel values associated with the red, blue, and green color components at the display pixels, h other examples, the pixel values associated with at least one of the color components are stored, and the stored values are retrieved after the pixel values associated with at least one other color component are scanned to the row of display pixels. In additional examples, the video processor is configured to determine pixel values associated with red, green, and blue color components. Pixel values associated with at least one of the color components are stored until pixel values associated with a different color component are delivered to at least one row of display pixels. In other representative examples, pixel values associated with at least one of the color components are stored until pixel values associated with a different color component are delivered to a plurality of rows of display pixels, hi other examples, pixel values associated with at least one of the color components are stored until pixel values associated with a different color component are delivered to all rows of display pixels.

These and other features are described below with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic block diagram of a display substrate that includes a polysilicon display and digital drive die attached to the substrate.

FIG. 2 is a schematic block diagram of a display control system for the display substrate of FIG. 1.

FIG. 3 is a plan view of a circuit board layout that includes a display substrate as shown in FIG. 1.

FIGS. 4A-4E illustrate image formation using banded illumination with the display substrate of FIG. 1. FIG. 5 is a schematic diagram of a portion of a line scan, sample and hold

(LSSH) liquid crystal display panel that includes an attached digital driver.

DETAILED DESCRIPTION

Full-color transmission mode LCD displays typically require operation at high data rates to support frame sequential operation. According to examples described herein, a representative display includes a silicon CMOS digital die that is mounted on a polysilicon display substrate. The CMOS die is configured to handle high-speed data to drive the display, so that only lower speed functions such as row scanning and a pixel thin film transistor (TFT) array are implemented in polysilicon. A CMOS digital die can be configured to generate outputs that directly drive column FETs associated with each display column. For convenience, the die can be modular so that, for example, four such die can be used to drive a WVGA panel, six can be used to drive a WXGA panel, etc. The die can be attached via an array of pads on a top surface that connect to a similar array of pads on the polysilicon display using, for example, a "flip-chip" process. Electrical connections are preferably made using an anisotropic adhesive connection, but solder or gold bumps or other connection schemes can be used. Interconnects between flip-chips can be handled by polysilicon or metal lines on the display substrate.

Because of the high data bandwidth used to drive the display, the display and drive electronics are preferably kept close together. Traditional interconnects such as flexible cables are also generally not preferred as it is difficult to make high quality transmission lines on such cables. In a preferred alternative, the display can be mounted on a small circuit board with the drive electronics also mounted to the circuit board and close to the display. The circuit board can include a cut-out behind the active area of the display to transmit light and the display can be electrically connected to the circuit board with wire bonds or Z-axis conductive strips.

Representative examples are described with reference to so-called line scan, sample and hold (LSSH) display panels. In such panels, pixel voltages are controlled by directing an input video signal and a ramp signal to a comparator. The comparator output is used to control a column FET that selectively connects a data ramp signal to a capacitor that stores a pixel value based on the input video signal. Pixel values for a row of pixels are similarly stored on respective pixel capacitors, and are delivered to the row when selected with a row scanner. Each additional row is similarly scanned by the row scanner after pixel values for all pixels in the row are stored. Such a display architecture is described in detail in, for example, PCT Publication WO 02/50810, that is incorporated herein by reference. FIG. 5 illustrates a portion of such a display that includes a drive die 502 and a row buffer 504.

Referring to FIG. 1, a polysilicon/quartz display substrate 100 includes a pixel array 102, drive die 104-107, and bond pad areas 110, 111. In the example of FIG. 1, the pixel array is 864 pixels wide by 480 pixels high. Display columns can be interleaved so that, for example, even columns are driven by the top drive die 104, 105, and odd columns are driven from the bottom drive die 106, 107. Each pair of die can be connected to a 16-bit digital data path or other data path with wirebonds or other interconnects, hi a representative example, the substrate 100 is about 15.6 mm by about 8.6 mm, and pixel pitch is 18 μm. A row scanner 112 is also provided on the display substrate 100. Digital line scan, sample and hold (LSSH)-systems can be used to drive such a display. Such digital LSSH systems are described in, for example, PCT Publication WO 02/50810. This disclosure describes an integrated full color display that, in some examples, can use such digital LSSH systems. Representative drive electronics configured for placement on a circuit board are illustrated in FIG. 2. A digital gate array 202, a frame buffer 204, a digital-to-analog converter 206, a buffer op-amp (not shown), and an EEPROM 210 are situated on a circuit board. The frame buffer 204 is configured for frame sequential refresh of three colors. A row buffer (not shown) can be used for row-sequential or segmented refresh. The DAC 206 produces dataramp signal (DR) at an output 212 based on digital values from the gate array 202, and the op-amp buffers the dataramp voltages to levels needed to drive the display. The EEPROM 210 can be used to store display-dependent calibrations, as needed.

External connections to the circuit board assembly 200 include an RGB video input 216, encoded as, for example, low voltage differential signaling (LVDS) pairs, and power supply connections. Vertical synch (VS), horizontal synch (HS), and a clock input (CLK) are also provided as well as an I C control bus 230.

FIG. 3 is a plan view of a representative display/display driver combination. A circuit board 302 is configured to retain a DAC, a gate array, a frame buffer (BUFF), an EEPROM, and a display assembly 303. An input 304 is configured to receive video and power. Bond pad regions 306 are provided, and flip chip drivers are provided for connection to drive die 311-314. The flip chips include inputs/outputs for a variety of signals such as frame synch, clock, digital video, and others, and can be implemented in a substrate area of about 3.5 mm by 0.8 mm. In a representative example, such a display is operated with co-called

"banded illumination," although a "color-wheel" arrangement or other method can be used. FIGS. 4A-4E illustrate banded illumination. At time T = 0, a green band is written beginning at row 1, a blue band at row 160, and a red band at row 320. At time T = 0.5 μs, green band is written at row 40, blue band at row 200, and a red band at row 360. At time T = 1.0 μs, a green band is written at row 80, a blue band at row 240, and a red band at row 400. At time T = 1.5 μs, a green band is written at row 120, a blue band at row 280, and a red band at row 440. At time T = 2.0 μs, a red band is written at row 1, a green band at row 240, and a blue band at row 400. The writing process continues in the same manner. Image data associated with red (R), green (G), and blue (B) are written down the display panel at rows spaced by 160 rows. In FIG. 4A, green begins at row 1, blue at row 160, and red at row 320. After a time T = 6.0 μs, rows 1-480 are written with red data, and the image data for the remaining colors will have written 480 rows, starting at row 160 and ending at row 159 (blue), and starting at row 320 and ending at row 319. A full image (480 rows of all colors) requires 6.0 μs.

Since only a few external connections to such a display are required, a small interconnect cable can be used. The board assembly can mount directly to an optical assembly, and alignment can be accomplished by simply loosening the board mounting screws and adjusting the whole assembly into the proper position. Since there is only a single display panel, the optical system is reduced to an illumination source and a projection lens. Convergence adjustments are unnecessary. It will be apparent that the examples described above can be modified in arrangement and detail without departing from the disclosed principles. These examples are not to be taken as limiting the scope of these principles, and we claim all that is encompassed by the appended claims.

Claims

We claim:

1. A sequential color display, comprising: a display substrate; and at least one video driver die mounted to the display substrate.

2. The sequential color display of claim 1, wherein the display substrate includes a plurality of pixels arranged in rows and columns, and each column is associated with a column conductor and a column FET, and the at least one video driver die is configured to control pixel values applied by the column FETs.

3. The sequential color display of claim 2, wherein the display substrate includes a column comparator, and the at least one video driver die is electrically connected to the column comparator.

4. The sequential color display of claim 1, wherein at least a first video driver die and a second video driver die are mounted to the display substrate, and the first video driver die is associated with a first set of pixel columns and the second video driver die is associated with a second set of pixel columns.

5. The sequential color display of claim 4, wherein the first set of pixel columns is interleaved with the second set of pixel columns.

6. The sequential color display of claim 1, wherein four video driver die are attached to the display substrate, and each of the driver die is associated with a respective set of pixel columns.

7. The sequential color display of claim 1, wherein a first through fourth video driver die are bonded to the display substrate, and the first video driver die and the second video driver die are configured to provide image data to a first set of column conductors, and the third video driver die and the fourth video driver die are configured to provide image data to a second set of column conductors.

8. The sequential color display of claim 7, wherein the column conductors of the first set and the second set are interleaved.

9. The sequential color display of claim 1, further comprising interconnect conductors configured to electrically connect the video driver die to the column conductors.

10. The sequential color display of claim 9, further comprising row scanners situated on the display substrate.

11. A display substrate, comprising: a set of row conductors; a set of column conductors, wherein intersections of the row conductors and the column conductors are associated with pixel locations; and at least one bond pad configured to receive a display driver die.

12. The display substrate of claim 11, further comprising row scanners in communication with the row conductors.

13. The display substrate of claim 11 , wherein a plurality of bond pads are configured to receive display driver die, and at least one bond pad is in communication with at least one column conductor.

14. A display method, comprising: directing a video signal to a video processor die mounted on a display substrate; processing the video signal with the video processor to determine pixel values of a row of display pixels; and producing a row scanner signal based on row scanner defined on the display substrate; and establishing pixel values for the row of display pixels based on the row scanner signal and the determined pixel values.

15. The method of claim 14, further comprising: processing the video signal to identify pixel values for the row of display pixels associated with red, blue, and green color components; and producing row scanner signals configured to sequentially establish the pixel values associated with the red, blue, and green color components at the display pixels.

16. The method of claim 15, further comprising: storing the pixel values associated with at least one of the color components; and retrieving the stored values after the pixel values associated with at least one other color component are scanned to the row of display pixels.

17. The method of claim 14, wherein the video processor is configured to determine pixel values associated with red, green, and blue color components, and further comprising storing pixel values associated with at least one of the color components until pixel values associated with a different color component are delivered to at least one row of display pixels.

18. The method of claim 17, further comprising storing pixel values associated with at least one of the color components until pixel values associated with a different color component are delivered to a plurality of rows of display pixels.

19. The method of claim 17, further comprising storing pixel values associated with at least one of the color components until pixel values associated with a different color component are delivered to all rows of display pixels.

20. A color sequential display system, comprising: a display substrate; an LCD; a digital driver die bonded to the display substrate and configured to produced pixel values associated with first, second, and third color components; a pixel buffer configured to store pixel values for at least one row of pixels for two color components, wherein the digital driver die directs pixel values to the LCD for a selected color component and to the pixel buffer for the unselected color components; and an optical projection system configured to project an image based on the LCD.