WO2004012256A1 - Process for manufacturing mosfets using amorphous carbon replacement gate and structures formed in accordance therewith - Google Patents
Process for manufacturing mosfets using amorphous carbon replacement gate and structures formed in accordance therewith Download PDFInfo
- Publication number
- WO2004012256A1 WO2004012256A1 PCT/US2003/021107 US0321107W WO2004012256A1 WO 2004012256 A1 WO2004012256 A1 WO 2004012256A1 US 0321107 W US0321107 W US 0321107W WO 2004012256 A1 WO2004012256 A1 WO 2004012256A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- gate
- amorphous carbon
- dummy gate
- substrate
- layer
- Prior art date
Links
- 229910003481 amorphous carbon Inorganic materials 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 20
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 14
- 238000004380 ashing Methods 0.000 claims abstract description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 6
- 238000009792 diffusion process Methods 0.000 claims abstract description 6
- 239000001301 oxygen Substances 0.000 claims abstract description 6
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 5
- 239000001257 hydrogen Substances 0.000 claims abstract description 5
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims abstract 2
- 239000000758 substrate Substances 0.000 claims description 21
- 125000006850 spacer group Chemical group 0.000 claims description 12
- 239000012212 insulator Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 229920005591 polysilicon Polymers 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000002513 implantation Methods 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 229910002091 carbon monoxide Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910000042 hydrogen bromide Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
Definitions
- Embodiments of the invention pertain to metal oxide semiconductor field effect transistors (MOSFETs), and in particular to the manufacture of MOSFETs using a replacement gate process.
- MOSFETs metal oxide semiconductor field effect transistors
- FIG. 1 shows an example of a typical MOSFET 10.
- the MOSFET 10 includes gate structure comprised of a gate line 12 (hereinafter "gate Line” or “gate”), a gate insulator 14 and spacers 16.
- the gate line 12 and gate insulator 14 are formed over a channel region 18 of a semiconductor substrate 20.
- the gate structure is surrounded by an interlevel dielectric layer (ILD) 22 such as silicon oxide.
- the MOSFET 10 further includes composite source and drain diffusions comprised of overlapping lightly doped source and drain regions 24 and heavily doped source and drain regions 26.
- replacement gate in which the initial polysilicon gate is used as a "dummy" gate that is replaced with metal after formation of other MOSFET features. This is typically done by forming a MOSFET gate structure including a polysilicon dummy gate, depositing an ILD over the substrate and the gate structure, polishing back the ILD to expose the polysilicon dummy gate, etching to remove some or all of the polysilicon dummy gate, and then inlaying metal in place of the removed polysilicon to form a metal gate.
- the replacement gate process improves over the conventional polysilicon gate MOSFET, the process has undesirable features.
- One undesirable feature is that it is relatively difficult to pattern polysilicon with good profiles, particularly at small dimensions, and so formation of the polysilicon dummy gate is relatively difficult.
- Another undesirable feature is the difficulty of preventing damage to the gate insulator. Because the gate insulator is so thin, any damage to the gate insulator during removal of the polysilicon gate requires complete removal and replacement of the gate insulator. Thus it would be desirable to have a replacement gate process that avoids the difficulties of polysilicon dummy gate formation and removal.
- the replacement gate process is improved by the use of an amorphous carbon dummy gate.
- Amorphous carbon is easily and accurately patterned and removed through the use of a dry anisotropic oxygen or hydrogen plasma etch, referred to herein as "ashing.” This treatment provides rapid removal and high selectivity.
- Figures 2a, 2b, 2c, 2d, 2e, 2f and 2g show structures formed during processing in accordance with a preferred embodiment.
- Figure 3 shows a process flow encompassing the preferred embodiment and alternatives thereto.
- Figure 2a shows a semiconductor substrate 30 having formed thereon a gate insulating layer 32 such as Si0 2 or SiON. Overlying the gate insulating layer 32 are an amorphous carbon layer 34, a hardmask layer 36 such as SiN, and a photoresist pattern 38.
- the amorphous carbon layer 34 is formed by a PECVD process using carbon containing precursors.
- the hardmask layer 36, and the amorphous carbon layer 34 are sequentially anisotropically etched to form an amorphous carbon dummy gate 40 on the gate insulator 32.
- the hardmask layer is typically patterned using a combination of Ar and CF 4 .
- the amorphous carbon layer is typically patterned using a combination of HBr, oxygen, and argon.
- lightly doped source and drain regions 44 are formed by implantation using the amorphous carbon dummy gate 40 to mask a channel region 46 in the substrate. Other areas of the substrate are suitably masked during implantation to define the lightly doped source and drain regions 44.
- Figure 2c shows the structure of Figure 2b after formation of spacers 48 surrounding the amorphous carbon dummy gate 40.
- the spacers 48 are typically made of silicon oxide or silicon nitride and are formed by depositing a conformal layer of silicon oxide over the substrate, followed by anisotropically etching the silicon oxide to leave spacers 48 as shown.
- heavily doped source and drain regions 50 are formed by an implantation process that uses the dummy gate 40 and spacers 48 to mask the channel region 46 and extension portions of the lightly doped source and drain regions 44. Other areas of the substrate are suitably masked during implantation to define the heavily doped source and drain regions 50.
- Figure 2d shows the structure of Figure 2c after formation of a conformal layer of an interlevel dielectric 52 such as silicon oxide over the substrate. As shown in Figure 2e, a portion of the interlevel dielectric layer 52 is removed by chemical mechanical polishing to expose the amorphous carbon dummy gate 40.
- an interlevel dielectric 52 such as silicon oxide
- Figure 2f shows the structure of Figure 2e after removal of the amorphous carbon dummy gate 40 by an ashing process to leave a void 54.
- Ashing is preferably performed using a dry oxygen or hydrogen plasma.
- the ashing process consumes amorphous carbon by forming volatile products such as carbon dioxide, carbon monoxide, or methane that are evacuated from the chamber.
- Figure 2g shows the structure of Figure 2f after inlaying of a metal gate 56 into the void 54 left by the removed amorphous carbon dummy gate.
- the metal gate 56 is preferably formed of a metal that exhibits relatively low resistivity and low diffusion, such as tungsten or aluminum. Other metals that may be used include, but are not limited to, TiN, WN, TaN, and Ru0 2 .
- Inlaying is typically performed by depositing a conformal layer of metal by sputtering to fill the void 54, followed by polishing to remove an overburden portion of the sputtered metal to leave the inlaid metal
- Figure 2g After the structure of Figure 2g is formed, additional conventional processing may be performed, such as formation of source and drain contacts by an inlay process and silicidation of the contacts, or formation of a protective layer over the ILD. While the process flow of Figures 2a-2g is presently considered to be the preferred embodiment of the invention, a wide variety of alternative embodiments in accordance with the invention may be formulated. For example, in one alternative embodiment, more than one set of spacers may be sequentially formed in conjunction with sequential implantations to form source and drain diffusions that are a composite of three or more implanted regions. In another alternative embodiment, source and drain contacts may be formed concurrently with inlaying of the metal gate.
- processing tasks such as seed layer formation, seed layer enhancement, formation and removal of passivation layers or protective layers between processing tasks, formation and removal of photoresist masks and other masking layers such as antireflective layers, trimming of photoresist masks and other masking structures, formation of isolation structures, as well as other tasks, may be performed along with the tasks specifically described above. Further, the process need not be performed on an entire substrate such as an entire wafer, but rather may be performed selectively on sections of the substrate.
- Figure 3 shows a process flow for producing a MOSFET that encompasses the preferred embodiment and its aforementioned alternatives, as well as other alternative embodiments that are not explicitly discussed here but will be apparent to those of ordinary skill in the art.
- amorphous carbon layer is formed over a substrate (60).
- the substrate is preferably a semiconductor layer that is covered by a gate insulating layer.
- a gate structure comprising an amorphous carbon dummy gate is then formed from the amorphous carbon layer (62). This is preferably accomplished by patterning the amorphous carbon using a photoresist mask and a hard mask, followed by formation of spacers.
- the dummy gate and spacers are preferably used as masks for one or more implantations that define source and drain diffusions.
- An interlevel dielectric layer is then deposited over the substrate and gate structure (64), and a portion of the interlevel dielectric layer is then removed to expose the amorphous carbon dummy gate (66).
- the amorphous carbon dummy gate is then removed by an ashing process (68). Ashing is preferably performed using oxygen or hydrogen plasma.
- a metal gate is then inlaid in place of the amorphous carbon dummy gate (70).
- the metal gate may be aluminum or tungsten, or another metal as described above.
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2003249717A AU2003249717A1 (en) | 2002-07-31 | 2003-07-03 | Process for manufacturing mosfets using amorphous carbon replacement gate and structures formed in accordance therewith |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US40012302P | 2002-07-31 | 2002-07-31 | |
US60/400,123 | 2002-07-31 | ||
US33547302A | 2002-12-31 | 2002-12-31 | |
US10/335,473 | 2002-12-31 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2004012256A1 true WO2004012256A1 (en) | 2004-02-05 |
Family
ID=31190861
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2003/021107 WO2004012256A1 (en) | 2002-07-31 | 2003-07-03 | Process for manufacturing mosfets using amorphous carbon replacement gate and structures formed in accordance therewith |
Country Status (3)
Country | Link |
---|---|
AU (1) | AU2003249717A1 (en) |
TW (1) | TW200403811A (en) |
WO (1) | WO2004012256A1 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102779746A (en) * | 2012-08-16 | 2012-11-14 | 上海华力微电子有限公司 | Method for forming metal grid |
CN103390556A (en) * | 2012-05-08 | 2013-11-13 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
CN103426754A (en) * | 2012-05-14 | 2013-12-04 | 中芯国际集成电路制造(上海)有限公司 | Method for forming transistor |
CN104078363A (en) * | 2013-03-29 | 2014-10-01 | 中国科学院微电子研究所 | Method for manufacturing semiconductor device |
CN105185713A (en) * | 2015-08-26 | 2015-12-23 | 上海华力微电子有限公司 | HKMG device preparation method |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5391510A (en) * | 1992-02-28 | 1995-02-21 | International Business Machines Corporation | Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps |
EP0929105A2 (en) * | 1998-01-09 | 1999-07-14 | Sharp Kabushiki Kaisha | Metal gate sub-micron mos transistor and method of making same |
US6090672A (en) * | 1998-07-22 | 2000-07-18 | Wanlass; Frank M. | Ultra short channel damascene MOS transistors |
US6251763B1 (en) * | 1997-06-30 | 2001-06-26 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing same |
US6376347B1 (en) * | 1999-09-27 | 2002-04-23 | Kabushiki Kaisha Toshiba | Method of making gate wiring layer over semiconductor substrate |
-
2003
- 2003-07-03 AU AU2003249717A patent/AU2003249717A1/en not_active Abandoned
- 2003-07-03 WO PCT/US2003/021107 patent/WO2004012256A1/en not_active Application Discontinuation
- 2003-07-22 TW TW92119915A patent/TW200403811A/en unknown
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5391510A (en) * | 1992-02-28 | 1995-02-21 | International Business Machines Corporation | Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps |
US6251763B1 (en) * | 1997-06-30 | 2001-06-26 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing same |
EP0929105A2 (en) * | 1998-01-09 | 1999-07-14 | Sharp Kabushiki Kaisha | Metal gate sub-micron mos transistor and method of making same |
US6090672A (en) * | 1998-07-22 | 2000-07-18 | Wanlass; Frank M. | Ultra short channel damascene MOS transistors |
US6376347B1 (en) * | 1999-09-27 | 2002-04-23 | Kabushiki Kaisha Toshiba | Method of making gate wiring layer over semiconductor substrate |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103390556A (en) * | 2012-05-08 | 2013-11-13 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
WO2013166631A1 (en) * | 2012-05-08 | 2013-11-14 | 中国科学院微电子研究所 | Method for manufacturing semiconductor component |
US20150118818A1 (en) * | 2012-05-08 | 2015-04-30 | Haizhou Yin | Method for manufacturing semiconductor device |
US9530861B2 (en) | 2012-05-08 | 2016-12-27 | Institute of Microelectronics, Chinese Academy of Sciences | Method for manufacturing semiconductor device |
CN103426754A (en) * | 2012-05-14 | 2013-12-04 | 中芯国际集成电路制造(上海)有限公司 | Method for forming transistor |
CN102779746A (en) * | 2012-08-16 | 2012-11-14 | 上海华力微电子有限公司 | Method for forming metal grid |
CN104078363A (en) * | 2013-03-29 | 2014-10-01 | 中国科学院微电子研究所 | Method for manufacturing semiconductor device |
CN105185713A (en) * | 2015-08-26 | 2015-12-23 | 上海华力微电子有限公司 | HKMG device preparation method |
Also Published As
Publication number | Publication date |
---|---|
AU2003249717A1 (en) | 2004-02-16 |
TW200403811A (en) | 2004-03-01 |
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