WO2004008509A1 - Defect reduction in semiconductor materials - Google Patents

Defect reduction in semiconductor materials Download PDF

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Publication number
WO2004008509A1
WO2004008509A1 PCT/EP2003/007604 EP0307604W WO2004008509A1 WO 2004008509 A1 WO2004008509 A1 WO 2004008509A1 EP 0307604 W EP0307604 W EP 0307604W WO 2004008509 A1 WO2004008509 A1 WO 2004008509A1
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Prior art keywords
etching
epitaxial
substrate
growth
layer
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PCT/EP2003/007604
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French (fr)
Inventor
Brendan John Roycroft
Pleun Pieter Maaskant
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University College Cork - National University Of Ireland, Cork
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Application filed by University College Cork - National University Of Ireland, Cork filed Critical University College Cork - National University Of Ireland, Cork
Priority to JP2004520620A priority Critical patent/JP2005532692A/en
Priority to AU2003254349A priority patent/AU2003254349A1/en
Priority to EP03763842A priority patent/EP1540713A1/en
Publication of WO2004008509A1 publication Critical patent/WO2004008509A1/en
Priority to US11/030,986 priority patent/US7399684B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H01L21/30621—Vapour phase etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02378—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H01L21/30617—Anisotropic liquid etching

Definitions

  • the invention relates to the production of epitaxial materials with a reduced defect density.
  • Epitaxial wafer materials are widely used as starting materials in semiconductor device fabrication.
  • the presence of defects in such wafer materials can seriously affect the subsequent device performance.
  • GaN and its related compounds InGaN and AlGaN are widely used in the fabrication of short- wavelength semiconductor laser diodes.
  • the performance of such laser diodes is seriously degraded by the presence of threading dislocations, which thread vertically through the epitaxial layers. Similar defects are found in other material systems, for example, when GaAs is grown on SiGe/Si. A reduced dislocation density on the epitaxial wafer materials is therefore desired.
  • GaN shall also refer to its compounds (In)(Al)(Ga)N, and may be p-type, n-type or undoped.
  • ELOG Epitaxial Layer Over-Growth
  • Defect density in good ELOG growth is reduced from 10 l ⁇ cm “2 in standard GaN/Sapphire growth, to 10 8 cm “2 in 1 step ELOG, or to 5.10 5 cm “2 after multiple steps of ELOG.
  • a defect density of 5.10 5 cm “2 corresponds to 1 defect per 14 ⁇ mxl4 ⁇ m square area. Therefore, the size of a defect-free area is still small in comparison to the 50mm diameter wafer area available for device fabrication.
  • a second approach, described in US patent application US2002/0005593 is to grow standard GaN epitaxial layers at high temperature (1000 °C), then deposit a thin layer of GaN at a lower temperature (700 - 900 °C), then resume growth at the high temperature (1000 °C). It is claimed that this prevents defects from propagating vertically, and reduces the defect density from >10 10 cm 2 to 4.10 7 cm 2 . This approach suffers from insufficient removal of defects.
  • a third approach is the direct production of GaN substrates from liquid gallium, and nitrogen at very high pressure (45,000 bar) (by Unipress in Poland). This approach suffers from the use of very highly specialised and expensive equipment, and the production of rather small ( ⁇ 1 cm 2 ) GaN crystals.
  • the invention is therefore directed towards providing a method and system to produce large areas of epitaxial material with low defect density in a simple and effective manner, using relatively common and inexpensive equipment and materials.
  • a method of producing a low-defect semiconductor wafer in which an epitaxial layer is grown on a substrate comprising the steps of:- (a) growing a layer of epitaxial material on the substrate,
  • the step (b) is performed by exposing the surface to dry etching by RIE, or ICP (Inductively Coupled Plasma etching), or chemically assisted ion beam etching, or other suitable dry etching process.
  • RIE reactive ion etching
  • ICP Inductively Coupled Plasma etching
  • chemically assisted ion beam etching or other suitable dry etching process.
  • the step (b) is performed by immersion in aqua regia, or a mixture of KOH/NaOH, or other suitable wet etching solution.
  • an additional compound is added for the growth step (c) to improve surface smoothness.
  • the additional compound is In(Ga)N, or Al(Ga)N, or magnesium doped (Al)(In)(Ga)N.
  • the epitaxial material is GaN.
  • the substrate is of sapphire material.
  • the substrate is of Si, SiC, or diamond material.
  • the epitaxial material is InP.
  • the epitaxial material is GaAs.
  • the method comprises the further steps of repeating steps (b) and (c) one or more additional times until a target defect density is achieved.
  • the etching is performed in-situ within a growth chamber.
  • the etching is performed under vacuum.
  • the invention provides a semiconductor wafer whenever produced by a method as defined above.
  • Figs. 1(a) to 1(d) are a series of diagrams showing a semiconductor growth method of the invention.
  • Fig. 2 is a photograph illustrating the surface of etched GaN after RIE.
  • a sapphire substrate 1 acts as the substrate for the epitaxial growth of device quality wafer material.
  • an initial epitaxial layer 2 of GaN is grown on the substrate 1 in a conventional manner. However, there are many defects 3 which thread through the epitaxial layer 2.
  • the epitaxial layer 2 is etched by wet or dry etching within the growth chamber.
  • the etching acts preferentially on the epitaxial layer 2 at the defects 3, causing them to become enlarged cavities 5, which may or may not extend down to the substrate 1.
  • These cavities 5 appear as black dots in the photograph of an etched surface shown in Fig. 2.
  • the cavities 5 are too large in proportion to the crystal lattice to act as defects in the usual sense.
  • Indium or magnesium may be added to the GaN to aid planarisation. Steps (c) and (d) may be repeated if removal of defects was not sufficient in step (c).
  • Further epitaxial growth allows wafer materials for devices such as high power transistors, light emitting diodes, and laser diodes to be produced.
  • GaN growth is initiated in the standard way by MOVPE or MBE. It has been found by other groups that after an initial three dimensional growth, a two dimensional growth mode takes over. Incorporated unintentionally in this two dimensional growth are many threading dislocations which propagate upwards through any subsequent growth.
  • the wafer is removed from the growth chamber and placed in a reactive ion etch (RIE) chamber. Etching proceeds with a mixture of SiCl 4 /H 2 as the etchant. This has been found to preferentially etch macroscopic defects and threading dislocations.
  • RIE reactive ion etch
  • etching is left to the discretion of the operator, but should be long enough to cause substantial etching of the defects, which may or may not be etched all the way back to the substrate.
  • the surface is heat treated at 300-1000°C in a N 2 or NH 3 ambient. GaN growth is then resumed in the growth reactor until a planar surface is achieved. The wafer is now ready for the subsequent growth of device epitaxial layers, as required.
  • Example 2
  • GaN growth is initiated in the standard way by MOVPE or MBE.
  • MOVPE commonly sapphire, but may be SiC or other
  • GaN growth is initiated in the standard way by MOVPE or MBE.
  • MOVPE commonly sapphire, but may be SiC or other
  • the wafer is removed from the growth chamber and placed in a beaker of boiling aqua regia solution (HC1:HN0 3 at 3:1).
  • Etching has been found to leave the good quality GaN areas almost unaffected, but macroscopic defects and threading dislocations are substantially etched.
  • the time of etching is left to the discretion of the operator, but should be long enough to cause substantial etching of the defects, which may or may not be etched all the way back to the substrate.
  • the wafer is then removed from the solution, placed in boiling ammonia polysulfide solution for ten minutes, removed, rinsed in de-ionised water, then dried. Finally, GaN growth is resumed in the growth reactor until a planar surface is achieved. The wafer is now ready for subsequent device epitaxial layers, as required.
  • the invention achieves a more effective reduction of defects with simpler processing than the prior art.
  • the etching step is applied to the whole wafer surface there is no need for definition/ masking of surface areas as in the ELOG approach.
  • the invention does not require the incorporation of a foreign material (such as Si0 2 or Si x N y in ELOG) as it effectively provides an homogenous GaN epitaxy over the substrate.
  • defects are removed over the whole surface, rather than in strips as in ELOG.
  • there is little material wastage as only about 1 micron is lost due to the dry etching, and almost no material is lost due to the wet etching. Regrowth may achieve planarisation in less than 1 micron of growth, due to the small size of the defects.
  • at least 2 micron growth is required to cover the Si0 2 strips and to achieve a planarised surface, often over 100 micron growth is used.
  • the invention can be applied to the growth of other epitaxial layers for a wide variety of semiconductor devices, such as InP, GaAs, and Si. Further any other suitable substrate may be used such as Si, SiC, or diamond. Also, any suitable wet or dry etching method which preferentially etches the defects may be used.

Abstract

An initial epitaxial layer (2) of GaN is grown on a sapphire substrate (2). The epitaxial layer (2) is then etched in a reactive ion etch (RIE) chamber. This etching acts preferentially at defects (3), causing them to become enlarged cavities (5). The cavities (5) are too large in proportion to the crystal lattice to act as defects in the usual sense, and so a further GaN epitaxial layer fills into the cavities. Thus, propagation of defects is avoided.

Description

"Defect Reduction in Semiconductor Materials"
Introduction
The invention relates to the production of epitaxial materials with a reduced defect density.
Epitaxial wafer materials are widely used as starting materials in semiconductor device fabrication. The presence of defects in such wafer materials can seriously affect the subsequent device performance. For example, GaN and its related compounds InGaN and AlGaN are widely used in the fabrication of short- wavelength semiconductor laser diodes. The performance of such laser diodes is seriously degraded by the presence of threading dislocations, which thread vertically through the epitaxial layers. Similar defects are found in other material systems, for example, when GaAs is grown on SiGe/Si. A reduced dislocation density on the epitaxial wafer materials is therefore desired. It shall be understood in the following descriptions that GaN shall also refer to its compounds (In)(Al)(Ga)N, and may be p-type, n-type or undoped.
A prior approach known to the inventors to solve the problem of reducing the defeςt density is Epitaxial Layer Over-Growth (ELOG) described in US patent application US2002/0022290. In this approach, narrow strips of silicon dioxide are patterned on a GaN buffer layer. GaN growth is then restarted until the SiO2 strips are covered and a planar surface is achieved. The defects under the strips are blanked out and epitaxial material above the strips apparently has a lower defect density than the material grown between the strips. The material above the Si02 is found to be of high quality, but the material between the strips is unchanged, and so it appears that multiple steps of ELOG need to be made to create large areas of good quality material. Defect density in good ELOG growth is reduced from 10lϋ cm"2 in standard GaN/Sapphire growth, to 108 cm"2 in 1 step ELOG, or to 5.105 cm"2 after multiple steps of ELOG. A defect density of 5.105 cm"2 corresponds to 1 defect per 14μmxl4 μm square area. Therefore, the size of a defect-free area is still small in comparison to the 50mm diameter wafer area available for device fabrication.
Another problem is that this approach requires considerable additional effort in processing and regrowth, requiring over 100 μm of epitaxial growth for best results.
A second approach, described in US patent application US2002/0005593 is to grow standard GaN epitaxial layers at high temperature (1000 °C), then deposit a thin layer of GaN at a lower temperature (700 - 900 °C), then resume growth at the high temperature (1000 °C). It is claimed that this prevents defects from propagating vertically, and reduces the defect density from >1010 cm2 to 4.107 cm2. This approach suffers from insufficient removal of defects.
A third approach is the direct production of GaN substrates from liquid gallium, and nitrogen at very high pressure (45,000 bar) (by Unipress in Poland). This approach suffers from the use of very highly specialised and expensive equipment, and the production of rather small (~1 cm2) GaN crystals.
The invention is therefore directed towards providing a method and system to produce large areas of epitaxial material with low defect density in a simple and effective manner, using relatively common and inexpensive equipment and materials.
Statements of Invention
According to the invention, there is provided a method of producing a low-defect semiconductor wafer in which an epitaxial layer is grown on a substrate, the method comprising the steps of:- (a) growing a layer of epitaxial material on the substrate,
(b) etching the epitaxial layer in such a manner as to preferentially etch the defects of the layer; and
(c) growing a subsequent layer of epitaxial material on the etched epitaxial layer.
In one embodiment, the step (b) is performed by exposing the surface to dry etching by RIE, or ICP (Inductively Coupled Plasma etching), or chemically assisted ion beam etching, or other suitable dry etching process.
In another embodiment, the step (b) is performed by immersion in aqua regia, or a mixture of KOH/NaOH, or other suitable wet etching solution.
In a further embodiment, an additional compound is added for the growth step (c) to improve surface smoothness.
In one embodiment, the additional compound is In(Ga)N, or Al(Ga)N, or magnesium doped (Al)(In)(Ga)N.
In another embodiment, the epitaxial material is GaN.
In a further embodiment, the substrate is of sapphire material.
In one embodiment, the substrate is of Si, SiC, or diamond material.
In one embodiment, the epitaxial material is InP.
In another embodiment, the epitaxial material is GaAs. In a further embodiment, the method comprises the further steps of repeating steps (b) and (c) one or more additional times until a target defect density is achieved.
In one embodiment, the etching is performed in-situ within a growth chamber.
In another embodiment, the etching is performed under vacuum.
According to another aspect, the invention provides a semiconductor wafer whenever produced by a method as defined above.
Detailed Description of the Invention
The invention will be more clearly understood from the following description of some embodiments thereof, given by way of example only with reference to the accompanying drawings in which :-
Figs. 1(a) to 1(d) are a series of diagrams showing a semiconductor growth method of the invention; and
Fig. 2 is a photograph illustrating the surface of etched GaN after RIE.
Referring to Fig. 1(a), a sapphire substrate 1 acts as the substrate for the epitaxial growth of device quality wafer material. As shown in Fig. 1(b) an initial epitaxial layer 2 of GaN is grown on the substrate 1 in a conventional manner. However, there are many defects 3 which thread through the epitaxial layer 2.
Referring to Fig. 1(c) the epitaxial layer 2 is etched by wet or dry etching within the growth chamber. The etching acts preferentially on the epitaxial layer 2 at the defects 3, causing them to become enlarged cavities 5, which may or may not extend down to the substrate 1. These cavities 5 appear as black dots in the photograph of an etched surface shown in Fig. 2. The cavities 5 are too large in proportion to the crystal lattice to act as defects in the usual sense. Thus, when a further layer of GaN is grown (Fig. 1(d)) it fills into the cavities 5 with lateral growth and over the layer 2 to form a homogeneous relatively-defect-free epitaxy 10. Indium or magnesium may be added to the GaN to aid planarisation. Steps (c) and (d) may be repeated if removal of defects was not sufficient in step (c). Further epitaxial growth allows wafer materials for devices such as high power transistors, light emitting diodes, and laser diodes to be produced.
The following are two detailed examples of implementation of the invention.
Example 1
Starting with a substrate suitable for GaN growth (commonly sapphire, but may be SiC or other), GaN growth is initiated in the standard way by MOVPE or MBE. It has been found by other groups that after an initial three dimensional growth, a two dimensional growth mode takes over. Incorporated unintentionally in this two dimensional growth are many threading dislocations which propagate upwards through any subsequent growth. After the planar growth mode is established, the wafer is removed from the growth chamber and placed in a reactive ion etch (RIE) chamber. Etching proceeds with a mixture of SiCl4/H2 as the etchant. This has been found to preferentially etch macroscopic defects and threading dislocations. The time of etching is left to the discretion of the operator, but should be long enough to cause substantial etching of the defects, which may or may not be etched all the way back to the substrate. After dry etching, the surface is heat treated at 300-1000°C in a N2 or NH3 ambient. GaN growth is then resumed in the growth reactor until a planar surface is achieved. The wafer is now ready for the subsequent growth of device epitaxial layers, as required. Example 2
Starting with a substrate suitable for GaN growth (commonly sapphire, but may be SiC or other), GaN growth is initiated in the standard way by MOVPE or MBE. After the planar growth mode is established, the wafer is removed from the growth chamber and placed in a beaker of boiling aqua regia solution (HC1:HN03 at 3:1). Etching has been found to leave the good quality GaN areas almost unaffected, but macroscopic defects and threading dislocations are substantially etched. The time of etching is left to the discretion of the operator, but should be long enough to cause substantial etching of the defects, which may or may not be etched all the way back to the substrate. The wafer is then removed from the solution, placed in boiling ammonia polysulfide solution for ten minutes, removed, rinsed in de-ionised water, then dried. Finally, GaN growth is resumed in the growth reactor until a planar surface is achieved. The wafer is now ready for subsequent device epitaxial layers, as required.
It will be appreciated that the invention achieves a more effective reduction of defects with simpler processing than the prior art. For example, because the etching step is applied to the whole wafer surface there is no need for definition/ masking of surface areas as in the ELOG approach. Further, the invention does not require the incorporation of a foreign material (such as Si02 or SixNy in ELOG) as it effectively provides an homogenous GaN epitaxy over the substrate. A further advantage is that defects are removed over the whole surface, rather than in strips as in ELOG. It will also be appreciated that there is little material wastage as only about 1 micron is lost due to the dry etching, and almost no material is lost due to the wet etching. Regrowth may achieve planarisation in less than 1 micron of growth, due to the small size of the defects. In ELOG, at least 2 micron growth is required to cover the Si02 strips and to achieve a planarised surface, often over 100 micron growth is used.
It is envisaged that the invention can be applied to the growth of other epitaxial layers for a wide variety of semiconductor devices, such as InP, GaAs, and Si. Further any other suitable substrate may be used such as Si, SiC, or diamond. Also, any suitable wet or dry etching method which preferentially etches the defects may be used.
The invention is not limited to the embodiments described but may be varied in construction and detail.

Claims

Claims
1. A method of producing a low-defect semiconductor wafer in which an epitaxial layer is grown on a substrate, the method comprising the steps of:-
(a) growing a layer of epitaxial material on the substrate,
(b) etching the epitaxial layer in such a manner as to preferentially etch the defects of the layer; and
(c) growing a subsequent layer of epitaxial material on the etched epitaxial wafer.
2. A method as claimed in claim 1, wherein the step (b) is performed by exposing the surface to dry etching by RIE, or ICP (Inductively Coupled
Plasma etching), or chemically assisted ion beam etching, or other suitable dry etching process.
3. A method as claimed in claim 1, wherein the step (b) is performed by immersion in aqua regia, or a mixture of KOH/NaOH, or other suitable wet etching solution.
4. A method as claimed in any preceding claim, wherein an additional compound is added for the growth step (c) to improve surface smoothness.
5. A method as claimed in claim 4, wherein the additional compound is In(Ga)N, or Al(Ga)N, or magnesium doped (Al)(In)(Ga)N.
6. A method as claimed in any preceding claim, wherein the epitaxial material is GaN.
7. A method as claimed in claim 6, wherein the substrate is of sapphire material.
8. A method as claimed in any of claims 1 to 6, wherein the substrate is of Si, SiC, or diamond material.
9. A method as claimed in any of claims 1 to 4, wherein the epitaxial material is InP.
10. A method as claimed in any of claims 1 to 4, wherein the epitaxial material is GaAs.
11. A method as claimed in any preceding claim, wherein the method comprises the further steps of repeating steps (b) and (c) one or more additional times until a target defect density is achieved.
12. A method as claimed in any preceding claim, wherein the etching is performed in-situ within a growth chamber.
13. A method as claimed in any preceding claim, wherein the etching is performed under vacuum.
14. A method substantially as described with reference to the drawings.
15. A semiconductor wafer whenever produced by a method as claimed in any preceding claim.
PCT/EP2003/007604 2002-07-11 2003-07-11 Defect reduction in semiconductor materials WO2004008509A1 (en)

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JP2004520620A JP2005532692A (en) 2002-07-11 2003-07-11 Defect reduction in semiconductor materials.
AU2003254349A AU2003254349A1 (en) 2002-07-11 2003-07-11 Defect reduction in semiconductor materials
EP03763842A EP1540713A1 (en) 2002-07-11 2003-07-11 Defect reduction in semiconductor materials
US11/030,986 US7399684B2 (en) 2002-07-11 2005-01-10 Defect reduction in semiconductor materials

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IE20020574 2002-07-11

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WO2006064081A1 (en) 2004-12-14 2006-06-22 Optogan Oy Semiconductor substrate, semiconductor device and method of manufacturing a semiconductor substrate

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