WO2004006311A3 - Transfer of a thin layer from a wafer comprising a buffer layer - Google Patents

Transfer of a thin layer from a wafer comprising a buffer layer Download PDF

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Publication number
WO2004006311A3
WO2004006311A3 PCT/IB2003/003497 IB0303497W WO2004006311A3 WO 2004006311 A3 WO2004006311 A3 WO 2004006311A3 IB 0303497 W IB0303497 W IB 0303497W WO 2004006311 A3 WO2004006311 A3 WO 2004006311A3
Authority
WO
WIPO (PCT)
Prior art keywords
layer
lattice parameter
wafer
transfer
semiconductor material
Prior art date
Application number
PCT/IB2003/003497
Other languages
French (fr)
Other versions
WO2004006311A2 (en
Inventor
Bruno Ghyselen
Cecile Aulnette
Benedicte Osternaud
Original Assignee
Soitec Silicon On Insulator
Bruno Ghyselen
Cecile Aulnette
Benedicte Osternaud
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator, Bruno Ghyselen, Cecile Aulnette, Benedicte Osternaud filed Critical Soitec Silicon On Insulator
Priority to AU2003250462A priority Critical patent/AU2003250462A1/en
Priority to DE60329293T priority patent/DE60329293D1/en
Priority to AT03762850T priority patent/ATE443344T1/en
Priority to EP03762850A priority patent/EP1522097B9/en
Priority to JP2004519128A priority patent/JP2005532688A/en
Publication of WO2004006311A2 publication Critical patent/WO2004006311A2/en
Publication of WO2004006311A3 publication Critical patent/WO2004006311A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Abstract

Method of producing a structure comprising a thin layer of semiconductor material obtained from a wafer (10), the wafer (10) comprising a lattice parameter matching layer (2) comprising an upper layer of semiconductor material having a first lattice parameter, a film (3) of semiconductor material which has a nominal lattice parameter substantially different from the first lattice parameter and is strained by the matching layer (2), a relaxed layer (4) having a nominal lattice parameter substantially identical to the first lattice parameter, the metod comprising transfer of the relaxed layer (4) and the strained film (3) to a receiving substrate (5). Structures produced according to one of the processes according to the invention.
PCT/IB2003/003497 2002-07-09 2003-07-09 Transfer of a thin layer from a wafer comprising a buffer layer WO2004006311A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
AU2003250462A AU2003250462A1 (en) 2002-07-09 2003-07-09 Transfer of a thin layer from a wafer comprising a buffer layer
DE60329293T DE60329293D1 (en) 2002-07-09 2003-07-09 TRANSFER OF A THIN LAYER FROM A DISK WITH A BUFFER LAYER
AT03762850T ATE443344T1 (en) 2002-07-09 2003-07-09 TRANSFER OF A THIN LAYER FROM A DISC WITH A BUFFER LAYER
EP03762850A EP1522097B9 (en) 2002-07-09 2003-07-09 Transfer of a thin layer from a wafer comprising a buffer layer
JP2004519128A JP2005532688A (en) 2002-07-09 2003-07-09 Transition of thin layers from wafers with buffer layers.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0208600A FR2842349B1 (en) 2002-07-09 2002-07-09 TRANSFERRING A THIN LAYER FROM A PLATE COMPRISING A BUFFER LAYER
FR02/08600 2002-07-09

Publications (2)

Publication Number Publication Date
WO2004006311A2 WO2004006311A2 (en) 2004-01-15
WO2004006311A3 true WO2004006311A3 (en) 2004-03-04

Family

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Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/IB2003/003466 WO2004006327A2 (en) 2002-07-09 2003-07-09 Transfer of a thin layer from a wafer comprising a buffer layer
PCT/IB2003/003497 WO2004006311A2 (en) 2002-07-09 2003-07-09 Transfer of a thin layer from a wafer comprising a buffer layer

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PCT/IB2003/003466 WO2004006327A2 (en) 2002-07-09 2003-07-09 Transfer of a thin layer from a wafer comprising a buffer layer

Country Status (11)

Country Link
US (1) US6991956B2 (en)
EP (2) EP1522097B9 (en)
JP (2) JP4904478B2 (en)
KR (1) KR100796832B1 (en)
CN (1) CN100477150C (en)
AT (2) ATE443344T1 (en)
AU (2) AU2003249475A1 (en)
DE (2) DE60329293D1 (en)
FR (1) FR2842349B1 (en)
TW (1) TWI289900B (en)
WO (2) WO2004006327A2 (en)

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US6982474B2 (en) 2002-06-25 2006-01-03 Amberwave Systems Corporation Reacted conductive gate electrodes
US6953736B2 (en) 2002-07-09 2005-10-11 S.O.I.Tec Silicon On Insulator Technologies S.A. Process for transferring a layer of strained semiconductor material
US7510949B2 (en) 2002-07-09 2009-03-31 S.O.I.Tec Silicon On Insulator Technologies Methods for producing a multilayer semiconductor structure
US7018910B2 (en) * 2002-07-09 2006-03-28 S.O.I.Tec Silicon On Insulator Technologies S.A. Transfer of a thin layer from a wafer comprising a buffer layer
CN100547760C (en) * 2002-08-26 2009-10-07 S.O.I.Tec绝缘体上硅技术公司 After removing thin layer to the method for recycling of the wafer that comprises resilient coating
KR100854856B1 (en) * 2002-08-26 2008-08-28 에스. 오. 이. 떼끄 씰리꽁 오 냉쉴라또흐 떼끄놀로지 Mechanical recycling of a wafer comprising a buffer layer, after having taken a layer therefrom
US6730576B1 (en) * 2002-12-31 2004-05-04 Advanced Micro Devices, Inc. Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer
FR2861497B1 (en) * 2003-10-28 2006-02-10 Soitec Silicon On Insulator METHOD FOR CATASTROPHIC TRANSFER OF A FINE LAYER AFTER CO-IMPLANTATION
FR2867307B1 (en) 2004-03-05 2006-05-26 Soitec Silicon On Insulator HEAT TREATMENT AFTER SMART-CUT DETACHMENT
US7282449B2 (en) 2004-03-05 2007-10-16 S.O.I.Tec Silicon On Insulator Technologies Thermal treatment of a semiconductor layer
FR2867310B1 (en) 2004-03-05 2006-05-26 Soitec Silicon On Insulator TECHNIQUE FOR IMPROVING THE QUALITY OF A THIN LAYER TAKEN
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US7495266B2 (en) * 2004-06-16 2009-02-24 Massachusetts Institute Of Technology Strained silicon-on-silicon by wafer bonding and layer transfer
US6893936B1 (en) * 2004-06-29 2005-05-17 International Business Machines Corporation Method of Forming strained SI/SIGE on insulator with silicon germanium buffer
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FR2880988B1 (en) * 2005-01-19 2007-03-30 Soitec Silicon On Insulator TREATMENT OF A LAYER IN SI1-yGEy TAKEN
FR2886052B1 (en) 2005-05-19 2007-11-23 Soitec Silicon On Insulator SURFACE TREATMENT AFTER SELECTIVE ENGRAVING
FR2886053B1 (en) 2005-05-19 2007-08-10 Soitec Silicon On Insulator METHOD OF UNIFORM CHEMICAL ENGRAVING
FR2888400B1 (en) 2005-07-08 2007-10-19 Soitec Silicon On Insulator LAYER TAKING METHOD
KR100707654B1 (en) 2005-07-26 2007-04-13 동부일렉트로닉스 주식회사 Device Isolation Struture of a Semiconductor Device and Method of Forming the Same
FR2891281B1 (en) * 2005-09-28 2007-12-28 Commissariat Energie Atomique METHOD FOR MANUFACTURING A THIN FILM ELEMENT
FR2892733B1 (en) * 2005-10-28 2008-02-01 Soitec Silicon On Insulator RELAXATION OF LAYERS
US7535089B2 (en) 2005-11-01 2009-05-19 Massachusetts Institute Of Technology Monolithically integrated light emitting devices
US8063397B2 (en) 2006-06-28 2011-11-22 Massachusetts Institute Of Technology Semiconductor light-emitting structure and graded-composition substrate providing yellow-green light emission
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JP5256519B2 (en) 2007-05-03 2013-08-07 ソイテック Improved process for making cleaned strained silicon surfaces
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CN104517883B (en) * 2013-09-26 2017-08-15 中国科学院上海微系统与信息技术研究所 A kind of method that utilization ion implantation technique prepares semiconductor-on-insulator (ssoi) material
FR3064398B1 (en) * 2017-03-21 2019-06-07 Soitec SEMICONDUCTOR TYPE STRUCTURE ON INSULATION, ESPECIALLY FOR A FRONT-SIDE TYPE IMAGE SENSOR, AND METHOD FOR MANUFACTURING SUCH STRUCTURE
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Also Published As

Publication number Publication date
US20050191825A1 (en) 2005-09-01
TWI289900B (en) 2007-11-11
AU2003250462A1 (en) 2004-01-23
AU2003250462A8 (en) 2004-01-23
CN100477150C (en) 2009-04-08
ATE442667T1 (en) 2009-09-15
DE60329293D1 (en) 2009-10-29
US6991956B2 (en) 2006-01-31
FR2842349B1 (en) 2005-02-18
KR20050018984A (en) 2005-02-28
ATE443344T1 (en) 2009-10-15
AU2003249475A1 (en) 2004-01-23
WO2004006327A3 (en) 2004-03-04
DE60329192D1 (en) 2009-10-22
EP1522097B9 (en) 2010-03-03
KR100796832B1 (en) 2008-01-22
WO2004006311A2 (en) 2004-01-15
EP1535326B1 (en) 2009-09-09
JP4904478B2 (en) 2012-03-28
JP2005532688A (en) 2005-10-27
EP1522097A2 (en) 2005-04-13
CN1666330A (en) 2005-09-07
WO2004006327A2 (en) 2004-01-15
FR2842349A1 (en) 2004-01-16
JP2005532687A (en) 2005-10-27
TW200411820A (en) 2004-07-01
EP1522097B1 (en) 2009-09-16
EP1535326A2 (en) 2005-06-01

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