WO2003107419A1 - Increasing thermal conductivity of thermal interface using carbon nanotubes and cvd - Google Patents
Increasing thermal conductivity of thermal interface using carbon nanotubes and cvd Download PDFInfo
- Publication number
- WO2003107419A1 WO2003107419A1 PCT/US2003/018305 US0318305W WO03107419A1 WO 2003107419 A1 WO2003107419 A1 WO 2003107419A1 US 0318305 W US0318305 W US 0318305W WO 03107419 A1 WO03107419 A1 WO 03107419A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- nanotubes
- thermal management
- die
- layer
- array
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3732—Diamonds
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/832—Nanostructure having specified property, e.g. lattice-constant, thermal expansion coefficient
- Y10S977/833—Thermal property of nanomaterial, e.g. thermally conducting/insulating or exhibiting peltier or seebeck effect
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24942—Structurally defined web or sheet [e.g., overall dimension, etc.] including components having same physical characteristic in differing degree
- Y10T428/2495—Thickness [relative or absolute]
- Y10T428/24967—Absolute thicknesses specified
- Y10T428/24975—No layer or component greater than 5 mils thick
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/30—Self-sustaining carbon mass or layer with impregnant or other layer
Definitions
- An integrated circuit package provides increased thermal conductivity to a thermal interface between a circuit die and a thermal management solution such as a heat spreader or a heat sink by forming a chemical vapor deposited diamond surface on the thermal management solution and growing an array of carbon nanotubes on the surface of the CVDD layer or the circuit die.
- a thermal management solution such as a heat spreader or a heat sink
- Figure 1 is an elevational cross-section of a prior art stack-up schematic of a cooling arrangement for an integrated circuit package
- Figure 2 is an elevational cross-section of a CVDD enhanced prior art stack-up
- Figure 3 is a detail of the elevational cross-section of a CVDD enhanced prior art stack-up depicted in Fig 2 showing thermal interface material positioned between the CVDD layer and the die;
- Figure 4 is a detail of an elevational cross-section of an embodiment of the invention wherein a CVDD enhanced stack-up utilizes nanotubes grown on the die surface;
- Figure 5 is a detail of an elevational cross-section of a CNDD enhanced stack-up which shows nanotubes grown on the die surface and the CNDD layer;
- Figure 6 is a detail of an elevational cross section of a CNDD enhanced stack-up which shows nanotubes grown on the CVDD layer of the integrated heat spreader;
- Figure 7 is a process flow diagram of a process for coupling a circuit die to a
- Figure 8 is a process flow diagram of another process for coupling a circuit die to a thermal management aid.
- the present invention relates to a structure and a process of forming an integrated circuit package that utilizes a thermal interface material layer having an aligned array of carbon nanotubes projecting from a surface thereof.
- a bare silicon die is covered with an integrated heat spreader which is formed from a thermally conductive material such as copper and serves to laterally distribute the thermal load provided by hot spots on the die corresponding, for example, to the areas of highest transistor activity.
- FIG 1 there is shown an integrated circuit package 10 which has an interposer or substrate 12 on which a die 14 is located adjacent the substrate 12 and thermally coupled thereto through solder balls 16 which are bonded to a surface of die 14 which adjacent to substrate 12.
- the space between adjacent solder balls 16 and between the surface of die 14 and substrate 12 is generally filled with a thermally conductive gel 18.
- the combination of the thermal conductivity of solder balls 16 and thermally conductive gel 18 provides a cooling path for a portion of the heat generated by die 14.
- a copper integrated heat spreader 20 is positioned adjacent to a further surface of die 14 which is opposite to the surface of die 14 which is adjacent to substrate 12.
- An inner surface 22 of heat spreader 20 is, in prior art packages such as the one shown in Figures 1 and 2, coupled to the surface of die 14 by a first thermal interface material layer 24 which is a thermally conductive material such as thermal grease or some similar material.
- the heat spreader 20 is in thermal contact with a copper heat sink 26 through a second thermal interface 28. Ambient air 30 flows
- CVDD layer 32 between the die and the integrated spreader 20 to improve the lateral thermal conductivity of either the spreader 20 or the silicon die 14.
- CVDD layer 32 is illustrated in Figures 2 and 3 applied to the inner surface 22 of integrated heat spreader 20.
- the thermal conductivity of the copper of the integrated heat spreader is about 395 W/mK while that of the silicon die is about 100 W/mK.
- the thermal conductivity of a CVDD layer is expected to exceed 1000 W/mK. It has been found through simulations that CVDD layers having a thickness of about 450 microns can provide thermal benefits, measured as a decrease in the total junction-to-ambient thermal resistance, are approximately 10% of total for CVDD layers applied to the integrated heat spreader, 20% for the CVDD layer applied to the die and approximately 30% for combined CVDD layers on both the die and the integrated heat spreader.
- the roughness of the CVDD layer increases with increasing thickness of the CVDD layer despite the fact that increasing the thickness of the CVDD layer increases the thermal effectiveness of the layers, h the prior art, accommodation of the uneven surface of the die 14 or the inner surface 22 of the integrated heat spreader 20 as well as the lack of smoothness of the CVDD layer, whether it is applied to the die or to the integral heat spreader; a void filling thermal interface material 38 is inserted between the two.
- Figure 4 shows an embodiment of the invention where the single or double wall carbon nanotubes 40 are grown on die 14 by a plasma discharge deposition process available in the art.
- the thermal conductivity of the nanotubes 40 is in a range of about 1000 to 6000 W/m-K as compared to the conductivity of the typical thermal grease thermal interface material of about 1-7 W/m-K.
- the length of the nanotubes would typically be about 100 microns or less so that the thermal resistance of the layer would be negligible.
- the growing of the nanotubes 40 on the surface of die 14 fills the surface roughness valleys to provide a nearly uniform layer for the interface.
- a limited crush of the nanotubes 40 allows for an excellent thermal connection between the surface of die 14 and the CVDD coating 32 on inner surface 22 of heat spreader 20.
- a thermal grease may be applied to the array of nanotubes 40.
- thermal grease is not used.
- CVDD coating 32 may be formed on the surface of a heat sink 26 instead of a spreader 20.
- Figure 5 illustrates a further embodiment of the invention in which a structure has nanotubes 40 which are grown from both the CVDD surface of heat spreader 20 and the surface of die 14 using a plasma discharge method, h this embodiment the nanotubes 40 grown from and affixed to the opposed surfaces intermesh as the surfaces are mated to provide a good thermal interface, even without the use of thermal grease 38.
- thermal grease 38 can be used in combination with the carbon nanotubes 40.
- Figure 6 shows an embodiment of the invention where single or double wall carbon nanotubes 40 are grown on and affixed to the CNDD layer 32 of the integrated heat spreader 20 using a plasma discharge process.
- the grown nanotubes 40 fill in the surface roughness valleys and asperities 36 and compensate for them.
- the projecting nanotubes 40 are subject to limited crushing of the nanotubes 40 into the peak roughness features 42 of the die 14.
- no grease 38 is necessary to form the thermal interface.
- thermal grease 38 is provided in combination with the nanotubes 40.
- Figure 7 is a flow chart of an embodiment of the inventive process for enhancing heat flow from a circuit die to a thermal management aid such as a heat spreader or a heat sink.
- the first stage 72 of the process is forming a CVDD layer on a surface of thermal management aid.
- a further stage 74 an array of substantially aligned nanotubes is grown on one surface of the circuit die or on the CVDD layer on the thermal management aid.
- the thermal management aid is mounted to the die with the layer of nanotubes thermally coupling the surface of the circuit die to the CVDD layer of the thermal management aid.
- FIG 8 is a flow diagram of another embodiment of the inventive process for thermally coupling a circuit die to a thermal management aid such as a heat spreader or a heat sink.
- a thermal management aid such as a heat spreader or a heat sink.
- a CVDD layer is formed on the thermal management aid.
- a layer of nanotubes is grown on the CVDD layer.
- the thermal management aid is mounted to the die with the layer of nanotubes thermally coupling the surface of the die to the CVDD layer of the thermal management aid.
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2003237548A AU2003237548A1 (en) | 2002-06-12 | 2003-06-10 | Increasing thermal conductivity of thermal interface using carbon nanotubes and cvd |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/170,313 US6891724B2 (en) | 2002-06-12 | 2002-06-12 | Increasing thermal conductivity of thermal interface using carbon nanotubes and CVD |
US10/170,313 | 2002-06-12 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2003107419A1 true WO2003107419A1 (en) | 2003-12-24 |
Family
ID=29732468
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2003/018305 WO2003107419A1 (en) | 2002-06-12 | 2003-06-10 | Increasing thermal conductivity of thermal interface using carbon nanotubes and cvd |
Country Status (4)
Country | Link |
---|---|
US (2) | US6891724B2 (en) |
CN (1) | CN100452370C (en) |
AU (1) | AU2003237548A1 (en) |
WO (1) | WO2003107419A1 (en) |
Cited By (5)
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US7094679B1 (en) | 2003-03-11 | 2006-08-22 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Carbon nanotube interconnect |
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US8093715B2 (en) | 2005-08-05 | 2012-01-10 | Purdue Research Foundation | Enhancement of thermal interface conductivities with carbon nanotube arrays |
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US7316061B2 (en) * | 2003-02-03 | 2008-01-08 | Intel Corporation | Packaging of integrated circuits with carbon nano-tube arrays to enhance heat dissipation through a thermal interface |
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2002
- 2002-06-12 US US10/170,313 patent/US6891724B2/en not_active Expired - Fee Related
-
2003
- 2003-06-10 CN CNB038188252A patent/CN100452370C/en not_active Expired - Fee Related
- 2003-06-10 WO PCT/US2003/018305 patent/WO2003107419A1/en not_active Application Discontinuation
- 2003-06-10 AU AU2003237548A patent/AU2003237548A1/en not_active Abandoned
- 2003-12-16 US US10/738,637 patent/US20040184241A1/en not_active Abandoned
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
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US7656027B2 (en) | 2003-01-24 | 2010-02-02 | Nanoconduction, Inc. | In-chip structures and methods for removing heat from integrated circuits |
US7094679B1 (en) | 2003-03-11 | 2006-08-22 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Carbon nanotube interconnect |
US7217650B1 (en) | 2003-03-11 | 2007-05-15 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration (Nasa) | Metallic nanowire interconnections for integrated circuit fabrication |
US7273095B2 (en) | 2003-03-11 | 2007-09-25 | United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Nanoengineered thermal materials based on carbon nanotube array composites |
US7109581B2 (en) | 2003-08-25 | 2006-09-19 | Nanoconduction, Inc. | System and method using self-assembled nano structures in the design and fabrication of an integrated circuit micro-cooler |
US7784531B1 (en) | 2004-04-13 | 2010-08-31 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Nanoengineered thermal materials based on carbon nanotube array composites |
US8093715B2 (en) | 2005-08-05 | 2012-01-10 | Purdue Research Foundation | Enhancement of thermal interface conductivities with carbon nanotube arrays |
Also Published As
Publication number | Publication date |
---|---|
US20030231471A1 (en) | 2003-12-18 |
US20040184241A1 (en) | 2004-09-23 |
CN1675763A (en) | 2005-09-28 |
CN100452370C (en) | 2009-01-14 |
US6891724B2 (en) | 2005-05-10 |
AU2003237548A1 (en) | 2003-12-31 |
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