WO2003094099A1

WO2003094099A1 - System and method for measuring characteristics of a surface

Info

Publication number: WO2003094099A1
Application number: PCT/NO2003/000138
Authority: WO
Inventors: Knut Riisnaes
Original assignee: Idex Asa; DYVE, Ingvild, Juvkam; RIISNÆS, Ida, Mathilde, Marstein; RIISNÆS, Jon, Alexander, Marstein
Priority date: 2002-04-29
Filing date: 2003-04-29
Publication date: 2003-11-13
Also published as: AU2003230470A1; NO317076B1; NO20022026D0; NO20022026L

Abstract

This invention relates to a method for measuring characteristics of a surface, especially a finger surface, using a sensor unit comprising at least one stimulation electrode for applying a varying voltage or current signal to the surface, said signal having chosen characteristics, and a number of sensor elements for sensing electrical characteristics of the surface between the stimulation electrode and the sensor element.

Description

System and method for measuring characteristics of a surface

This invention relates to a system for measuring patterns in a surface, especially in finger surfaces, the system comprising a number of sensor electrodes being provided with an electrically insulating material over which the surface is to be moved, and at least one stimulation electrode for providing a varying current or voltage between the stimulation electrode and the number of sensors through the surface.

Biometrics technologies include face recognition using optical or thermal imaging; finger imaging using optical, thermal, AC- and DC-capacitive sensing; hand- geometry measurement and palm scanning; iris and retina scanning; signature recognition; and voiceprints.

Finger surface pattern detection and matching is a technique use for identification and verification of persons and of all the biometrics technologies, is the one that currently has received most attention due to its technical capabilities and low cost solutions.

International patent applications No PCT/NO01/00240 and PCTYNO98/00183 describes fingerprint skanners applying a varying voltage or current to a finger surface for detecting surface features related to the fingerprint of a user, preferably by measuring the capacitance distribution over the finger surface. The capacitance measurements of the sensor may, as is clear from the abovementioned applications, be performed in a number og different ways. It is, however, an object of this invention to provide an improved readout method for obtaining the capacitance measuments at each pixel during the measurments. The method according to this invention is characterized as described in the accompanying independent claims.

The Dual Slope principle has been used for AD converters for years due to its intrinsic noise rejection capabilities and its superb linearity. The Dual Slope AD- converters have however been used in "slow" measuring systems such as multi-metres and thermometers. In general in the dual slope principle, the current representing the input sensor voltage, is used to charge up a capacitor for a specific period of time, which is subsequently discharged to a fixed reference potential. The time for discharging the capacitor, being representative of the signal current, can be detected by means of a comparator and counter, allowing a direct analog to digital conversion. The counter value after ending discharge is hence the digital representative of the input current.

Due to the higher frequency limits in digital circuits and more accurate analog technology due to the recent developments within semiconductor technology,, e.g. as suggested in the examples included below, the dual slope principle can be applied in measuring cycles lasting for only micro seconds in stead of seconds.

The present invention thus relates to a system for real time finger surface pattern measurement being based on the system described in PCT /NO01/00240, employing the socalled Dual Slope measuring principle for use in the analog front-end of a Finger Scanner and other Bio-impedance measuring system such as the solution decribed in the abovementioned PCT application, hereafter referred to as the Dual Slope Detector (DSD).

The inventions in this patent is to use the dual slope principle not only to convert from analog to digital, but in combination with phase synchronized multiplexing (half wave rectification) as a demodulator for amplitude and phase of multi channel modulated AC-signals, in which inter channel gain and offset differences are compensated by digital normalisation. The digital normalisation is based on measurements cycles applied to a fixed common reference current or voltage.

In addition to benefiting from the Dual Slope principle intrinsic noise rejection capabilities, the DSD will hence yield a low noise, low power, minimum size and hence cost optimal, high resolution solution for multi channel AC or DC analog front-end systems.

In an AC-capacitive Finger Scanner, a low voltage Carrier signal is inserted into the finger through one or more electrodes. The output signal from the finger, referred to as input signals to the front-end system, is the actual Carrier signal modulated by the ridges valleys of a fingerprint structure.

The invention will be described below with reference to the accompanying drawing illustrating the invention by way of examples. Figure 0 Illustrates a known fingerprint sensor structure suitable for the application of the present invention.

Figure 1 Illustrates the Dual Slope principle.

Figure 2 Illustrates a first example of a circuit for a Dual Slope Detector (DSD). Figure 3 A and 3B Illustrates two variants of a second example of a DSD.

Figure 4 Illustrates an AC voltage to current converter.

Figure 5 Shows a wave form diagram for the DSD.

Figure 6 Illustrates a digital back-end for the output signals of the DSDs in a fingerprint skanner system

Figure 7 Shows an implementation of a carrier generator with delay control

Figure 8 Illustrates a system connecting a number of DSDs.

Figure 0 illustrates the known art og international patent application No PCT/NOO 1/00240 being based on a linear sensor scanning a finger surface 1 being moved over the sensor, and being constituted by a large stimulation electrode 3 for applying a voltage to the finger surface 1 and a number og sensor elements 20 for measuring the capacitance between the input sensor 3 and the sensor elements 20. The shown sensor also includes a number of sensor elements 21 for measuring the velocity of the finger 1 over the sensor.

Figure 1 shows a normalized image of a measuring cycle (one Carrier T-cycle). The Carrier cycle is divided into tree phases.

1. In phase 1 , the Carrier signal from the finger is switched on for a time equal to half the T-cycle. The signal is demodulated ("half wave rectified") and integrated. If Phase 1 starts simultaneously with the start of a sine cycle, the output of the integrator will by the end (of Phase 1) have reached a level equal to |V_0Ut|= 2I_pt/πCj_nt.

2. During Phase 2, the input channel is switched off and the integrator input is switched on to a fixed DC reference of the opposite polarity of during Phase 1. The output voltage will move back to zero with a fixed slope. The time from start of Phase 2 to zero crossing will be proportional to the output of the integrator at end of

Phase 1.

3. Phase 3 has two purposes. First it fills the time gap between completion of phase 2 and the start of the next Phase 1. Secondly, and more importantly, it keeps the output of the integrator at zero. It also yields room for gain deviation and offsets. The three phases added together must last for exactly the same amount of time as one Carrier cycle. The actual start of Phase 1 can be delayed with respect to the start of the Carrier cycle, however, this shift must be synchronously fixed. There are several reasons for introducing delay:

1. It must be possible to compensate for the over all (typical) phase shift caused by the finger and the sensor itself.

2. It must be possible to delay the phases in order to compensate for internal group delay in the analog front-end system itself, if any.

3. It must be possible to set the delay in order to discriminate on phase shifts imposed on the Carrier between the finger and the sensor if the system is intended to separate values of reactance from conductance.

It is important to observe that in order to allow a shift of Phase 1 of more than 1 quadrant of the Carrier cycle with respect to the input of the integrator, the DC reference of Phase 2 must switch polarity in order for the system to work.

Figure 2 and 3 show examples of implementation of Current sensing- and Voltage sensing DSD, respectively. Each channel Ch_x in the drawings may refer to a signal received at a sensor element 20 in figure 0, the signal applied to the stimulation electrode 3 being related to VDD. The example also includes circuitry for offset- and gain calibration. The organisation of DSDs, as well as the other modules discussed in this proposal into a system, is shown in figure 8.

It is important to note that the examples below discriminates all input channels at the same phase angel. Individual phase discrimination per channel is also possible by starting each DSD T-cycle after a time delay predefined per input channel. The actual channel phase, or T-cycle starting point, is then programmed into the digital Control Unit.

The examples below implies three operating modes: 1. Normal Operation mode, reading external sensors

2. Internal Offset Measure mode

3. Internal Gain Measure mode

The DSD principle described in this proposal is not limited by the actual examples given.

Figure 2 illustrates a current sensing DSD In normal operation mode the Channel Multiplexer (Ch. Mux) is switched to one of N input channels during Phase 1 of the measurement cycle. Assuming Phase 1 refer to the positive half of the modulated Carrier AC signal, positive current will flow into the integrator capacitor (Cint). This will force the output of Al negative. Since time is fixed, the output voltage amplitude of Al after ending Phase 1 will be proportional to - 2I_p/π (the average amplitude of a half sine) if a synchronous sine wave is detected, or 0 if a synchronous cosine is detected.

During Phase 2, the Ref_en switch will be turned on. This will enable a constant negative current to flow into Cint, forcing the output of Al back to zero with a constant slope.

The output of comparator A2 is positive as long as the output of Al is more negative than Vm.

Ph2_en enables T_out to be valid only during Phase 2. Ph2_en will be switched off during Phase 3. Ph3_en will be turned on for the rest of the cycle, short circuiting C;_nt.

Rshunt is the internal impedance of the short switch.

Offset and Gain Measure for Calibration and Normalisation

During Offset Measure all the inputs to the integrator is turned off during Phase 1. The output of the integrator will slope according to input offset current. The pulse length of T_out will be proportional to the integrator offset plus the comparator offset. In order to avoid negative input offset current (which would not be possible to compensate digitally without affecting the gain), a fixed positive offset current (Ioffs.) may be added. The digital readout based on T_out is stored as offset value in memory for further digital processing.

During Gain Measure, a constant current is switched on to the input of the integrator. The resulting digital readout based on T_out is stored as gross gain value in memory for further digital processing.

The actual calibration is done in the digital back end of the system. The individual offset values are subtracted from the gross gain values, yielding net gain values. A defined digital value is then divided by the net gain value in order to create the gain factor for the channel. If the net channel gain was larger than defined the gain factor will be less than one. If gain was lower than defined, the gain factor will be larger than one.

During Normal operating mode, the values measured on each input electrode will be digitally normalised by first subtracting the individual offset value and then multiplied by the individual gain factor.

Figure 3A and 3B illustrates two equivalent voltage sensing DSDs.

In normal operation mode the Channel Multiplexer (Ch. Mux) is switched to one of N input channels during Phase 1 of the measurement cycle. A voltage follower is inserted between the Ch. Mux and the integrator. This creates a high input impedance for the modulated Carrier AC signals.

Assuming Phase 1 refer to the positive half of the Carrier, a positive current will flow into the integrator capacitor (Cint.). This will force the output of Al negative. Since time is fixed, the output voltage amplitude of Al after ending Phase 1 will be proportional to -2V_p/π (the average amplitude of a half sine wave) if a synchronous sine wave is detected, or 0 if a synchronous cosine is detected.

The circuitry for, and operation of phases 2 and 3 are the same as for the current sensing DSD described previously.

Offset and Gain Measure for Calibration and Normalisation

During Offset Measure, Vm is turned on to the input of the voltage follower during Phase 1. The output of the integrator will slope according to the input voltage offset of the voltage follower and the input current offset of the integrator. The pulse length of T_out will be proportional to the offsets at the integrator plus the comparator offset. In order to avoid negative input offset current (which would not be possible to compensate digitally without affecting the gain), a fixed positive offset current (Ioffs.) may be added. The digital readout based on T_out is stored as offset value in memory for further digital processing.

During Gain Measure, a constant AC-current is switched on individually to each of the input channels. This is necessary in order to compensate for the individual parasitic capacitances of the input channels as well as the Ch. Mux output, since the virtual ground of the integrator input is separated by the high impedance voltage follower input. The resulting digital readout based on T_out is stored as gross gain value in memory for further digital processing.

The digital calibration and normalisation is the same as for Current sensing. Figure 4 illustrates an AC voltage to current converter in which the AC output current, I_p sin ω t is generated by input voltage V_psin ωt from the drive ring (DR) generator. The amplitide of the output current is defined by selecting the proper values for Rl, R2 and R3. In some cases R2 and R3 may not be necessary.

Figure 5 illustrates a wave form diagram for the DSD, the curve for output of Al shows the wave form for a complete Carrier T-cycle when measuring a sine wave synchronous to the start of Phase 1.

Phase 2 enable (Ph2_en) is high during Phase 2. The output of the comparator A2 is high as long as Al is less than Vm. Phase 3 enable (Ph3_en) goes high when a "high to low transition" is detected at the A2 output. Ph3_en stays high until end of the T-cycle (start of next Phase 1). T_out goes active when Phase 2 starts and goes inactive in Phase 3. The pulse width of T_out is proportional to the measured signal amplitude at the input of the integrator.

By enabling a digital, binary counter with T_out, the counter will give a digital read out in the end of the cycle, proportional to the input signal amplitude. The digital resolution of the signal is defined by the clock frequency (and number of bits) of the counter. This is explained in more details in the digital section.

Calculation example for Current sensing where Tc = lOμs and fc = lOOKHz:

Phase 1 (t = 5μs)

V_0Ut = l/Cfat J l dt

I = I_p sin(2π/T)t

Vout = V nt J sin(2π/T)t dt

Solving the integral from 0 to t, defining T = 2t

Vout = Ip Cint (2t/2π) (cos(0) - cos(π)) V_0ut = 2I_pt/πC int

Solving for Ci_nt: Cint ⁼ 2I_pt/πV₀ut Setting I_p = 0,07μA; V_out = 0,1V; t = 5μs:

C_int = 2(0,07μA)(5μs)/π(0,lV) = 2,23pF

Phase 2 (W = 4μs)

V_out = l/(R_refC) l V_ref dt V_0Ut = V_reft/(R_refC)

Setting V_ref = 1,2V; V_out = 0,1V; t = 4μs:

Solve for R_ref:

R_ref = V_ref t/(V_0UtC) = (l,2V)(4μs)/(0,lV)(2,23pF) = 21.5MΩ

Since this value is not practical inside an ASIC, V_ref could be divided by 100 through a voltage divider so that R_ref can be set to 215KΩ.

Phase 3 (tmi_n = lμs)

Rshunt is the Ron of the shunting transmission gate. R_Shunt » 1,5KΩ

Figure 6 show an example of a digital back-end for a Finger Scanner sub system. Each group (DSD) is connected to an individual binary counter. The number of bits represented in each counter corresponds to the digital resolution needed for the measurements. The counter counts during phase 2 for the time defined by the pulse length of

T_out. The digital values of each counter is shifted out during next Phase 1 and into the Normalisation block.

Alternatively, in a low power application, only one counter may be used, starting at the beginning of Phase 2. Each T_out, high to low transition, laches/clocks/enables the output of the counter into an individual register. The content of the registers will then be mux'ed into the Normalisation block during next Phase 1.

During Offset and Gain measure, the digital data are stored into the RAM.. During Calibration Mode, these data are used for calculating the Gain Factors.

During Normal Operation mode, the incoming data to the Normalisation module is subtracted by individual offset value and multiplied with the individual gain factor before the data is transferred to the I/O port. The Control module controls the counters as well as the DSDs and input multiplexers.

The actual system clock frequency will depend on the system requirements. For high resolution digital readout, a high clock frequency is required for the counters.

Using the 4μs used for Phase 2 in the previous example, the following clock frequency' s are needed for the stated resolutions :

10 bit resolution: 1024/4μs = 256MHz

8 bit resolution: 256/4μs = 64MHz

6 bit resolution: 16/4μs = 16MHz In a Finger Scanner system, 6 bit digital resolution will usually be sufficient. In the given example, Phase 3 corresponds to 20% extra time beyond Phase 2.

This means that if 6 bit corresponds to the max input signal, Phase 3 will yield a head- rom for a maximum of +20% offset and gain deviation (overhead) within thelόMHz clock constraint for T = lOμs. This also means that in a 6 bit system, each counter must be min. 7 bits (in order to count the overhead). The overhead is later removed during Normalisation. A small portion of Phase 3 should always be fixed. This is required to avoid a high overhead to continue Phase 2 into next Phase 1.

For accomplishing a higher resolution with, or without, more overhead, a higher clock frequency will be needed.

If higher resolution and/or overhead is required, with a max 16 MHz clock frequency, aside from using an internal PLL to speed up frequency for the counters, several hybrid solutions can be mentioned.

The DSD can be modified so that the integrator output during Phase 2 remains at a constant output level. The outputs of the integrators can then be multiplexed and fed into a regular ADC with a much faster conversion rate, such as an Successive Approximation ADC. The integrators will be reset during Phase 3. If drifting of the integrator is a problem during Phase 2, or Phase 2 must be extended beyond Phase 3 , inserting S/H elements between the integrator and the second multiplexer may be a choice. These hybrid solutions will, however, have a higher sensitivity to noise, as well as require a larger silicon die size and higher power consumption than the original DSD described in this document. Other hybrid solutions may also be possible still within the scope of this proposal.

Carrier Generation and Phase Control

As previously mentioned, the Carrier and the three phases of the DSD must be synchronised but with an adjustable time delay between the two.

Figure 7 shows a possible implementation of a Carrier generator with delay control. The delay is set as a digital byte into the Phase Register. As the counter increments, the Phase Controller (state machine) will detect when the counter equals the byte in the Phase Register. When equal, the Phase Controller will start cycling synchronously to the Counter, emitting Ph2_en after half a T-cycle. Ph3_en will go high at once A2 goes low and stay high until the end of the T_cycle. If A2 fails to go low (too high overhead on the DSD, Ph3_en is forced high close to the end of the T_cycle, regardless.

The output of the counter is fed into a look-up table (LUT) which converts the linear ramp to a digital sine representation. This digital sine is then converted to an analog sine wave by the DAC, before it is buffered and Low pass filtered and output as the Carrier.

Figure 8 shows an example connecting the different modules described into a system, such as the SmartFinger™ module as described in the abovementioned international patent application No PCT /NOOl/00240.

In this case 276 output sensors are organised into 12 DSD modules. Other organisations with a higher number of input electrodes, as well as a higher or lower number of output sensors (input signals to the front-end system), is still within the scope of this proposal.

Claims

C l a i m s

1. Method for measuring characteristics of a surface, especially a finger surface, using a sensor unit comprising at least one stimulation electrode for applying a varying voltage or current signal to the surface, said signal having chosen characteristics, and a number of sensor elements for sensing electrical characteristics of the surface between the stimulation electrode and the sensor element, the method comprising the steps of:

• at a chosen amplitude of the applied signal, coupling at least one sensor element to an associated capacitor, the voltage or current at the sensor element thus charging the capacitor,

• after a chosen part of the period coupling the capacitor from the sensor element to a defined fixed voltage potential via a resistor or directly to a defined fixed current source, • measuring the time period from the coupling of the capacitor to the chosen voltage till the arrival of the capacitor voltage at a chosen value, the measured time being indicative of the amplitude of the signal received by the sensor element.

2. Method according to claim 1, wherein the coupling of the sensor element to the capacitor is performed when the amplitude of the received signal is zero and that the capacitor is coupled to the chosen voltage after Vi period of the received signal.

3. Method according to claim 2, wherein the capacitor is short circuited after the arrival of the capacitor voltage at the chosen value, the short circuit being maintained for a time period corresponding to the period of the signal minus ! period of the signal and the measure time period, possibly plus a chosen number of periods of the signal.

4. System for measuring the characteristics of a surface, especially a finger surface, comprising at least one stimulation electrode connected to means for applying a varying voltage or current signal to the surface, said signal having chosen characteristics, and a number of sensor elements for sensing electrical characteristics of the surface between the stimulation electrode and the sensor element, comprising:

• a capacitor coupled to each of a number of sensor elements and means for coupling of the the sensor elements to the capacitors at chosen times, • coupling means for disconnecting the capacitors from the sensor elements an coupling of the capacitors to generator means for providing a reference voltage,

• voltage measuring means for measuring the voltage over the capacitor, and

• timer means for measuring the time period from the coupling of the capacitor to the chosen voltage till the arrival of the capacitor voltage at a chosen value, the measured time being indicative of the amplitude of the signal received by the sensor element.

5. System according to claim 4, comprising measuring means connected to each sensor element for coupling the sensor element to the capacitor when the received signal is zero, and coupling of the the capacitor to the chosen voltage after ^lA period of the received signal, the charge of the capacitor thus corresponding to an integral over Vz period of the received signal.