WO2003093848A1

WO2003093848A1 - Method and device for use in dc parametric tests

Info

Publication number: WO2003093848A1
Application number: PCT/CA2003/000635
Authority: WO
Inventors: Gordon W. Roberts; Clarence K. L. Tam
Original assignee: Mcgill University
Priority date: 2002-05-03
Filing date: 2003-04-29
Publication date: 2003-11-13
Also published as: US20030206127A1; AU2003222702A1; US20040246002A1; US6727834B2; US6917320B2

Abstract

A system and device suitable for use in performing a DC parametric test on an external load is provided. The device may be configured to apply a desired voltage or current to the external load. The circuit device receives a forcing parameter signal at an input (202) and releases at an output a signal approximating the forcing parameter signal to the external load. The circuit device includes a first circuit segment between the input and the output having a search unit (199), an intermediate voltage point (214) and an internal load (216) between the intermediate voltage point and the output. A second circuit segment connected in a feedback arrangement with the first circuit segment provides the search unit with the voltage at the output. The search unit is adapted for generating a second voltage signal on the basis of the forcing parameter signal and the first voltage signal received and to apply the second voltage signal to the intermediate voltage point. The application of second voltage signal to the intermediate voltage point causes a change in either one of the voltage signal or the current signal at the output such that a signal approximating the forcing parameter signal is caused at the output. A current measuring circuit adapted for providing a measure of the current at the external load suitable for use with a voltage generating circuit device is also provided.

Description

TITLE: METHOD AND DEVICE FOR USE IN DC PARAMETRIC TESTS

FIELD OF THE INVENTION

The present invention relates generally to electronic chips and devices, and more particularly, to a method and device suitable for use in performing DC parametric tests.

BACKGROUND OF THE INVENTION

Recent years have seen a rapidly increasing demand for highly integrated mixed- signal integrated circuits (IC's). This demand is mostly driven by the ever-expanding communications industry. However, as the level of integration increases, more and more mixed-signal components are becoming buried deep inside large amounts of digital circuitry without any external I/O access. This creates a difficult problem for initial device and circuit characterisation and diagnosis, as well as during a production test. For example, to measure the bias current for a high precision ADC circuit requires some form of external access. However, the access mechanism, such as a test bus, can introduce additional noise from off-chip sources.

Typically circuit characterisation includes the determination of the electrical characteristics of a circuit such as for example measuring the input/output impedance of an amplifier circuit, or finding the voltage transfer characteristics of an amplifier circuit or transistor device amongst others.

One particular area of IC testing that is being affected is the DC parametric tests. These tests are typically conducted to characterise a wide variety of mixed-signal circuits such as Analog-to-Digital Converters (ADCs), PLLs and bias networks. Also, these tests are used in digital test applications such as pad current leakage and I_DDQ tests. For example, the pad current leakage test and the IDDQ test are common test techniques for detecting faults in digital ICs. DC parametric tests are generally classified as one of two types. The first type of DC parametric test involves forcing a voltage at a circuit node while measuring the current that flows into the node. Commonly used method for on-chip current measurements include using device having either a transimpedance amplifier, as shown in figure la), an integrating network as shows in figure lb) or a shunt resistance, as shown in figure lc). For additional information regarding the above mentioned methods, the reader is invited to refer to the following documents:^"

1. Teradyne, Inc., "Low Current Ammeter Channel Card", Advanced Mixed- Signal Instrumentation Manual, 1996.

2. C. D. Thompson, S. R. Bernadas, "A Digitally-Corrected 20b Delta- Sigma Modulator", Proc. IEEE International Solid-State Circuits Conference, pp. 194-195, 1994.

3. U.S. Patent No. 5,274,375 issued to Charles D. Thompson December 28, 1993;

4. M. Breten, T. Lehmann, E. Bruun, "Integrating Data Converters for Picoampere Currents from Electrochemical Transducers", Proc. IEEE International Symposium on Circuits and Systems, Vol. 5, pp. 709-712, May 2000. 5. C. B. Wang, J. Todsen, T. Kalthoffi "A Dual Channel 20 Bit Current-Input

A/D Converter for Photo-Sensor Applications", Proc. Southwest Symposium on Mixed-Signal Design, pp. 57-60, 2000.

6. Burr-Brown Product # DDC112

7. J. Kotowski, B. Mclntyre, J. Parry, "Current Sensor IC Provides 9 bit + Sign Result without External Sense Resistor", Proc. IEEE Custom

Integrated Circuits Conference, pp. 35-38, 1998;

8. U.S. Patent No. 5,867,054 issued to Jeffrey P. Kotowski February 2, 1999;

9. National Semiconductor Product # LM3814

The contents of the above documents are hereby incorporated by reference.

A deficiency of devices of the type described above is that they involves the use of elaborate Analog-to-Digital Converters (ADCs) with trimmed components, which makes these devices expensive and relatively non-scalable for on-chip implementation. Another deficiency of devices of the type described above is that they make use of op-amps (operational amplifiers) which also makes them relatively non-scalable for on-chip implementation. Generally, the size of the op-amp circuit does not shrink to the same extent as the size of logic circuits do as IC technology advances.

The second type of DC parametric test involves forcing a known current into a circuit node while measuring the voltage at the node!

A deficiency of commonly used on-chip current sources is that they generally suffer from low output resistance and shifts in current levels due to process variation. Such current sources are described in W. Sansen et al., "A CMOS Temperature- Compensated Current Reference", IEEE Journal of Solid-State Circuits, Vol. 23, pp. 821-824, June 1988 and in H. J. Oguey et al., "CMOS Current Reference Without Resistance", IEEE Journal of Solid-State Circuits, Vol. 32, pp. 1132-1135, July 1997 whose contents are herein incorporated by reference. Other on-chip current source implementations, of the type described in Burr-Brown Corporation, "Dual Current Source/Current Sink", REF200 (Datasheet), Oct. 1993 and in U.S. Patent No. 4,792,748 issued to David M. Thomas et al. in December 20, 1998, can generally achieve good current accuracy but require laser-trimmed on-chip resistors, which is costly when multiple measurement units are required on a single chip. The contents of the above documents are hereby incorporated by reference.

In the context of the above, there is a need in the industry to provide a method and device for use in performing DC parametric tests that alleviates at least in part problems associated with the existing devices and methods.

SUMMARY OF THE INVENTION

In accordance with a first broad aspect, the invention provides a circuit device suitable for use in performing a DC parametric test on an external load. The circuit device includes an input suitable for receiving a forcing parameter signal, an output suitable for releasing to the external load a signal approximating the forcing parameter signal, a first circuit segment and a second circuit segment. The first circuit segment is located between the input and the output and includes a search entity, an intermediate voltage point and an internal load between the intermediate voltage point and the output of the circuit device. The second circuit segment is connected in a feedback arrangement with the first circuit segment. The second circuit segment provides the search entity in the first circuit segment with a first voltage signal indicative of the voltage at the output of the circuit device. The search entity is adapted for generating a second voltage signal on the basis of the forcing parameter signal and the first voltage signal received from the second segment and for applying the second voltage signal to the intermediate voltage point. The application of the second voltage signal to the intermediate voltage point causes a change in either one of the voltage signal or the current signal at the output of the circuit device such that, at equilibrium, a signal approximating the forcing parameter signal is caused at the output.

In accordance with another broad aspect, the invention provides a circuit for performing a DC parameter test on an external load. The circuit comprises a circuit input, a circuit output, a search unit, a circuit module having digital-to-analog conversion functionality and load functionality and an analog-to-digital converter (ADC). The circuit input is for receiving a forcing parameter signal. The circuit output is for connection to the external load. The search unit has a first input connected to the circuit input and has a second input and an output. The circuit module has digital-to-analog conversion functionality and load functionality and is connected between the output of the search unit and the circuit output. The analog-to- digital converter (ADC) is connected between the circuit output and the second input of the search unit. The search unit is adapted to generate a digital target voltage at its output on the basis of a voltage at the circuit output and the forcing parameter signal whereby a signal approximating the forcing parameter signal is derived at the circuit output. Advantageously, the above-described circuit can be implemented using some digital logic as permitted by the use of ADCs and DACs. The digital logic allows taking advantage of the down-scaling of digital integrated circuit technology and facilitates the on-chip implementation of such devices.

In accordance with a specific example implementation, the forcing parameter signal is a forced voltage signal.

In accordance with an alternative specific example implementation, the forcing parameter signal is a forced current signal.

Specific examples of implementation may make use of a forcing parameter signal that is in either one of an analog format or digital format.

In a specific example of implementation, the circuit module having digital-to-analog conversion functionality and load functionality includes a low-pass filter module one side of which is connected to the circuit output and a pulse generator module connected between the output of the search unit and another side of the low-pass filter module.

In an alternate specific example of implementation, the circuit module having digital- to-analog conversion functionality and load functionality includes an internal load one side of which is connected to the circuit output and a digital-to-analog converter (DAC) connected between the output of the search unit and another side of the internal load.

In accordance with a first non-limiting implementation, the internal load in the circuit device is a linear non-inverting load. Such a linear non-inverting load may include one or more linear resistor elements, RC (resistor/capacitor) circuit elements and any other suitable linear analog circuit having linear non-inverting properties. Such linear analog circuits having linear non-inverting properties may include non-linear components arranged in such a manner to produce a linear non-inverting load. Such non-linear components may include for example PMOS circuits, NMOS circuits, CMOS circuits, BJT circuits, BiCMOS circuits, JFET circuits and MESFET circuits.

In accordance with a second non-limiting implementation, the internal load in the circuit device is a non-linear and inverting load. Such a non-linear and inverting load may include one or more MOS elements, BJT circuits, JFET circuits, diode circuits, MESFET or BiCMOS circuits. MOS configurations including a CMOS circuit, a PMOS circuit and NMOS circuit may also be used.

In accordance with a third non-limiting implementation, the internal load in the circuit device is a non-linear and non-inverting load. Such a non-linear and non-inverting load may include one or more MOS elements, BJT circuits, JFET circuits, diode circuits, MESFET or BiCMOS circuits.

In accordance with a fourth non-limiting implementation, the internal load in the circuit device is a linear and inverting load. Such a linear and inverting load may include one or more MOS elements, BJT circuits, JFET circuits, MESFET or BiCMOS circuits.

Advantageously, by using a non-linear internal load, larger changes in current at the output can be established for a smaller corresponding change in voltage applied at the output. In addition, the downscaling of digital circuit will limit the power supply to lower voltage levels, which in turn will limit the output voltage range of analog circuits. Consequently, circuits of the type described above making use of a non- linear internal load will be affected to a lesser extent by reductions in power supply voltages.

In a specific non-limiting example of implementation where the forcing parameter signal is a forced voltage signal, the search unit includes a digital comparator, a digital integrator module and an output. The digital comparator is for generating a digital difference voltage signal dependent on the difference between the forced voltage signal and the digital approximation of the voltage signal at the output of the circuit device. The digital integrator module is adapted for processing the digital difference voltage signal to derive the digital target voltage. The digital target voltage is released at the output of the search unit for processing by the digital-to-analog converter module. Where the forcing parameter signal is an analog signal, the search unit further includes an analogue-to-digital converter module for processing the forced voltage signal to generate a corresponding digital forced voltage signal. The digital forced voltage signal is then provided to the digital comparator.

In accordance with a specific example of implementation, the analog-to-digital converter module in the circuit device includes an analog comparator, a digital integrator and a feedback circuit. The analog comparator receives a signal indicative of the voltage at the output and a tracking voltage and generates a difference signal on the basis of the signals received. The digital integrator receives the difference signal and generates successive digital approximations of the voltage signal at the output of the circuit device. The feedback circuit processes the successive digital approximations of the voltage signal to generate the tracking voltage and provide the tracking voltage to the analog comparator. In a non-limiting implementation, the feedback circuit includes a digital-to-analog converter module. In accordance with an alternative specific example of implementation, the digital integrator in the analog-to- digital converter module is replaced by a successive-approximation circuit (SAR) module. For additional information regarding successive-approximation circuits (SAR), the reader is invited to consult D. A. Johns, K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, Inc., pp. 492-493, 1997. The content of this document is hereby incorporated by reference.

In accordance with another broad aspect, the invention provides a system for providing a current measurement suitable for use in performing a DC parametric test on an external load. The system includes a voltage generating circuit device and a current measurement circuit. The voltage generating circuit device includes an input for receiving a signal indicative of a forced voltage, an output suitable for releasing to the external load a signal approximating the forced voltage, a first circuit segment and a second circuit segment. The first circuit segment is between the input and the output and includes a search unit, an intermediate voltage point and an internal load between the intermediate voltage point and the output. The second circuit segment is connected in a feedback arrangement with the first circuit segment. The second circuit segment provides the search unit in the first circuit segment with a first voltage signal indicative of the voltage at the output. The search unit is adapted for generating a second voltage signal on the basis of the signal indicative of the forced voltage and the first voltage signal received from the second segment and applying the second voltage signal to the intermediate voltage point. The application of the second voltage to the intermediate voltage point causes a change in either one of the voltage signal or the current signal at the output such that, at equilibrium, a voltage approximating the forced voltage is caused at the output. The current measurement circuit includes a first input for receiving a first signal derived from the second voltage signal, a second input for receiving a second signal derived from the signal indicative of the forced voltage signal, search logic and an output. The search logic derives a certain current measurement on the basis of the first signal and the second signal. The certain current measurement is released at the output of the current measurement circuit. When the system is in equilibrium, the certain current measurement is indicative of an approximation of measurement of the current flowing at the output of the voltage generating circuit when the signal indicative of the forced voltage is applied to the output of the voltage generating circuit.

In accordance with a non-limiting example, the first signal derived from the second voltage signal includes a digital representation of the second voltage signal and the second signal derived from the signal indicative of the forced voltage includes a digital approximation of the signal indicative of the forced voltage.

In accordance with another broad aspect, the invention provides a system for providing a current measurement for use in performing a DC parametric test on an external load. The system includes a voltage generating circuit device and a current measurement circuit. The voltage generating circuit device includes a circuit input, a circuit output, a search unit, a circuit module having digital-to-analog conversion functionality and load functionality and an analog-to-digital converter (ADC). The circuit input is for receiving a signal indicative of a forced voltage. The circuit output is for connection to the external load. The search unit has a first input connected to the circuit input and has a second input and an output. The circuit module having digital-to-analog conversion functionality and load functionality is connected between the output of the search unit and the circuit output. The analog-to-digital converter (ADC) is connected between the circuit output and the second input of the search unit. The search unit is adapted to generate a digital target voltage at its output on the basis of a voltage at the circuit output and the signal indicative of the forced voltage whereby a signal approximating the forced voltage is applied at the circuit output. The current measurement circuit includes a first input for receiving a first signal derived from the digital target voltage, a second input for receiving a second signal derived from the forced voltage signal and a search logic module. The search logic module is coupled to the first and second inputs and derives a certain current measurement on the basis of the first signal derived from the digital target voltage and the second signal derived from the forced voltage signal and a search logic module. When the system is in equilibrium, the certain current measurement is indicative of an approximation of measurement of the current flowing at the output of the voltage generating circuit when the signal approximating the forced voltage is applied to the output of the voltage generating circuit. The certain current measurement is released at an output of the current measurement circuit.

In a specific implementation, the circuit module having digital-to-analog conversion functionality and load functionality includes a low-pass filter module one side of which is connected to the circuit output and a pulse generator module connected between the output of the search unit and another side of the low-pass filter module.

In an alternative specific implementation, the circuit module having digital-to-analog conversion functionality and load functionality includes an internal load one side of which is connected to the circuit output and a digital-to-analog converter (DAC) connected between the output of the search unit and another side of the internal load.

In accordance with a specific implementation, the search logic of the current measurement circuit includes a data structure having a plurality of entries, each entry providing a mapping between a data element conveying a given target voltage and data element conveying a given the forced voltage to a corresponding current measurement. The data structure may be stored on any suitable memory unit such as a RAM, ROM, PROM, EPROM and EEPROM. In a specific non-limiting implementation, the data structure is stored on a RAM device.

Advantageously, the search logic captures the DC transfer characteristic of the internal load at different current levels. Once known, the transfer characteristic of the internal load can be used indirectly to determine the value of an unknown current level at the output of the circuit device when the output is connect to an external load.

In accordance with yet another broad aspect, the invention provides a current generating circuit device suitable for use in performing a DC parametric test on an external load. The circuit device includes a circuit input, a circuit output, a search unit, a circuit module having digital-to-analog conversion functionality and load functionality and an analog-to-digital converter (ADC). The circuit input is for receiving a signal indicative of a forced current. The circuit output is for connection to the external load. The search unit has a first input connected to the circuit input and has a second input and an output. The circuit module having digital-to-analog conversion functionality and load functionality' is connected between the output of the search unit and the circuit output. The analog-to-digital converter (ADC) is connected between the circuit output and the second input of the search unit. The search unit is adapted to generate a digital target voltage at its output on the basis of a voltage at the circuit output and the signal indicative of a forced current whereby a signal approximating the signal indicative of a forced current is derived at the circuit output.

In accordance with a specific example, the circuit module having digital-to-analog conversion functionality and load functionality includes a low-pass filter module one side of which is connected to the circuit output and a pulse generator module connected between the output of the search unit and another side of the low-pass filter module. In accordance with an alternate example, the circuit module having digital-to-analog conversion functionality and load functionality includes an internal load one side of which is connected to the circuit output and a digital-to-analog converter (DAC) connected between the output of the search unit and another side of the internal load.

In accordance with a specific example of implementation, the search unit includes a data structure having a plurality of entries, each entry providing a mapping between:

1. a data element conveying the voltage signal at the output of the circuit device; and

2. a data element conveying a given forced current and a data element conveying a target voltage.

In a non-limiting implementation, the data structure may be stored on any suitable memory unit such as, but not limited to, a RAM, ROM, PROM, EPROM and EEPROM. In a specific embodiment, the memory unit is stored on a RAM.

In accordance with an alternative implementation, the search unit provides a data structure having a plurality of entries, each entry providing a mapping between: 1. data elements conveying voltage signals at the output and a data element conveying a given forced current signal; and 2. data elements conveying target voltage values.

These and other aspects and features of the present invention will now become apparent to those of ordinary skill in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings: Figures la, lb and lc show examples of prior art circuit devices for on-chip current measurements; Figures 2a and 2b show circuit devices suitable for use in performing a DC parametric test on an external load in accordance with non-limiting examples of implementation of the invention;

Figure 3 is a graph showing the DC characteristics of internal load of the circuit device shown in figure 2b in accordance with a non-limiting example of implementation of the invention; Figure 4a and 4b show specific example of implementation of the internal load of the circuit device shown in figure 2b in accordance with a non-limiting example of implementation of the invention; Figure 5 is a graph showing the DC characteristics of external load R₂ in accordance with a non-limiting example of implementation of the invention; Figure 6 is a graph showing on a same graph the load lines of internal load Ri and the load line of internal load R₂ depicted in figures 3 and 5 when the loads

Ri_. and R₂ are connected in series; Figure 7 is a graph showing the location of the desired voltage to apply to the intermediate voltage point V_DA_C shown in figure 2b of the drawings for a desired forcing parameter voltage signal N_for_ce in accordance with a specific example of implementation of the invention;

Figure 8 shows the circuit device of figure 2b adapted for searching for a voltage to apply to intermediate voltage point V_DAC for a desired forcing parameter voltage signal Nf_orce in accordance with a non-limiting example of implementation of the invention; Figure 9 is a graph showing the DC characteristics of internal load Ri of the circuit device shown in figure 2b and showing the location of the current measurements in accordance with a non-limiting example of implementation of the invention; Figure 10 is a graph illustrating a function mapping a forcing parameter signal N_fo_rce and the voltage to apply to intermediate voltage point VDA_C to a current value at the output of the circuit device shown in figure 8 in accordance with a non-limiting example of implementation of the invention; Figure 11 shows the circuit device of figure 8 adapted for further providing a current measurement value in accordance with a non-limiting example of

• implementation of the invention;

Figure 12 shows a calibration circuit for calibrating the circuit device shown in figure 8 in accordance with a non-limiting example of implementation of the invention;

Figure 13 is a graph showing a plot of k _DA_C VS. I_outin accordance with a non-limiting example of implementation of the invention; Figure 14 shows a test circuit for calibrating the circuit device shown in figure 8 including a test current reference I_test in accordance with a non-limiting example of implementation of the invention; Figure 15 shows an alternate calibration circuit for calibrating the circuit device shown in figure 8 in accordance with a non-limiting example of implementation of the invention; Figure 16 shows the circuit device of figure 2b adapted for searching for a voltage to apply to intermediate voltage point V_DAC for a desired forcing parameter current signal I_force in accordance with a non-limiting example of implementation of the invention; Figure 17 is a graph showing the location of a desired voltage to apply to intermediate voltage point V_ADC for a desired forcing parameter current signal I_fo_rce in accordance with a non-limiting example of implementation of the invention; Figure 18 shows the circuit device of figure 2b adapted for forcing a voltage at output N_ADC for a desired forcing parameter voltage signal I_fo_rce in accordance with a non-limiting example of implementation of the invention;

Figure 19 is a graph showing the location of a desired voltage to apply to output VA_DC for a desired forcing parameter current signal I_out⁼If_orce in accordance with a non-limiting example of implementation of the invention; Figure 20 is a graph showing the DC characteristics of internal load Ri of the circuit device shown in figure 2b and showing the location of the voltage measurements for I₀ut⁼If₀rce in accordance with a non-limiting example of implementation of the invention; Figure 21 is a graph illustrating a function "H" mapping a forcing parameter signal

I_fo_rce and the voltage to apply to intermediate voltage point VDAC to a voltage value at the output of the circuit device shown in figure 16 in accordance with a non-limiting example of implementation of the invention;

Figure 22 is a graph illustrating a function "H^"1" mapping forcing parameter signal I_fo_rce and to a voltage value at the output of the circuit device shown in figure 16 to a voltage to apply to intermediate voltage point V_DAC accordance with a non-limiting example of implementation of the invention;

Figures 23 a), b), c) and d) show four alternate specific examples of implementation of the circuit device of figure 2b adapted for searching for a voltage to apply to intermediate voltage point VDA_C or V_ADC for a desired forcing parameter voltage signal I_fo_rce in accordance with non-limiting examples of implementation of the invention;

Figures 24 and 25 are graphs showing on a same plot the load lines of internal load Ri_. and the load line of internal load R₂ when the loads Ri and R₂ are connected in series in accordance with a non-limiting example of implementation of the invention; Figure 26 shows an alternate specific example of implementation of the circuit device of figure 2b adapted for searching for a voltage to apply to intermediate voltage point V_DAC for a desired forcing parameter voltage signal I_force in accordance with a non-limiting example of implementation of the invention; Figure 27 and 28 show portions of calibrating circuits for calibrating the circuit device shown in figure 23 in accordance with a non-limiting example of implementation of the invention;

Figure 29 shows the circuit device of figure 2b adapted for searching for a voltage to apply to intermediate voltage point V_DAC for a desired forcing parameter voltage signal N_fo_rce in accordance with a non-limiting example of implementation of the invention where the internal load R_\ is an inverting load; 1.5

Figure 30 shows a modified version of the calibration circuit of figure 15 adapted for an inverting internal load Ri in accordance with a non-limiting example of implementation of the invention; Figure 31 shows a modified version of the calibration circuit of figure 18 adapted for an inverting internal load Ri in accordance with a non-limiting example of implementation of the invention; Figure 32 shows a modified version of the calibration circuit of figure 23a) adapted for an inverting internal load Ri in accordance with a non-limiting example of implementation of the invention; Figure 33 shows a modified version of the calibration circuit of figure 23b) adapted for an inverting internal load Ri in accordance with a non-limiting example of implementation of the invention; Figure 34 shows a modified version of the calibration circuit of figure 23 c) adapted for an inverting internal load Ri in accordance with a non-limiting ' example of implementation of the invention;

Figure 35 shows the circuit device of figure 2b adapted for forcing voltage V_DAC on the basis of a forcing parameter including a linear resistive internal load

Ri in accordance with a non-limiting example of implementation of the invention; Figure 36 shows the circuit device of figure 2b adapted for forcing voltage VA_DC on the basis of a forcing parameter including a linear resistive internal load

Ri in accordance with another non-limiting example of implementation of the invention; Figure 37 shows the circuit device of figure 11 where internal load Ri is a linear resistive load in accordance with a non-limiting example of implementation of the invention; Figures 38 and 39 show calibration circuits for a a linear resistive internal load Rj_. suitable for use in calibrating the circuit devices of figure 36 and 37 in accordance with non-limiting examples of implementation of the invention; Figures 40-62 show various embodiments of the circuit device of figure 2b in accordance with non-limiting examples of implementation of the invention;

Figures 63-66 show an alternative configuration of a circuit device suitable for use in performing a DC parametric test on an external load in accordance with a non-limiting example of implementation of the invention;

Figure 67 shows another alternative configuration of a circuit device suitable for use in performing a DC parametric test on an external load in accordance with another non-limiting example of implementation of the invention.

Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.

DETAILED DESCRIPTION

With reference to Fig. 2a and 2b, there is shown a general configuration of a system 200 suitable for use in performing a DC parametric test and an unknown external load 206 representing a circuit under test.

The system 200 includes an input 202 for receiving a forcing parameter signal, an output 204 suitable for releasing to an external load 206 a signal approximating the forcing parameter signal. The system also includes a first circuit segment between the input 202 and the output 204 and a second circuit segment connected in a feedback arrangement with the first circuit segment.

As shown in figure 2a, the first circuit segment includes a search entity 199, an intermediate voltage point 214 and an internal load 216 between the intermediate voltage point and the output 204. The second circuit segment provides the search entity 199 in the first circuit segment with a signal indicative of the voltage at the output 204. The search entity 199 is adapted for generating a second voltage signal on the basis of the forcing parameter signal received at input 202 and the first voltage signal received from the second segment and to apply the second voltage signal to the intermediate voltage point 214. The application of the second voltage signal to the intermediate voltage point 214 causes a change in either one of the voltage signal or the current signal at the output 204 such that a signal approximating the forcing parameter signal is caused at the output 204.

It will be appreciated to the person skilled in the art that the search entity 199 may be adapted for processing and generating signals in either digital format or analog format or a combination of both without detracting from the spirit of the invention. For example, the forcing parameter signal applied at input 202 and the second voltage signal released by the search entity 199 may also be in either digital or analog format.

In a specific configuration shown in figure 2b, the search entity 199 is shown including a search unit 208, an analog-to-digital converter module (ADC) 212 and a digital-to-analog converter module (DAC) 210. In this configuration, the second circuit segment includes the analog-to-digital converter module (ADC) 212 for processing the voltage at the output 214 to generate a digital approximation 85 of the voltage signal at the output 204. The first circuit segment includes the search unit 208, the intermediate voltage point 214, the internal load 216 between the intermediate voltage point 214 and the output 204 and the digital-to-analog converter module (DAC) 210. The search unit 208 is for generating a digital target voltage 87 on the basis the digital approximation of the voltage signal at the output 204 and the forcing parameter signal at input 202. The digital-to-analog converter module 210 is between the search unit 208 and the intermediate voltage point 214 and is adapted for processing the digital target voltage 87 to generate a second voltage signal and applying the second voltage signal to the intermediate voltage point 214. The application of the second voltage signal to the intermediate voltage point 214 causes a change in either one of the voltage signal and the current signal at the output 204 such that, at equilibrium, a signal approximating the forcing parameter signal is caused at the output 204. In yet another configuration (not shown in the figures), the first path includes a search unit and a circuit module having digital-to-analog conversion functionality and load functionality. The circuit module is connected between the output of the search unit and the circuit output. A non-limiting example of a circuit module having digital-to- analog conversion functionality and load functionality is shown in figures 46A and 46B which will be described in greater detail further on in the specification. Another example of a circuit module having digital-to-analog conversion functionality and load functionality is a circuit module including digital-to-analog converter module (DAC) 210 and internal load 216 connected as depicted in figure 2b.

With reference to figure 2b, when the system 200 is in use, a first terminal of external load R 206 is connected to output 204. For the purpose of simplicity, it is assumed that the other terminal of external load R₂ 206 is connected to a fixed voltage 220. The resistance of external load R₂ 206 can be derived from the voltage VA_DC at output 204, from the voltage at 220 and by the current I_out flowing at output 204.

The input 202 allows receiving either a forcing voltage value or a forcing current value. In embodiments where the input 202 is for receiving a forcing voltage, the set of functional elements allows forcing the voltage V_ADC at output 204 to a required voltage value at the external load R₂ 206 using a search algorithm implemented by search unit 208. The search unit 208 controls the voltage at intermediate voltage point 214, which is input to the Digital-to-Analog-Converter (DAC) 210, such that the desired voltage V_ADC at output 204 is set as desired. In embodiments where the input 202 is for receiving a forcing current, the set of functional elements allows forcing the current I_out at output 204 to a required current value at the external load R₂ 206.

Depending on the forcing parameter (the voltage V_AD_C or I_out at output 204), different searching algorithms are implemented by the search unit 208. The algorithms implemented by search unit 208 are described in greater detail herein below.

The resistance of the internal load Ri 216 depends on both terminal voltage V_DA_C at point 214 and voltage VA_DC at output 204. The Analog-to-Digital-Converter (ADC) 212 has an input coupled to output 204 and an output coupled to the search unit 208. The ADC 212 has essentially an infinite resistance in the operating range of the system 200. As such the ADC 212 does not draw current and consequently, the current at output 204 flowing in external load 206 also flows into internal load Ri 216.

Internal Load Ri 216

In a specific implementation, the internal load Ri 216 is a non-linear resistor device whose resistance depends on both terminal voltages V_DAC and V_ADC- AS a result, I_out is dependent on both V_DA_C and V_ADC A non-limiting example of the DC characteristics of internal load Ri 216 is shown in Figure 3 of the drawings.

Positive Resistance Property

From Figure 3, it can be observed that for any particular voltage V_DA_C at intermediate voltage point, current I_out at 204 increases when the voltage V_ADC at 204 increases. Mathematically, this can be expressed by the following:

Equation 1

^ADC > 0 for all voltage values VDAC dl_

An internal load Ri 216 is said to have a "positive resistance" if the condition in equation 1 is satisfied. Two non-limiting examples of implementations of such a load element are shown in Figures 4(a) and 4(b). Figure 4(a) shows a linear resistor and Figure 4(b) shows a CMOS inverter. For either one of these elements, the current I_out at 204 increases with voltage V_ADC if voltage V_DAC is fixed at any voltage. Hence the examples of load elements shown in Figures 4(a) and 4(b) follow the relationship in equation 1.

For the purpose of simplicity, only elements with a positive resistance will be used for internal load Ri 216. Therefore, in all the analysis that follows, Ri will be assumed to have a positive resistance. It will be readily apparent to the person skilled in the art in light of this description that an implementation where Ri has a non-positive resistance can be implemented without detracting from the spirit of the invention.

Non-Inverting Property

If the voltages at the intermediate voltage point 214 correspond to V_DA_C voltages in Figure 3 as V_DAC3^>VDAC2^>VDACI₅ then voltage VADC will increase with voltage VDAC if l_out is held at any constant value. Mathematically, this can be expressed by the following:

Equation 2

^^ > 0 for all I_out dV_DAC

A load element Ri 216 is said to be "non-inverting" if the condition in equation 2 is satisfied. An example of a non-inverting load Ri 216 is shown in Figure 4 (a). It will be readily apparent to the person skilled in the art that if current I_out at output 204 is fixed at any value, there will be a constant potential difference between V_ADC and V_DAC- Therefore, VA_DC increases with VDAC- The condition in equation 2 is satisfied.

Alternatively, load element Ri 216 may be "inverting" if it satisfies the following condition. If the voltages shown in Fig. 3 at the intermediate voltage point 214 as VDAC3^<VDAC2^<VDACI, then V_ADC will increase while VDAC decreases (and vice versa) if lout is held constant. Mathematically, this can be expressed by the following:

Equation 3

^∞ < 0 for all l_out

W_DAC A load element Ri 216 is said to be "inverting" if the condition in equation 3 is satisfied. An example of an inverting Ri is shown in Figure 4(b). For a constant I_out, the VA_DC increases while V_DA_C decreases, and vice versa.

Depending on whether an inverting or a non-inverting internal load Ri 216 is implemented in the system 200 (shown in figures 2a and 2b), slightly different search algorithms have to be implemented by the search unit 208. The search algorithms implemented by the search unit 208 will first be described with reference to an non- inverting internal load Ri 216. The algorithm modifications for an inverting-type load Ri 216 will be described later on in the specification.

External Load R₂ 206

With reference to figures 2a and 2b of the drawings, the current I_out flowing from external load R₂ at output 204 is dependent on the voltage V_ADC at the output 204. In most microelectronic circuits, whenever a current is pumped into a node, the node voltage increases. In a specific example of implementation, the system 200 is designed with the assumption that current I_out decreases as V_ADC increases (i.e., V_ADC increases when a positive current is pumped into R₂). Mathematically, this constraint can be expressed as

Equation 4 dl_

< 0 dV A,DC

An example DC characteristic of external load R₂ 206 that follows equation 4 is shown in Figure 5. For the purpose of simplicity, R₂ is assumed to follow the property defined by equation 4. It will be readily apparent to the person skilled in the art in light of this description that an implementation where R₂ does not follow the property defined by equation 4 can be implemented without detracting from the spirit of the invention. Series-connected Loads

When the system 200 is in operation, the internal load Ri 216 is connected in series with external load R₂ 206 as shown in Figures 2a and 2b. As a result, the load currents (I_out's) through the load Ri 216 and load R₂ 206 are equal. The DC bias points can be found by overlapping the DC plots of Figure 3 and Figure 5 to form a load-line plot shown in Figure 6.

It can be seen from Figure 6 that for a voltage V_DAC at intermediate voltage point 214, there is only one valid V_ADC and I_out at output 204 that can satisfy the equilibrium condition. Thus V_ADC and I_out are functions of voltage V_DAC- Mathematically, this relationship can be expressed as two simultaneous equations:

Equation 5

VADC ⁼ ft (VDAC)

Equation 6 lout ⁼ £_(VDAC)

The relationships in equations 5 and 6 imply that it is possible to force either a voltage (V_ADC) or a current (I_out) at output 204 by establishing a corresponding voltage V_DAC at the intermediate voltage point 214.

Force- Voltage-Measure-Current Algorithm

In a first example of implementation of the invention, the input 202 (shown in figures 2a and 2b) is adapted for receiving a forcing parameter signal indicative of a forced voltage signal V_f0rce- In such an implementation, the system is a voltage generating circuit and the search unit 208 is said to implement a force voltage algorithm.

The Search Algorithm An objective of the force- voltage algorithm is to vary the voltage V_DA_C at the intermediate voltage point 214 such that the voltage at the output (V_ADC) 204 will be set to approximate the desired forcing voltage Vf_orce. We will refer to this desired VDAC voltage as V*_DAC-

Figure 7 shows a graphical view of the search process used to obtain V _DA_C- For a particular V_force applied at input 202, the operating current I_out at output 204 corresponds to the intersection of a vertical line representing VADC⁼N_fo_rce and the load line for R₂. This point of intersection is labelled as point A 71 in figure 7. The search algorithm adjusts V_DA_C at the intermediate voltage point 214 such that the load line for load Ri 216 intersects point A 71. The corresponding V_DAC is then V _DA_C-

Figure 8 shows the circuit device of figure 2b adapted for searching for a voltage to apply to intermediate voltage point V_DAC for a desired forcing parameter voltage signal V_for_ce in accordance with a non-limiting example of implementation of the invention.

As shown in figure 8, a forced voltage signal V_fo_rce is applied to input 202. The search unit 208 includes an ADC 80, a digital comparator 82, a digital integrator module 83 and an output for releasing a digital target voltage ko_AC 87. The ADC 80 processes the forced voltage signal Vforce to generated a digital forced voltage signal kpoRC_E 84. The digital comparator 82 is for generating a digital difference voltage signal dependent on the difference between the digital forced voltage signal 84 and the digital approximation 85 of the voltage signal at the output 204 of the circuit device. The digital integrator module 83 is adapted for processing the digital difference voltage signal to derive the digital target voltage k_DAc 87. The digital target voltage k_ϋAc 87 is released at the output of the search unit 208 for processing by the digital- to-analog converter module 210. Where the forcing parameter signal is a digital signal, the ADC 80 may be omitted from the system shown figure 8.

Mathematically, k_forcβ 84 can be expressed as follows: Equation 7

_ JΑ force\ _ "for force y _γ ^r LSB- ADC ^v LSB- ADC

where Q[x] is the quantizer function of the ADC 80, VL_SB-_AD_C is the LSB voltage of 5 the ADC 80 and v_force is the quantized Vfor_ce aplied at 202. Also, the digitized value of V_DAC at intermediate point 214 is denoted by ko_AC at point 87 in figure 8.

It will be readily apparent that for any voltage x and its quantized value Q[x], the difference is no bigger than half the LSB voltage of the ADC 80 (V_LSB-_ADC)- This 0 voltage difference is negligible when ADC 80 has a sufficiently small quantization step. Therefore, for the purpose of simplicity of the description, the following assumption have been made:

Equation 8 5 x — Q_x = kx V_LSB__ADC

where k is the digital representation of voltage x at the output of the ADC. From equation 8, it can be seen that:

Equation 9 ^l0" V ' f.orce - V ' f .orce

Therefore, equation 7 becomes:

Equation 10

JL force force _τr

" LSB- ADC 5

Similarly, for the ADC 212 at the feedback path of Figure 8, Equation 11

track jr

* LSB- ADC

where V_ADC is the voltage at output 204 and k_track is the digital approximation of the voltage signal VA_DC at node 85 in figure 8.

Upon equilibrium in the system, VADC= Vforce and VDAC⁼V^*DAC-

Current Measurement

Once the voltage V_fo_rce has been applied, the current I_out at output 204 needs to be obtained in order to obtain the DC characteristics of external load R₂ 206.

With reference to figure 9, the load lines of internal load Ri 216 are shown with reference to current I_out at output 204. It can be seen from this figure that I_out is dependent on both the voltage V_DAC at the intermediate voltage point 214 and on the voltage V_ADC at the output 204. Mathematically, this can be expressed as follows:

Equation 12 lout ⁼ G (VDAC , VADC)

If the voltage V_ADC at output 204 is kept constant at a voltage which approximates V_fo_rce, current I_out at output 204 becomes a one variable function of the voltage V_DAC at the intermediate voltage point 214 as follows:

Equation 13 lout ⁼ G (VDAC , Vfo_rCe)

This is illustrated in Figure 9, where the vertical line representing N_ADC-N_fo_rce have been superimposed on the load lines. As shown in figures 9 and 10, the intersection points uniquely relate the current I_out at output 204 and the voltage V_DAC at the intermediate voltage point 214. With reference to figure 8, by forcing a voltage VA_DC at output 204 approximating a particular V_force applied at input 202, the voltage V_DA_C at the intermediate voltage point 214 will settle at a corresponding N DA_C- Suppose the relationship G in equation 13 is known, then the current I_out at output 204 can be deduced by simply substituting NDAC⁼N _DA_C into equation 13 to obtain:

Equation 14 lout = G (V DAC . Nforce)

Using the relationship in equation 14, a current measurement mechamsm can be derived as follows. First, it can be seen in figure 8 that the value of the voltage V_DAC at the inteπnediate voltage point 214 is reconstructed from the digital value ko_AC at point 87 via a DAC 210. If we- denote the LSB voltage of the DAC 210 by V_LSB-_DAC, then mathematically V_DAC can be expressed as follows: Equation 15

' DAC ~ "-DAC ^X LSB-DAC

When the circuit in figure 8 is in equilibrium, V_DAC ⁼V _DAC- According to equation 15, the value of koA_C will be given by: Equation 16

V DAC k ^DAC ~ k DAC

V L,SB-DAC

By substituting equations 7 and 16 into equation 14, the value of the current I_ou at output 204 can be deduced as follows: Equation 17 _ut = ^G(^v"^DAc_. V_force) = G(k*DAc x V_ISB__DλC,k_βιreβ x Vj_[SB_ _DC)

As V_LSB-_DA_C and VLSB-ADC in equation 17 are constant scale factors, equation 17 can be simplified as follows: Equation 18 _ut = ^G vAc * V _SB_ _c,k_force x. V_LSB__ΛDC) = G{k^*DAc,k_force)

The relationship described in equation 18 can be implemented by the circuit shown in Figure 11.

The system depicted in figure 11 includes the same system as that is depicted in figure 8 in addition to a current measuring circuit. The current measurement circuit includes search logic 90. Search logic 90 receives a signal conveying a forced voltage signal and a signal conveying the target voltage signal at intermediate point 214 (or alternatively at point 87) and processes these signals to derive a measurement of the current flowing at the output 204 of the voltage generating circuit. In the specific example depicted in figure 11, the current measurement circuit includes a first input for receiving the digital representation of the second voltage signal ko_AC 87, a second input for receiving a digital approximation of the forced voltage signal k_Fo_RCE 84, search logic 90 and an output 92. The search logic 90 derives a certain current measurement on the basis of the digital representation of the second voltage signal k_ϋAC 87 and the digital approximation of the forced voltage signal k_FORCE 84. The certain current measurement is released at the output 92 of the current measurement circuit. When the system is in equilibrium, the certain current measurement is indicative of an approximation of measurement of the current flowing at the output of the voltage generating circuit when the forced voltage is applied to the output 204. It will be appreciated that although the search logic 90 has been described as receiving signals in digital format, search logic 90 may be implemented such that it may receive signals in analog format without detracting from the spirit of the invention.

In accordance with a specific implementation, the search logic of the current measurement circuit includes a data structure in the form of a lookup table 90 containing G . The data structure may be stored on any suitable memory unit such as a RAM, ROM, PROM, EPROM and EEPROM. In a specific non-limiting implementation, the data structure is stored on a RAM device. The values k^* _DAc 87 and k_fo_rce 84 are fed into lookup table 90 to derive I_out. When the system is in equilibrium, the value of I_out can be computed using equation 18.

Calibration Techniques

In a specific implementation, to perform a force-voltage current measurement, a lookup table containing G 90 is used. In this section, two different examples of methods of the calibration procedure for generating the required lookup-table entries for G are described. It will be readily apparent that methods other than those described herein below may be used for generating the lookup table containing G 90 without detracting from the spirit of the invention.

Method 1

In a first specific example, if k_Aoc is forced to a constant value approximating k_force, equation 18 can be written as follows:

Equation 19

Equation 19 indicate that I_out would become a one- variable function of k _DAC- Alternatively, we can write the inverse relationship of equation 19 as follows:

Equation 20

* ,A-i where k _DA_C is a function of I_out, and G is the inverse function of G. The relationship in equation 20 can be obtained by the circuit shown in figure 12. In the circuit, voltage

N_ADc at output 204 is held constant at the desired forcing voltage dictated by k_forCe 84.

The inverse function G is found by sweeping an external current reference I_sweep 94 over a range of current values, followed by recording k DA_C 87 at each current step. The values of k DA_C may be recorded in any suitable readable memory device. In a non-limiting implementation, the values of k _DA_C 87 are recorded on a RAM. In other words, for a given combination of k_forCe 84 and I_sweep 94, a corresponding value of k DA_C i recorded.

Once the inverse mapping G A-i is known, the input and output variables can be interchanged to obtain the function in equation 19. The resultant mapping G can then be used in the current measurement circuit in figure 11. Note that the lookup table G 90 needs to be re-calibrated using this procedure should a different forcing voltage Nforce/ kforce be needed.

Method 2

A drawback of a force-voltage current measurement with calibration method 1 described above is that a large number of calibration points is required before an actual measurement can be done. For example, an n-bit current measurement will require a calibration of 2ⁿ points for the function G . If the number of actual current measurements is small, a significant amount of test time will be wasted to generate the unused entries of the lookup table G 90.

This section describes a second specific example of a calibration scheme that can avoid unnecessary calibrations. To achieve this, the current measurement system is calibrated after an actual measurement is made. The details of this algorithm are described below.

A plot of <_r defined in equation 20 is shown in Figure 13. It can be seen that for the same forcing voltage given by a constant k_ADC-kf_orce 84, voltage k _DA_C 87 is a function of I_out at the output 204. Suppose

when the voltage at the external load R₂ 206 in figure 8 is forced to approximate N_fo_rce- According to figure 13, the corresponding k^* _DAC will be given by k^* _DAc_x- Mathematically, this can be expressed as follows: Equation 21

Now, suppose the output node 204 is connected to a current source at a value I _est 96 as shown in figure 14. It can be seen from figure 13 that when I_out is not equal to I_x (e.g., when I_out=Itestι or IouHtest-D, the corresponding k^* _DAC will not equal k^* _DACχ- The principles of this calibration algorithm is to use the setup in figure 8 to first measure k^* _DACx when I_out is equal to the unknown current I_x. Then, a current reference is applied to the system in a manner shown in figure 14. A search can be conducted to find the required I_test value that generates k DA_C ⁼ k _DACX- The resultant I_test value from the search will be the value of the unknown current I_x.

It can be seen from figure 13 that when I_test is set to Itesti^x, the corresponding k _DA_CI is bigger than k^* _DACx- From this, we can conclude that:

Equation 22 k^*DAC > k^*DACx when I_test < Iχ

Similarly, by observing the intersection point at Iou ltest-^l , it can be said that

Equation 23 k^*DAc < k^* _DACχ when I_test > I_x

The relationships in equations 22 and 23 provide the basis for the calibration search algorithm. In each iteration, I_test is set to a value and the corresponding k _DAC will be compared with k _DACX, the comparison result can then be used to increment/decrement I_test in the next iteration. The detail of this algorithm is summarised in Table 1.

Tablel - Calibration Search Algorithm

The calibration algorithm described in Table 1 can be implemented by the calibration circuit 102 shown in figure 15. The calibration circuit 102 includes a current DAC (ID AC) 104, a digital comparator module 108 and a digital integrator 106. In the figure, ID AC 104 is a current DAC whose output current I_test can be controlled digitally. Upon equilibrium, k _DA_C (87) = k _DA_CX (HO), the digital value of Itest 112 would be equal to the digitised value of the unknown current I_x.

The advantage of this calibration algorithm is that for an n-bit current measurement, a calibration of the 2n points for function G is not required. For example, when the search algorithm in Table 1 is implemented using the step search circuit in figure 15, on average only 2^n_1 calibration points are required. If the search algorithm in Table 1 is implemented by a binary search algorithm, only n calibration points are required for each measurement.

Force-Current-Measure- Voltage Algorithms

In a second example of implementation of the invention, the input 202 (shown in figures 2a and 2b) is adapted for receiving a forcing parameter signal indicative of a forced current signal I_force.

The Search Algorithms

The objective of the force-current algorithms is to control the voltage V_DA_C at intermediate voltage point 214 or voltage V_ADC at output 204 using the system in figures 2a and 2b such that the current I_out at output 204 will be set to approximate the desired forcing current I_forCe applied at input 202.

Search Variables

From equation 6, it can be seen that by varying voltage V_DA_C intermediate voltage point 214, the value of I_out can be set to approximate a desired value, I_fo_roe. A search of the voltage V_DAC can be implemented using the system shown in figure 16. The desired V_DAC voltage is defined as V _DA_C- Mathematically, this can be expressed as follows:

Equation 24 Iforce ⁼ fl(y DAC)

Figure 17 depicts a graphical view of the search process used to obtain N _DAC- For a particular I_forCe applied at input 202, the operating VA_DC (labelled N _ADC) corresponds to the intersection of a horizontal line representing I_ouι~I_brce and the load line for R₂ labelled point B. The search algorithm adjusts the voltage V_DAC such that the load line for internal load Ri 216 intersects point B. The corresponding V_DAC is then V DAC-

V_ADC may also be viewed as a search variable. According to equations 5 and 6, we can write:

Equation 25 lout = f₂ (fl^_1(VADc) ) = f₃ (NADC)

Equation 25 indicates that if voltage VA_DC an output 204 can be controlled, I_out at output 204 can be set to a desired value by searching for the corresponding V_ADC- A search of voltage V_ADC at output 204 can be implemented using the system shown in figure 18. Figure 18 shows the same system depicted in figure 2b but with the search unit 208 designed such that voltage V_ADC at output 204 is set via a feedback network. In this non-limiting implementation, the search unit 208 includes a "V_ADC Search Logic" circuit 304, a digital comparator module 302 and a digital integrator module 300. The "V_ADC Search Logic" circuit 304 implements a search algorithm where voltage VA_DC is a search variable. When the I_out at output 204 is equal to I_force applied at input 202, the desired voltage V_ADC value is given by V*AD_C in:

Equation 26 Iforce ⁼ f->(N ADC) Figure 19 provides a graphical view of the search process used to obtain N A_DC- F°^r particular current I_fo_rce applied at input 202, the operating V_DA_C (labelled N _DA_C) corresponds to the intersection of a horizontal line representing

and the load line for R₂, labelled point C in the graph of figure 19. The search algorithm adjusts N_ADC such that the vertical line representing VA_DC intersects point C. The corresponding VAD_C is then N ADC-

Convergence Conditions

From equations 24 and 26, it can be seen that when I_out ⁼Ifo_rce, the following two conditions will be satisfied:

Equation 27

VDAC ⁼ V DAC

Equation 28

* VADC = V ADC

Therefore, a search algorithm can determine if I_out-Iforc_e by observing either V_DAC or V_ADC- This means that either equation 27 or 28 can be used as a convergence condition of the search.

The Four Search Algorithms

From the above discussions, it has been shown that a force-current search algorithm can be implemented by using either VDA_C or V_ADC as the search variable. Also, the convergence condition can be determined by observing either V_DA_C or V_ADC- Therefore, there are at least four possible variations for the force-current algorithm, as shown in Table 2.

Table 2 - Four Force-Current Search Algorithms

The descriptions for four force-current algorithms will be presented in the following sections.

Voltage Measurement

For the force-current-measure-voltage operation, the voltage V_ADC at output 204 must be measured after the force-current algorithm is applied. From the general architecture of the System in figure 2b, it can be seen that the value of the voltage V_ADC at output 204 can be readily measured by reading the value kADc from the ADC 212 at the end of the force-current searching process.

Convergence Criteria

In the search control logic implemented by search unit 208 of a force-current system, the convergence conditions are observed by evaluating a function (or its inverse) that relates the quantities ko_AC, kADc and I_out. That function will be described in this section.

Consider the load lines of internal load Ri 216 in figure 20. It can be seen from this figure that voltage V_ADC at output 204 is dependent on both the voltage V_DAC at the intermediate voltage point 214 and current I_out at output 202. Mathematically, this can be expressed as follows:

Equation 29 NADC = H (NDAC , lout) If current I_out at output 204 is kept constant at a value that approximates Ifo_rce, voltage N_ADC at output 204 becomes a one variable function of V_DA_C as follows:

Equation 30

NADC = H (NDAC , Iforce)

This is illustrated in figure 20, where the horizontal line representing IoutHforce is shown in the load lines for internal load Ri 216. As can be seen, the intersection points uniquely relates voltage V_ADC and voltage V_DAC in a manner such as that shown in figure 21.

If we denote the LSB voltage of the DAC 210 used in the system 200 by V_LSB-D_AC, then V_DAC can be represented by a digital number koAC defined in equation 15. Similarly, if the LSB voltage of the ADC 212 is defined as V_LSB-_ADC, V_ADC can be represented by a digital value kA_Dc as follows: Equation 31

"ADC ⁼ ^ADC ^X * LSB-ADC

Substituting equation 15 and 31 into equation 30, the following relationship is obtained: Equation 32 ADC ^X " LSB-ADC ⁼ " >ΛC ^X "LSB-DAC ^ force)

As V_LSB-_DAC and V_LSB-AD_C in equation 32 are constant scale factors, equation 32 can be simplified as follows: Equation 33

, _ " pAC ^X "LSB-DAC > I force) _ fa _n_ r

^KADC ~ y- ~ H ^KDAC ' ¹ forc )

* LSB-ADC On the other hand, it can be seen from equation 30 that if current I_out is kept constant at I_fo_rce, voltage V_ADC i a one variable function of VDAC From this, the reverse relationship can be expressed as:

Equation 34

The relationship in equation 34 is illustrated in figure 22, where the horizontal line representing I_0Ut ⁼I_fo_rce is superimposed on top of vertical lines representing different values of V_ADC- The intersection points are circled in the figure. The intersection point at V_ADC^V_ADCI, labelled point D, will be taken as an example. For VADC⁼VADCI, the corresponding value of V_DA_C according to equation 34 is given by the load line of internal load Ri 216 that intersects with Point D. Therefore the value of V_DAC at point D is given by the following:

Equation 35

' DAC ~ " V ADC\ ' -lout ) ,,, =/ _<,„»

If k_DAC and k_ADc in figure 18 are defined by equation 15 and 31, equation 34 becomes: Equation 36

As V_LSB-_DA_C and V_LSB-_AD_C in equation 36 are constant scale factors, equation 36 can be simplified as follows: Equation 37

The functions H and H ^_1 defined in equations 33 and 37 are used in the four force- current search algorithms. A summary of the algorithms is presented in Table 3.

Table 3 - Force current search algorithms

Table 4 is an index to the figures corresponding to the Force-Current Search Algorithms described in the specification. It will be appreciated that binary searches can also be performed by replacing the integrators 352 362 372 376 in Figure 23 (a) to ^• (d) with Successive Approximation Registers (SARs) without detracting from the spirit of the invention.

Table 4 - Force-Current Search Algorithms - Diagrams and Descriptions

The Four Search Implementations

In this section, details of the four search algorithms will be described. Note that because of the similarities in the four algorithms, the reader should get the basic idea from any one of the four algorithm descriptions and may not need to read the other descriptions. In addition, the algorithms are described for signals represented in digital format. It will be appreciated that corresponding algorithms for signals represented in the analog domain may be used without detracting from the spirit of the invention. Such corresponding algorithms and will become apparent to a person skilled in the art in light of the present specification and as such will not be described further here.

Vary-Vr>Ac-Comτ>are-V Anc (Algorithm 1)

The plot in figure 6 can be superimposed with that in figure 20 to form a load line plot in figure 24. It can be seen that out of all the three V_DAC voltages, N_DAC2 will yield Iout=Iforce, i.e.,

Also, at N_DAC2, the corresponding VADC voltage (NADC2) follows the following relationship:

Equation 38

NADC2 ⁼ H (NDAC2 , Iforce)

Therefore, it follows that: Equation 39

VADC = H (V_DAC , Iforce) when N_DAc = N^*DAC

Moreover, it can be seen that for NDACi<NDAC2, the corresponding V_ADCI is given by:

Equation 40

VADCI > H (VDACI , Iforce) Therefore,

Equation 41 VADC > H ( V_DAc , Iforce) when V_DAC < V*DAC

Similarly, by observing V_DAC₃, it can be shown that:

Equation 42

VADC < H (V_DAc , Iforce) when V_DAC > V*_DAC

The relationships in equations 39, 41 and 42 provides the search algorithm required to force I_0ut ⁼I_force- In each iteration, voltage V_DAC is set to a value and the corresponding VA_DC will be compared with H(VD_AC , Iforce)- The comparison result can then be used to increment/decrement V_DAC in the next iteration. Using the definitions of oAC, kADC and H in equations 15, 31 and 33, the conditions in equations 41 and 42 can be summarised into the force current algorithm in Table 3. The corresponding circuit implementation is shown in Figure 23 a). As shown, the search unit 208 implemented in accordance with this first algorithm includes a lookup table 354 containing the function H , a digital comparator 350 and a digital integrator 352.

Var -V ATicrCompare-V AΏC (Algorithm 2)

An alternative force-current approach can be derived by interpreting the load line plot in figure 24 in another manner. Let voltage V_ADC be the search variable and the desired VADC that yield I₀ut⁼Iforce be V^* _AD_C- It can be seen from figure 24 that out of all the three VADC voltages, VADC2 will yield i.e., V^*ADC=VADC2- Also, at VADC2 the corresponding V_DA_C voltage (ND_AC2) follows the following relationship:

Equation 43

NADC2 = H (NDAC2 , Iforce)

Therefore, it follows that:

Equation 44

NADC = H (NDAC , Iforce) when NADC = N*ADC

Moreover, by observing the intersection points at VADC = VAD_CI and VADC = VAD_C3, it can be shown that:

Equation 45

VADC > H (VDAC , Iforce) when VADC < V^*ADC

Equation 46 NADC < H (NDAC , Iforce) when NADC >N* ADC

Using the definitions of koA_C, kADC and H in equations 15, 31 and 33, the conditions in equations 45 and 46 can be summarised into the force current algorithm in Table 3. The corresponding circuit implementation is shown in figure 23 (b). As shown, the search unit 208 implemented in accordance with this second algorithm includes a lookup table 354 containing the function H , a first digital comparator 356, a first digital integrator 358, a second digital comparator 360 and a second digital integrator 362.

Vary-V c-Conxpare-VnA (Algorithm 3)

The graph in figure 6 can be superimposed with that in figure 22 to form a load line plot in figure 25. It can be seen that out of all the three VA_DC voltages, N_ADC2 will yield i.e., N^*ADC^=:NADC2. Also, at VADC2 the corresponding VDAC voltage (V_DA_C2) follows the following relationship: Equation 47

V_DAC2

Therefore, it follows that:

Equation 48

V_DAC = ^_1 (V_mc , I_force) |_/M=/_ when VADC = V^*ADC _.

Moreover, it can be seen that for V_ADCI VADC2, the corresponding VDACI is given by:

Equation 49

VDACI <

Therefore,

Equation 50 V_DAC < H^_1()^_c,/_/oree) \_Im __Ifirce when VADC < V^*ADC

Similarly, by observing NADC3, it can be. shown that:

Equation 51 V_DAC >

__Iforce when VADC > V^*ADC

The relationships in equations 48, 50 and 51 provides the search algorithm required to force I_ou_t-I_force- In each iteration, VA_DC is set to a value and the corresponding VDAC will be compared with

» ^me comparison result can then be used to increment/decrement VA_DC in the next iteration. Using the definitions of kϋAc, k_ADC and H¹ in equations 15, 31 and 37, the conditions in equations 50 and 51 can be summarised into the force current algorithm in Table. 3. The corresponding circuit implementation is shown in Figure 23 c. As shown, the search unit 208 implemented in accordance with this third algorithm includes lookup table 364 containing the function H ^"*, a first digital comparator 366, a first digital integrator 368, a second digital comparator 370 and a second digital integrator 372. Varv-VnAc-Comvare-Vmr, (Algorithm 4)

An alternative force-current approach can be derived by interpreting the load line plot in figure 25 in another manner. Let V_DAC be the search variable and the desired V_DAC that yield I₀ut⁼I_force be V*_DAC It can be seen from figure 25 that out of all the three VDAC voltages, V_DAC2 will yield Iout=Ifbrce. i-e., V*DAC=VDAC2- Also, at VDAC2, the corresponding V_ADC voltage (NADC2) follows the following relationship:

Equation 52

' DAC2 ~

Therefore, it follows that: Equation 53

V_DAC = H^~ ΦADC' I force) cm,=-/' f,_or, when NDAC = N DAC

Moreover, by observing the intersection points at VDAC = NDAci and VDAC = VDAC3, it can be shown that:

Equation 54

V_DAC <

when V_DAC < V*DAC

Equation 55 V_DAC > H-'iV^cI^ \_Im __Ifom when V_DAc > V^* _DAC

Using the definitions of ko_AC, kADC and H^_1 in equations 15, 31 and 37, the conditions in equations 54 and 55 can be summarized into the force current algorithm in Table 3. The algorithm described in Table 3 can be implemented by the circuit shown in figure 23 (d). As shown, the search unit 208 implemented in accordance with this fourth algorithm includes lookup table 364 containing the function H ^" , a digital comparator 374 and a digital integrator 376. It can be observed that the circuit in figure 23 (d) including 374, 376 and the feedback line from 376 to 374 is a unity gain buffer. As such, the circuit can be simplified to the implementation shown in figure 26.

In the circuit in figure 26 the search unit 208 is implemented by a memory module 364, such as a RAM. In a non-limiting implementation, the search unit 208 is implemented by a RAM without any addition digital circuitry for performing the searching functionality.

Calibration Techniques

In the first and second force-current algorithms described above, a lookup table 354 containing the function H is used in the circuit implementation as shown in figures 23a) and 23b). Also in the third and fourth force-current algorithms, a lookup table

364 containing the function H ^-1 is used in the circuit implementation as shown in figures 23c) and 23d). The calibration procedures for these functions will be described herein below.

The function H defined in equation 34 can be found using the circuit shown in figure 27. In the circuit, I_out at output 204 is held constant at the desired forcing current If_orCe by current source 380. The function H is found by sweeping ko_AC over the full-scale range of the DAC 210, followed by recording k_ADC 85 at each step.

On the other hand, the function H , defined in equation 37, can be found using the circuit shown in figure 28. In this circuit, I_out at output 204 is held constant at the desired forcing current I_fo_rce by current source 380. The function H^"1 is found by sweeping k_ADC over the full-scale range of the ADC 212, followed by recording koA_C 87 at each step. Note that, alternatively, the function H can be obtained by first finding the functional relationship H ^-1 followed by a switch of input and output variables. Similarly, the function H^"1 can be obtained by switching the input and output variable after finding H .

The lookup table H (or H^_1, whichever is employed in the force-current search algorithm) needs to be re-calibrated should a different forcing current I_forCe be needed.

Algorithm Modifications for an Inverting Load

The section below describes the circuit modifications when the internal load Ri 216 used in the system 200 is an inverting load.

Force-Voltage-Measure-Current Algorithms

If the internal load Ri 216 of the system 200 follows the inverting property defined in equation 3, the feedback loop in Figure 8 needs to maintain negative feedback by switching the polarity of the comparator 82. The modified circuit is shown in figure 29 where the comparator 82 of figure 8 has been replaced by comparator 400 in figure 29. Note that the same change also applies to the measurement and calibration circuits in figures 11, 12 and 14.

The current measurement and the first calibration method described above for a non- inverting internal load Ri 216 do not need to be modified for an inverting Ri because V DA_C (as well as k^*DAc) is still a one-to-one corresponding function of I_out for any particular VA_DC ⁼Vf_orce- However, the second calibration method described needs to be modified for an inverting Ri. A modified calibration search algorithm is shown in Table 5. The modified calibration search circuit in figure 15 is shown in figure 30 where the comparators 82 and 108 of figure 15 have been replaced by comparators 400 and 402 respectively in figure 30. Table 5 - Modified Calibration Search Algorithm for an Inverting Ri

Force-Current-Measure-Voltage Algorithms

When the internal load Ri 216 of the system 200 follows the inverting property as defined in equation 3, the feedback loop in the general force- VA_DC architecture in figure 18 needs to maintain negative feedback by switching the polarity of the comparator. The modified circuit is shown in figure 31 where the comparator 302 of figure 18 has been replaced by comparator 600 in figure 31. Similarly the V_ADC search logic module 304 in figure 18 is replaced by modified V_ADC search logic module 604 for certain algorithms (as in figure 32).

The modifications for each force-current algorithm is described herein below.

Varv-VnAc-Comyare-V oc (Algorithm 1)

When an inverting internal load Ri 216 is used, this search algorithm is modified in order to maintain convergence of the target current value I_for_ce- The modified search algorithm and its implementation are shown in Table 6 and figure 32. As shown, the search unit 208 implemented in accordance with this first algorithm when an inverting internal load Ri 216 is used includes a lookup table 364 containing the function H ^Λ, a digital comparator 600 and a digital integrator 602.

Table 6 - Force current algorithm for an inverting Ri (vary- V_DAc-compare- VA_DC)

Vary-V AncyCompare-V mc (Algorithm 2)

There is no change in this search algorithm when an inverting internal load Ri 216 is used. However, because this algorithm has a force- VA_DC circuit implementation, the modification in figure 31 is required. The modified circuit is shown in figure 33. As shown, the search unit 208 implemented in accordance with this second algorithm includes a lookup table 614 containing the function H , a first digital comparator 612, a first digital integrator 610, a second digital comparator 608 and a second digital integrator 606.

Vary-VAnc-Compare-VnAc. (Algorithm 3)

When an inverting internal load Ri 216 is used, this search algorithm has to change in order to maintain convergence of the target current value. The modified search algorithm is shown in Table 7. Also, because this algorithm has a force- V_ADC circuit implementation, the modification in Figure 31 is required. The modified circuit is shown in figure 34. As shown, the search unit 208 implemented in accordance with this third algorithm includes a lookup table 616 containing the function H , a first digital comparator 612, a first digital integrator 610, a second digital comparator 608 and a second digital integrator 606.

Table 7 - Force current algorithm for an inverting Ri (vary- VADC-compare- VDA_C)

Vary-VnAc-Compare-VnAC (Algorithm 4)

There is no change in this algorithm or its implementation if an inverting Ri is used.

5 Special case; Using an Internal Linear Resistive Load Ri 216

This section deals with the special case where the internal load Ri 216 used in the system 200 is a linear resistor. The general architectures of the system that forces V_DAC and V_ADC are shown in figure 35 and figure 36. In both figures, the internal load 0 Ri 216 is a linear resistor and is denoted by R_IL. In figure 36, the search unit 208 includes search logic 704, a digital comparator 702 and a digital integrator 700. Upon equilibrium, the current I_out at output 204 in both circuits is given by:

Equation 56 ς γ __ ^ADC ^X ' LSB-ADC ~ ^DAC ^X ' LSB-DAC , T ^{J 1} out ~ r> ~^{r x} offset

^K\L

where I₀ff_Set is a current offset term resulted from the offset voltages of the DAC 210 and the ADC 212. A calibration process is required to determine the values of the constants Ri_L and I₀ff_set. After these values are found, the lookup tables can be readily 0 constructed for the force-voltage-measure-current or the force-current-measure- current algorithms.

From equation 56, it can be seen that the quantities I_out, kADc and ko_AC are linearly related. As we will see in the following sections, this linearity property will 5 dramatically deduce the amount calibration time required.

Current Measurement Consider the force- voltage-measure-current circuit in figure 37. It is the same as the circuit in figure 11 except that internal load Ri 216 is a linear resistor denoted by R_IL-

For this circuit, we can write G defined in equation 18 as:

Equation 57

T - il-* v \ - ^ADC ^x VLSB-ADC ~ k ^{DΛC X} VLSB-DAC , r

¹out - DAC, V_force) ^{+ 1} offset

^K\L

where the values of R_IL and I_0ffset can be found using the calibration method described further on in the specification.

The relationship in equation 57 indicates that the lookup table G 706 in the current measurement system (shown in figure 37) can be generated by_ttwo calibration points.

Moreover, from equation 57, it can also be seen that the lookup table G 706 need not be re-calibrated if a different forcing voltage is required. This is different from the lookup table G 90 shown in figure 11 for the generalized current measurement system, where the function G needs to be re-calibrated whenever a different forcing voltage Nforce) is needed.

Current Generation

With the relationship in equation 56, we can write H defined in equation 33 as follows:

Equation 58 π(l T \ - lr - - f°^rce ~Ioffset ^R\L ^ _Jr „ VLSB-DAC ^{n K}DAC ' ^J force ) ~ ^KADC ~ γ ^{V K}DAC ^Λ 9}

' LSB-ADC ' LSB-ADC

Similarly, we can write H ^J defined in equation 37 as follows: Equation 59

The relationships in equations 58 and 59 mean that the lookup table H and H^-1 in the force-current system described previously for the case of a general internal load Ri 216 can be generated by two calibration points when internal load Ri 216 is a linear resistor. Moreover, from equations 58 and 59, it can also be seen that the lookup tables need not be re-calibrated if a different forcing current is required. This is different from the lookup tables for the generalised current forcing system in Section 2.4, where the functions H and H^"1 need to be re-calibrated whenever a different forcing current (Iforce) is needed.

Calibration Circuits

The force- voltage circuit in figure 38 is analogous to the front end of the system in figure 35. In figure 38, a reference current source 708 with value I_ref is connected to the resistor 216 at output 204. The voltage V_DAC at output 204 is forced by the digital value ko_AC-_cai 709. When the circuit in figure 38 is in equilibrium, the value of voltage V_ADC at output 204 is represented by kADC-cai 711. The reference current source I_ref 708 can be expressed as:

Equation 60

T _ ^ADC-cal ^X ' LSB-ADC ~ ^DAC-cal ^X ' LSB-DAC , γ ¹ref - _Ό ^"T^J offset

^K L

Another force- voltage circuit is shown in figure 39. This circuit is similar to the force- V_ADC architecture shown in figure 36. The voltage VA_DC at output 204 is set by the digital value kADC-cai 713. When the circuit is shown in figure 39 is in equilibrium, the value of voltage VDAC at intermediate voltage point 214 is represented by ko_Ac-_cai 714. The expression in equation 60 can also be used to describe current I_ref 708. A purpose of the calibration process is to determine the values of the constants R^ and l_offset- To find these two constants, two calibration points are used. Note that either one of the circuits in figure 38 and figure 39 can be used as the calibration circuit as they both follow equation 60.

For the circuit in figure 38, a value of koAC-cai 709 and a reference current I_ref 708 is set at each calibration point. Then the resultant kADC value, kADC-cai 711, is recorded. For the circuit in Figure 39, a value of kADC-_cai 713 and a reference current I_ref 708 is set at each calibration point. Then the resultant koAC value, koAC-cai 714, is recorded.

The values of kAD_C-_cai or the two calibration points will be designated as kADC-caii and k_ADC-_cai2- Similarly, the calibration values for koAC-cai and I_ref can be written as kDAC_caiι, kDAC-cai , Lefi and I_ref2- Using equation 60, two equations can be generated after two calibration points: Equation 61

T _ k ADC-call ^X ' LSB-ADC ~ ^DAC-call ^X ' LSB-DAC , j ^Xref\ - _Ώ ~^{r l} offset

^R\L

Equation 62

T _ ^ADC-call ^X ' LSB-ADC ~ '^ZDAC-cal2 ^X ' LSB-DAC , r

^Xref2 - _Ώ ^"^ offset

^K\L

Equations 61 and 62 can be solved to yield the values of R_IL and loffset as follows:

Equation 63 r>

Equation 64

*^■ offset

Special Case: Simplified Calibration and Measurement

Equations 57, 58 and 59 can be used to generate a lookup table with the generic calibration procedure described previously in the specification. The section below shows how to simplify equations 63 and 64 to reduce the computational complexity of generating a lookup table for a linear resistive load.

Equations 57, 58 and 59 can be simplified if constraints are imposed on the design of the system and on the calibration procedures. This section describes an example of such a set of constraints that enables effective implementation of the system with a linear element. It will be readily appreciated that other methods for simplifying the computations may also be used without detracting from the spirit of the invention.

To avoid unnecessary arithmetic due to LSB conversions, the system 200 can be designed such that:

Equation 65

In other words, the LSB voltage of ADC 212 and DAC 210 are the same. In the calibration procedure, the force- V_ADC circuit in figure 39 is used. The two calibration points are given in Table 8.

Table 8 - Calibration Points

The zero reference current I_ref2 can be easily set by merely disconnecting the output 204. Hence, only one calibration point Ifo_rce-ref requires an external reference. The calibration process is summarised in Table 9 with reference to figure 39.

Table 9 - Calibration of the System with Linear Ri 216

With the system requirement in equation 65 and the calibration points in Table 8, equations 57, 58 and 59 can be simplified as follows:

Equation 66 k DAC k_DAC__cal2 + k_βrce__ref k_force

^Iout = ^G(^k*DAC , V_force " force— ref

Equation 67 ADC ~

+ EC* force)

Equation 68 k-DAC

where:

Equation 69

7 ^~/ force -* force) ' ~

r + V¹ force-ref

force-ref These formulas can be reasonably easily implemented by a digital circuit. The force- voltage-measure-current process using the calibrated values is summarised in Table 10 with reference to figure 37.

TablelO - Force- Voltage Current Measurement Procedure

The calibrated system can also be used to force any arbitrary current I_out at output 204 to the external load R₂ 206 and measure the voltage V_ADC at output 204. Any force- current algorithm in figures 23 or 26 can be used. This process is summarised in Table 11.

Table 11 - Force-Current Voltage Measurement Procedure

CIRCUIT IMPLEMENTATIONS

The following part of this specification describes specific examples of implementations of the general system 200 shown in figures 2a and 2b. Circuit implementations of the force- voltage-measure-current and the force-current-measure- voltage algorithms will be described. General Architectures of the Force-Voltage/Force-Current Algorithms

In a non-limiting implementation, the system 200 shown in figure 2b may be implemented using digital logic components and a front-end circuit. The details of the front-end circuit are provided herein below.

Force- Voltage-Measure-Current Algorithm

The general structure of the system for implemented a force- voltage-measure-current circuit is shown in figure 40. As depicted, the system includes a lookup table 706 containing G and a front-end circuit, referred to as 'N_ADC-Forcing circuit" 721 in figure 40. In this non-limiting implementation, lookup table 706 is implemented by a RAM. Lookup table 706 releases a current measurement at output 715. It will be appreciated that other suitable memory devices may be used without detracting from the spirit of the invention. The V_ADC-Forcing circuit 721 is shown in isolation in figure 41. Details of the V_ADC-Forcing circuit 721 will be described further on in the specification.

Force-Current-Measure- Voltage Algorithm

With reference to figures 23 a), b), c), d) and figure 26, two basic architectures have been described for the Force-Current-Measure- Voltage Circuit, depending on whether the search variable is the voltage V_ADC at output 204 or voltage V_DAC at the intermediate voltage point 214. The two basic architectures are shown in figures 42 and 43. As shown, for both of these architectures, the search logic 720 724 accesses a lookup table 722 where either function H or function H^_1 is stored. In this non- limiting implementation, lookup table 722 is implemented by a RAM device. It will be appreciated that other suitable memory devices may be used without detracting from the spirit of the invention. For the force-current architecture that uses voltage V_ADC at output 204 as a search variable, shown in figure 42, the VAD_C-Forcing circuit 721 shown in figure 41 is used as a front-end circuit. For the force-current architecture that uses voltage V_DAC at the intermediate voltage point 214 as a search variable, shown in figure 43, the value voltage V_DAC at point 214 is reconstructed from value koAC at node 87 using DAC 210. The V_DAC-Forcing circuit 725 shown in figure 43 and in figure 44 includes DAC 210, internal load Ri 216 and the ADC 212. Details of the V_DAc-Forcing circuit 725 will be described herein below.

V_DA_C-F or cing Circuit 725

In a non-limiting implementation, the architecture of the Vr-Ac-Forcing Circuit 725 in figure 44 includes of a DAC 210 with essentially zero output impedance, hereinafter referred to as a "low-impedance DAC" 210, an internal load element Ri 216 and an ADC 212 with infinite input impedance, hereinafter referred to as a "high-impedance ADC". It is to be appreciated that the expression "infinite input impedance" is meant to designate a device, which in its effective operating range will draw a quantity of current that is considered to be essentially negligible. The components of the V_DAC- Forcing Circuit 725 are described in the following sections.

DAC 210 and the Internal Load Element Ri 216

The partial front-end circuit with the low-impedance DAC 210 and internal load Ri 216 is shown in figure 45. The combination of the DAC 210 and internal load Ri 216 as separate components is one example of implementation of a circuit module having digital-to-analog conversion functionality and load functionality. The voltage V_ADC at output 204 is given by a function of voltage VDA_C at intermediate voltage point 214' and current I_out at output 204 as follows:

Equation 70 V^^H^V^,!^) where the function Hiu is dependent on the internal load Ri 216. The voltage V_DA_C at intermediate voltage point 214 is described by:

Equation 71

' DAC — ^DAC ^X ' LSB-DAC

In this description, five alternative specific implementations of the circuit module having digital-to-analog conversion functionality and load functionality in figure 45 will be described. It will be readily appreciated that other configurations of the circuit in figure 45 may be used without detracting from the spirit of the invention.

Two of these implementations are shown in figures 46a) and 46b). The implementations in figures 46a) and 46b) are hereinafter referred to as Load Configurations A and B respectively. In both circuits, a PDM generator 801 generates digital pulses with a specific density of l's (hereinafter referred to as "pulse density") controlled by k_DAC When the digital pulses pass through the low-pass filter (LPF) formed by R_AX and C_AX (where x = 1 to m), the output voltage V_AD_C at output 204 is settled at a specific DC value that is dependent on the pulse density. Also, it can be seen that for a particular pulse density, the DC value of voltage V_ADC at output 204 will change depending on current I_out at output 204. Therefore, the circuits in figures 46a) and 46b) can be represented by a low-impedance DAC connected with a resistor. The parameters of the equivalent DAC 210 and the internal load Ri 216 shown in figure 45 can be derived as follows. For the circuits in figures 46a) and 46b), if the PDM generator 801 can generate 2ⁿ distinct pulse densities, V_LSB-_DAC of the equivalent DAC 210 (in figure 45) is given by:

Equation 72

where V_DD is the voltage representing the high value of the PDM generator 801. Also, the equivalent internal load Ri 216 is linear and is given by the values in Table 12 below.

Table 12 - Equivalent load resistances of Load Configurations A and B

Alternatively, the circuit in figure 45 can be implemented using other configurations. Consider the three implementations shown in figures 47 (a) to (c) (hereinafter referred to as Load Configurations C to E). In these circuits, the PDM generator 801 and the low-pass filter (LPF) 805 corresponds to the low-impedance DAC 210 in figure 45. If the PDM generator 801 can generate 2ⁿ distinct pulse densities, V_LSB-_DAC of the equivalent DAC 210 in figure 45 is given by equation 72.

Each of the MOS circuits 807 in figures 47 (a) to (c) correspond to the internal load Ri 216 in figure 45. It can be seen that the equivalent internal load Ri 216 for any one of the MOS circuits shown is inverting because the equivalent voltage V_DA_C at intermediate voltage point 214 (not shown) increases while voltage V_ADC at output 204 decreases for a particular current I_out at output 204. Note that in practice, the current sources in figures 47(b) and (c) of the MOS circuits 807 will generally have a positive differential output resistance. Hence, I i_as is dependent on voltage V_ADC at output 204. Moreover, load configurations D and E (shown in figures 47(b) and (c)) can also be implemented with the bias current sources removed (i.e., I_Di_as ⁼0). In this case, configuration D (in figures 47(b)) can be used to measure/generate negative output currents (where l_out<0) only while configuration E (in figures 47(c)) can be used to measure/generate positive output currents (where l_out>0) only.

The value of voltage V_ADC at output 204 for the five configurations described above can be easily deduced and is shown in Table 13. In Table 13, voltage V_DAC at intermediate node 214 is the equivalent DAC voltage given by equation 71. The functions H_NOT, H_PMOS and H_NMOS are DC transfer functions of the CMOS inverter, PMOS and NMOS circuits shown in figures 48 (a), (b) and (c), respectively, which can be written as:

Equation 75

Vouti ⁼ HNOT (Vini , Iouti)

Equation 76

Vout2 = HpMOS (Vjn2 , Iout2)

Equation 77

V₀ut3 = HNMQS (Nin3 , Iout3)

It will be appreciated that although the examples shown in figures 46(a), 46(b) and 47(a) to (c) include the PDM generator 801, the latter may be replaced by a suitable general-purpose pulse generator that provides a digital pulse.

ADC 212 (Digital Integration / Successive Approximation)

In a non-limiting implementation, the ADC 212 shown in figure 44 can be implemented by a delta-modulator of the type described in U.S. Patent No. 2,605,361 issued to Cassius C. Cutler et al. in July 29, 1952. The content of this document is hereby incorporated by reference. This implementation is shown in figure 49.

As shown, the analog-to-digital converter module 212 includes an analog comparator 504, a digital integrator 502 and a feedback circuit. The analog comparator 504 receives a signal indicative of the voltage at the output 204 and a tracking voltage V_trac and generates a difference signal on the basis of the signals received. The digital integrator 502 receives the difference signal and generates successive digital approximations of the voltage signal at the output of the circuit device. The feedback circuit processes the successive digital approximations of the voltage signal to generate the tracking voltage V_track and provide the latter to the analog comparator 504. In a non-limiting implementation, the feedback circuit includes a digital-to- analog converter module 500.

In a non-limiting implementation, the DAC 500 in figure 49 can be implemented using the voltage reference described in M. M. Hafed, S. Laberge, G. W. Roberts, "A Robust Deep Submicron Programmable DC Voltage Generator", Proc. IEEE International Symposium on Circuits and Systems, Vol. 4, pp. 5-8, May 2000 and depicted in figure 50. The content of this document is hereby incorporated by reference. The output of the digital integrator 502, k_ADC, increases or decreases by a constant amount depending on the result from the comparator 504. Upon equilibrium, the tracking voltage Vtra_ck released by the DAC 500 will equal voltage VA_DC- The value k D_C will become a digital representation of VAD_C

In accordance with an alternative specific example of implementation, the ADC 212 shown in figure 44 can be implemented by successive-approximation circuit of the type described in D. A. Johns, K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, Inc., pp. 492-493, 1997. The content of this document is hereby incorporated by reference. As shown in figure 51, the digital integrator 502 in the analog-to-digital converter module in figure 49 is replaced by a successive- approximation register (SAR) 506 module. In this implementation, the Successive- Approximation Register Logic (SAR Logic) 506 binary searches for the value of k_ADC that equalises V_ADC and Vrack- The output value kAD_C will be a quantized representation of VA_DC given by:

Equation 83

7, _ V ' A.D: C

*ΆDC ^~ V L,SB-ADC

where VL_SB-_AD_C is the LSB voltage of the ADC circuit 212. If we denote the LSB voltage of the DAC 500 that is used in the ADC circuit in figures 49 and 51 by V_LSB- DAC(ADC), the value of VLSB-ADC will be given by:

Equation 84

' LSB-ADC ⁼ ' LSB-DAC(ADC)

ADC 212 (Delta Modulator) In yet another alternative implementation, the ADC 212 is implemented by a delta- modulator of the type described in D. J. G. Janssen, "Delta Modulation in DVM Design", IEEE Journal of Solid-State Circuits, Vol. SC-7, pp. 503-507, Dec. 1972. The content of this document is hereby incorporated by reference. A non-limiting implementation of the circuit is shown in figure 52. As shown, the ADC 212 includes an analog comparator 504, a D-Flip-Flop (D-FF) 508, an RC filter 512 and a frame counter 510. It will be appreciated that although the example shown in figure 52 includes a the frame counter 510, the latter may be replaced by a general purpose digital filter implementing accumulation functionality such as a digital integrator for example.

At equilibrium, the tracking voltage Vtrack will equal voltage V_ADC at output 204. The DC value of V_track (and thus VAD_C) can be deduced by observing the density of l's (hereinafter referred to as "pulse density") from the D-FF 508. The frame counter 510 captures a frame of bits from the output of the D-FF 508 and counts the number of l's in a frame. The resultant count k_ADc will become a digital representation of voltage VA_DC- For example, if the length of the frame captured is 2ⁿ bits, the output value k_ADc will be a quantized representation of V_ADC given by equation 83, where:

Equation 85

Functional Relationship Between kAnc, k andln t

When the VoAc-Forcing circuit 725 (figure 44) is used to implement the first and second current-searching algorithm, the corresponding function H defined in equation 33 is dependent on the internal load Ri. From equations 70, 71 and 83, H can be written as: Equation 86

where V_LSB-A_DC is the LSB voltage of the ADC 212 in the Vo_AC-Forcing circuit 725. Using equation 86, the relationships in Table 13 can be rewritten as functions H listed in Table 14.

Table 14 - Value of k_ADC for different load configurations

Load Definition of H Configuration

A Equation 87

H(J^CDAC> ^Ioι )

V L,SB-ADC

B Equation 88

^DAC ^X " LSB-DAC ^{" "} RB +∑RAI R.

;=1

H(^fcDAC>^Io, ) ⁼ - F L,SB-APC

Equation 89 ^NOT KpAC ^X ' LSB-PAC ^O.

H(kpAc>Iout) - r L,SB-ADC

D Equation 90

H(k_DAC,I_0Ut) tt PMOS DAC ^X " LSB-DAC ' ^OΗΓ )

V L,SB-ADC

E Equation 91

V_ADC-Forcing Circuits 721

V_ADC-Forcing Circuits 721, of the type shown in figure 42, are used in the force- voltage-measure-current algorithm as well as the third and fourth force-current- 5 measure- voltage algorithms. In this section, two specific non-limiting implementations of the V_ADC-Forcing circuits 721 will be described. It will be readily apparent that other suitable implementations are possible without detracting from the spirit of the invention. Before the description of the two implementations, the definition of a function that relates the key variables of the VAoc-Forcing Circuit 721 10 is provided in the following.

When a V_ADC-Forcing Circuit 721 is in equilibrium, the quantities koA_C, kADC and I_out will be related by a function which is dependent on the internal load Ri 216. That function will be described in the following. Let us define a DC transfer characteristic 15 W_RI for internal load Ri 216 such that voltage V_DAC at intermediate voltage point 214 is a function of the voltage V_ADC and the current I_out at the output 204. Mathematically, this can be expressed as follows:

Equation 92

20 VDAC=W_R1(NADC, lout)

When the circuit in figure 44 is in equilibrium, ko_AC can be expressed as:

Equation 93

■J Γ ;L _ ^ j.1 ^ADC ^x VLSB-ADC - ut ) ^{J K}DAC ~~

' LSB-DAC

where VLSB-A_DC and V_LSB-_DAC are the LSB voltages of the equivalent ADC 212 and the DAC 210 employed in the V_ADC-forcing circuit 721, respectively. Function W_Rl can be defined as: 30 Equation 94

VfT (l_r T \ — J_r - " R\ ^ADC ^X ' LSB-ADC ■ hut ) ^πR\ ^lζADC > ^I out ) - ^KDAC 91

' LSB-DAC

For each variation of the V_ADC-Forcing Circuit 721 described in the following sub- sections, the function W_Rl will be derived and listed. At the end of the section, we will show that the function W_Rl for the V_Aoc-Forcing circuits described is related to the functions G and H used the force-voltage / force-current algorithms.

VAnr-Forcing Circuit 721 (Digital Integration / Successive Approximation)

The V_ADC-Forcing Circuit 721 in figure 41 is redrawn in figure 53. It can be seen that the V_ADC-Forcing circuit 721 includes a Vo_AC-Forcing circuit 725 with a digital comparator 702 and a digital integrator 700. Therefore, a V_Aoc-Forcing Circuit 721 can be implemented using a Vo_AC-Forcing circuit 725 described above in addition to the digital logic shown in figure 53.

In a non-limiting implementation where the combination of DAC 210 and internal load Ri 216 is of the type shown in figures 46 a) or b) (type A or B), the equivalent internal load Ri 216 is linear and the corresponding values are shown in Table 12 above.

If an alternative non-limiting implementation where the combination of DAC 210 and the internal load Ri 216 is of the type shown in figures 47a), b) or c) (type C or D or E), the equivalent internal load Ri 216 will be an inverting load. For these implementations, the polarity of the digital comparator 702 in figure 53 should be inverted to maintain negative feedback. This modification is shown in figure 54 where digital comparator 702 was replaced by digital comparator 730. Similarly to the ADC circuit 212 described above with reference to figures 49 and 51, the digital integrator 700 in figures 53 and 54 can be replaced by an SAR Logic unit such that the value of ko_AC can be obtained by a binary search.

Upon equilibrium, the function W_RX for each load configuration is given by Table 15. In Table 15, V_LSB-A_DC and V _SB-_DAC(PDM) are the LSB voltages of the equivalent ADC 212 and the DAC 210. The functions W_NOT, WPMO_S and W_NMOS represent the DC transfer characteristics of the CMOS inverter, PMOS and NMOS circuits shown in figure 48 (a), (b) and (c), which can be written as: Equation 95

Vjni = WNOT (V_outi , louti)

Equation 96

Vjiβ = WpMOS (Vout2 , lout-)

Equation 97 Vjn₃ = WNMOS (V_0Ut3 , Io t3)

Table 15 - The Value of ko_AC for different load configurations

Load Definition of the function W R.\ Configuration

A Equation 98

B Equation 99

c Equation 100

VAnc-Forcing Circuit 721 (Delta Modulation)

The V_ADC-Forcing Circuits 721 in figures 53 and 54 can be simplified into a group of circuits derived from a Delta-Modulator structure. Specific examples of implementation of such circuits are shown in figures 55 (a) to (e). Each circuit shown in figure 55 includes a DAC 904, an analog comparator 902 (916 in figures 55 (c) to (e)), a D-FF 906 and a digital filter in the form of a frame counter 900. It will be appreciated that although the example shown in figures 55 (a) to (e) includes frame counter 900, the latter may be replaced by a general purpose digital filter implementing accumulation functionality such as a digital integrator for example. The corresponding set-ups for load configurations shown in figures 46 (a) and (b) and in figures 47 (a) to (c) (i.e. Load Configurations A to E) are shown in figure 55 (a) to (e) respectively.

Upon equilibrium, the voltage V_ADC at output 204 will be equal to the DC value set by k_ADC and the DAC 904. As previously described, the value of koA_C can be deduced by observing the pulse density from the D-Flip Flop 906 using a frame counter 900.

The function W_Rl for the different load configurations are given by equations 105 to 109 shown in Table 16. In the table, V_LSB-_ADC is given by: Equation 103

VLSB-ADC⁼ VLSB-DAC (Force-vADC)

where VLSB-DAC(Force-vADC) is the LSB voltage of the DAC used in the Force- VADC circuits in figures 55 (a) to (d).

The value of VLSB-DAC in Table 16 depends on the length of a captured frame in the frame counter 900. For a captured frame with 2ⁿ bits in length, VLSB-DAC is given by:

Equation 104

V ' D_nP.

V L,SB-DAC 2"

Table 16 - Value of ko_AC for different load configurations

Load Definition of the function W R,\ Configuration

Equation 105

w_Rl(k _ '\A ADnrCA ' L rS<mB_-DnA_rC K M-Aλl X ' -t_Λ,

ADC ' ^■'^■out)

V L,SB-ADC

B

Equation 106

Equation 107

D Equation 108

XV Or T \ — PMOS ^ADC ^X " LSB-DAC ' 1 out ) ^WR\ y^ADC > ^l out ) T_r

V L,SB-ADC

Equation 109

Comparing the equations in Table 16 to that in Table 15, it can be seen that the structures in figure 55 (a) to (d) can also be mapped into the generalised architecture of the V_ADC-forcing circuit in figure 41. For the load configuration of type shown in figures 46 (a) and (b) (type A or B), the equivalent internal load Ri 216 is linear and the corresponding values are shown in Table 17. For load configurations shown in figures 47 (a) to (c) (type C, D or E) the equivalent internal load Ri 216 will be an inverting load.

Table 17 - Equivalent load resistances

When the V_ADC-Forcing circuit 721 (figure 41) is used to implement the force- voltage-measure-current or the third or fourth current-searching algorithm, the corresponding functions G and H , defined in equations 18 and 33, will be dependent on the internal load Ri.

Comparing equation 94 to equations 20 and 37, it can be seen that W_Rl represents G ¹ in the force- voltage-measure-current algorithm and H^~ in the force-current measurement voltage algorithm, i.e.:

Equation il2

Equation 113

Therefore, for all the V_ADC-Forcing circuit 721 with W_R1 defined in equations 105 to 109, the corresponding G and H for the force- voltage-measure-current algorithm and the third and fourth force-current-measure-voltage algorithm are given by equations 112 and 113.

SPECIFIC EXAMPLES OF IMPLEMENTATION

Example 1 -System with Non-linear Inverting Load Element R₇ 216

In a first alternative specific example, depicted in figure 56, the system includes a V_ADC-Forcing circuit described in figure 55 (c) with the DAC 904 implemented by the circuit shown figure 50. A first-order RC filter is used for the DAC 904. In the figure, both the PDM generator and the frame counter 900 have 8-bit (256 distinct levels) resolution. The analog full-scale voltage range is from 0 V to 5 V.

Current Measurement

Using the V_ADC-Forcing circuit in figure 56, a force-voltage-measure-current system can be constructed as described previously in the specification. The resultant system is shown in figure 57. In this example, let us assume that we need to force 3.75 V at the output 204 (V_AD_C)- According to equations 72 and 103, the value of k_ADC should be set as follows:

Equation 114

Jr - l-

^KADC ~ ^K force

To calibrate this ammeter for a 5-bit current resolution, 32 currents, each with an increment of 1/32 of the full-scale current, is applied to the output 204 in the manner shown in figure 58. For each current increment, the corresponding k DA_C from the frame counter is recorded. The result is tabulated as that listed in Table 18. In this example, the full-scale current range is from -1 mA to 0.9375 mA. Note that Table 18 is a mapping of the function G^~l defined in equation 18. To find G , we simply invert the second and third column of the table.

Table 18 - A 5 -bit look-up table for the ammeter

After the calibration, the system in figure 57 can then be used to set 3.75 V at an unknown external load 206, from which the appropriate load current I_out flows. The resultant bit code k _DA_C is then compared to the counts found in Table 18. For example, if an unknown current is applied and a k _DAC of 108 is produced, the unknown current will be found to be 0.0625 mA.

Current Generation

Using the VAoc-Forcing circuit in figure 56, the force-current-measure-voltage system shown in figure 33 can be constructed. The resultant system is shown in figure 59. This system employs the third current-forcing algorithm described previously, where k_ADC is controlled by a search unit 928 that observes the value of koAC As shown in figure 59, the digital logic 928 includes a look-up table, a digital comparator 930 and an integrator 932.

The lookup table 933 containing H needs to be calibrated whenever a new value of I_fo_rce applied at input 202 is required. That can be done using the set-up shown in figure 60. During calibration, the I_out is set to I_fo_rce by an external current reference 926 while k_ADC is swept. For each kADC increment, the corresponding value koAC from the frame counter 900 is recorded. The resultant lookup table lists the value of ko_AC as a function of k_ADC, i-e-, the function H^"1 defined in equation 37. An example lookup- table is shown in Table 19.

Table 19 - An 8-bit look-up table for the current source

After calibration, an external load 206 can be applied to the output 204 of the system as shown in figure 59. A current of value I_force will be forced into the external load R₂ 206 when the system is in equilibrium.

Example 2 - System with Linear Load Element R₇

In a second alternative specific example, depicted in figure 61, the system is constructed using the V_ADC-Forcing circuit described in figure 55 (a) with the DAC 904 implemented by the circuit in Figure 50. Again, a first-order RC filter is used for the DAC 904. In the figure, both the PDM generator and the frame counter 900 have 10-bit (1024 distinct levels) resolution. The analog full-scale voltage range is from 0 V to 2.56 V.

The architectures/operations of the Force- voltage and Force-current systems derived from the V_ADC-Forcing circuit in figure 61 is similar to those described with regards to the first alternative specific example described above. However, because the internal load element Ri is linear, calibration/measurement method described in connection with a linear resistive internal load Ri 216 can be used.

As both the equivalent ADC and DAC 904 in the V_ADC-Forcing circuit shown in figure 61 have 10-bit resolution over a full scale of 0 V to 2.56 V, the LSB voltage (V_LSB) can be defined as follows:

Equation 115

2.56V

' LSB ~ ' LSB-DAC ~ ' LSB-ADC = 2.5mV 1024

In a non-limiting implementation, the resistance R₂ in the RC circuit 932 in figure 61 is 2.5 kohms, then from equation 110, the equivalent internal load Ri 216 in the system will also equal to 2.5 kohms. This resistance value described in equation 110 into equation 56 to get:

Equation 116

h_ut = ^{kADC ~ k c} * V_LSB +I_φel = \k_mc -k_DAC] x lμA +h_ffset

^Λli

Calibration

The method summarised in Table 9 can be used to calibrate the system depicted in figure 61. In this example, we first set kADC to an arbitrary reference level (k_force-_ref) at 612. For the calibration process, in a first step a current reference (I_fo_rce-_ref) 936 of +200uA is applied to the system as shown in figure 62 and the value of k_DAC as ko_Ac- _caii is recorded. In a second step, the output 204 is disconnect from any external sources/loads to make current I_out zero and the corresponding ko_AC as ko_Ac-_caβ is recorded. The resultant calibration points are summarised in Table 20. These calibration values will be used in generating the lookup tables required in the force- voltage/force-current algorithms described herein below.

Table 20 - Calibration Points in the Example

Current Measurement

In a non-limiting implementation, the force- voltage-measure-current system described in connection with figure 37 and with reference to equation 57 can be constmcted using the V_ADC-Forcing circuit shown in figure 61. The resultant system is shown in figure 63. For this current-measurement system, the lookup table G 936 is a simple expression generated by calibration data. If the calibration points in Table 20 are substituted into equation 66 and the equation is simplified, the following can be obtained:

Equation 117 h_ut = G(k^*DAc , k_force ) = [k_force - k _Ac -7] x\μA

Knowing equation 117, the calibrated system in figure 63 can then be used to set an arbitrary voltage at output 204, from which a current I_out flows. In this example, let us assume that we need to force 1.28 V at the output 204 (V_ADC)- That means the corresponding value of k_AD_C will be given by equations 72 and 103 as:

Equation 118

The resultant bit code k _DA_C can then be substituted in equation 117 to find the current value for I_out at output 204. For example, if an unknown current is applied and a k _DA_C of 866 is produced, the value of the unknown current I_out will be given by:

I_out = G(866,512) ^' = [512 - 866 - 7] x \μA = -361μA

Equation 119

I_out = r (866,512) = [512- 866- 7l]xl t-4 = -361 ^

Current Generation

In accordance with a specific non-limiting implementation, an embodiment of the force-current-measure-voltage system shown in figure 23 (c) can be constructed using the V_ADC-Forcing circuit in figure 61. The resultant system is shown in figure 64. For this force-current system, the lookup table H^"1 is a simple expression generated by calibration data. If we substitute the calibration points in Table 20 into equation 69 and 68, the following is obtained:

Equation 120

LU force) = ^

Equation 121

j^. - ^~l(k T Λ \ - k ^force 7

Knowing the result of equation 121, the system can then be used to set an arbitrary current at output 204 node. In this example, let us assume that a current if_0rCe of 50uA must be forced at the output 204. The corresponding relationship in equation 121 can be simplified as: Equation 122

'^ζDAC ⁼ H V^ζADC ' lo t )

~ 7

After defining the lookup table H^_1 from the calibration data, an external load R₂ 206 can be applied to the output 204 as shown in figure 64. With H^_1 defined in equation 122, a current of value I_fo_rce=50uA will be forced into the load R₂ 206 when the system is in equilibrium.

The general structure of the circuits shown in figures 63 and 64 is shown in figures 65 and 66 respectively. The set of circuit components labelled 1050 in figures 63 to 66 implement an equivalent functionality.

As shown in figure 65, the system includes an input 1012 for receiving a digital forced voltage signal, an output 204 suitable for releasing to an external load a signal approximating the digital forced voltage signal, a first circuit segment and a second circuit segment. The first circuit segment is between the input 1012 and the output 204. The second circuit segment is connected in a feedback arrangement between the output 204 and the first circuit segment and provides the first circuit segment with the voltage associated with the output 204. The first circuit segment includes a first digital-to-analog converter module 904, a difference module 934, an analog-to-digital converter module 906, a second digital-to-analog converter module 1002, an analog accumulation device 1000, an intermediate voltage point 214 and in internal load 216 between the intermediate voltage point 214 and the output 204. The first digital-to- analog converter module 904 processes the digital forcing parameter signal and generates an analog value of the digital forcing parameter signal. The difference module 934 processes the analog value of the digital forcing parameter signal as well as the voltage associated with the output of the circuit device and generates a difference signal. The polarity of the difference module 934 is reversed if internal load 216 is an inverting load. The analog-to-digital converter module 906 processes the difference signal and generates a digital representation of the difference signal. The second digital-to-analog converter module 1002 processes the digital representation of the difference signal and generates an analog representation of the difference signal. The analog accumulation device 1000 generates a second voltage signal on the basis of the analog representation of the difference signal and applies the second voltage signal to the intermediate voltage point 214. The application of the second voltage signal to the intermediate voltage point 214 causes a change in either one of the voltage signal or the current signal at the output such that a voltage approximating the forced voltage signal is caused at the output 204.

In a first non-limiting implementation, the analog accumulation device 1000 includes an analog integrator module. In a second non-limiting implementation, the analog accumulation device 1000 includes a low-pass filter unit. It will be appreciated that other suitable equivalent devices instead of a low-pass filter unit may be used without detracting from the spirit of the invention.

The system shown in figure 65 also includes a current measurement circuit having a first input for receiving the digital representation of the difference signal generated by the analog-to-digital converter module 906, a second input for receiving a digital forced voltage signal from input 1012, a digital filter implementing accumulation functionality 900, search logic 936 and an output 938. The digital filter 900 is adapted for processing the difference signal received at the first input for generating' an average voltage value. The search logic 936 receives the digital forced voltage signal and the average voltage value from the second input and the digital filter 900.

The search logic 936 derives a certain current measurement on the basis of the digital forced voltage signal and the average voltage value such that, when the system is in equilibrium, the certain current measurement is indicative of an approximation of measurement of the current flowing at the output 204 of the voltage generating circuit.

The certain current measurement is then released at the output 938.

Figure 67 shows an alternative general structure of the circuit shown in figure 66. In this alternate configuration, the digital filter 900 of figure 66 present in the feedback path has been replaced by digital filter 1090 located between ADC 906 and DAC

1002. Digital filter 1090 may implement any suitable accumulation functional element such as for example a digital integrator. The output of digital filer 1090 is provided to the search control logic 940. It will be appreciated that binary searches can also be performed by replacing the digital filter 1090 with a successive- approximation circuit (SAR) module without detracting from the spirit of the invention. The corresponding alternate stmctures associated with the circuit shown in figure 65 will be readily apparent to the person skilled in art upon a reading of this specification and as such will not be described further here.

Other specific examples of implementation of this invention are presented in C. K. L. Tarn, G. W. Roberts, "A Robust DC Current Generation and Measurement Technique for Deep Submicron Circuits", Proc. IEEE International Symposium on Circuits and Systems, Vol. 1, pp. 719-722, May 6, 2001. The contents of this document are hereby incorporated by reference.

SPECIFIC PHYSICAL IMPLEMENTATION

Those skilled in the art should appreciate that in some embodiments of the invention, all or part of the functionality previously described herein with respect to the circuit device and system may be implemented as pre-programmed hardware or firmware elements (e.g., application specific integrated circuits (ASICs), FPGA chips, ROM, PROM, EPROM, etc.), or other related components.

For example, the above described circuits may be incorporated in IC generally, diagnostic tools, IC testing equipment, on-chip testing and IC including on-chip testing functionality amongst others. Specific non-limiting examples of use of the above-described system include:

• the measurement of leakage currents in bonding pads of ICs; • continuity tests for bonding wires;

• parametric testing of logic output pins;

• parametric testing of output drivers (analog/digital);

• IDDQ testing of an IC or modules on an IC; • parametric testing of resistors/diodes/transistors;

• parametric testing of voltage/current sources, bias networks or other analog components.

Although the present invention has been described in considerable detail with reference to certain preferred embodiments thereof, variations and refinements are possible without departing from the spirit of the invention. Therefore, the scope of the invention should be limited only by the appended claims and their equivalents.

Claims

CLAIMS:

1. A circuit device suitable for use in performing a DC parametric test on an external load, said circuit device comprising: a. an input suitable for receiving a forcing parameter signal; b. an output suitable for releasing to the external load a signal approximating the forcing parameter signal; c. a first circuit segment between said input and said output comprising: i. a search entity; and ii. an intermediate voltage point; iii. an internal load between said intermediate voltage point and said output; d. a second circuit segment connected in a feedback arrangement with said first circuit segment, said second circuit segment providing the search entity in the first circuit segment with a first voltage signal indicative of the voltage at the output; e. said search entity being adapted for: i. generating a second voltage signal on the basis of said forcing parameter signal and the first voltage signal received from said second segment; ii. applying said second voltage signal to said intermediate voltage point thereby causing a change in either one of the voltage signal or the current signal at said output such that a signal approximating the forcing parameter signal is caused at said output.

2. A circuit device as defined in claim 1, wherein said search entity includes: a. an analog-to-digital converter module for processing the voltage at the output to generate a digital approximation of the voltage signal at the output; b. a search unit for generating a digital target voltage on the basis the digital approximation of the voltage signal at the output and the forcing parameter signal; c. a digital-to-analog converter module between said search unit and said intermediate voltage point, said digital-to-analog converter module being adapted for: i. processing the digital target voltage to generate the second voltage signal; ii. applying said second voltage signal to said intermediate voltage point thereby causing a change in either one of the voltage signal or the current signal at said output such that a signal approximating the forcing parameter signal is caused at said output.

3. A circuit for performing a DC parameter test on an external load, the circuit comprising: a. a circuit input for receiving a forcing parameter signal; b. a circuit output for connection to the external load; c. a search unit having a first input connected to the circuit input and having a second input and an output; d. a circuit module having digital-to-analog conversion functionality and load functionality connected between the output of the search unit and the circuit output; and e. an analog-to-digital converter (ADC) connected between the circuit output and the second input of the search unit, wherein the search unit is adapted to generate a digital target voltage at its output on the basis of a voltage at the circuit output and the forcing parameter signal whereby a signal approximating the forcing parameter signal is derived at the circuit output.

4. A circuit as defined in claim 3, wherein the circuit module having digital-to- analog conversion functionality and load functionality includes: a. a low-pass filter module one side of which is connected to the circuit output; b. a pulse generator module connected between the output of the search unit and another side of the low-pass filter module.

5. A circuit as defined in claim 3, wherein the circuit module having digital-to- analog conversion functionality and load functionality includes: a. an internal load one side of which is connected to the circuit output; b. a digital-to-analog converter (DAC) connected between the output of the search unit and another side of the internal load.

6. A circuit device as defined in claim 5, wherein said internal load is a linear non- inverting load.

7. A circuit device as defined in claim 6, wherein said internal load includes at least one linear resistor element.

8. A circuit device as defined in claim 7, wherein said internal load includes at least one RC circuit element.

9. A circuit device as defined in claim 5, wherein said internal load is a non-linear and inverting load.

10. A circuit device as defined in claim 9, wherein said internal load includes at least one MOS circuit.

11. A circuit device as defined in claim 10, wherein the MOS circuit includes at least one element selected from the set consisting of a CMOS inverter, a PMOS circuit and NMOS circuit.

12. A circuit device as defined in claim 5, wherein said forcing parameter signal is indicative of a forced voltage.

13. A circuit device as defined in claim 3, wherein said forcing parameter signal is indicative of a forced current.

14. A circuit device as defined in claim 3, wherein said forcing parameter signal is in a digital format.

15. A circuit device as defined in claim 12, wherein said search unit includes: a. a digital comparator for generating a digital difference voltage signal dependent on the difference between the signal indicative of a forced voltage and the digital approximation of the voltage signal at the output of the circuit device; b. a digital integrator module adapted for processing the digital difference voltage signal to derive the digital target voltage; c. an output for releasing the digital target voltage for processing by the digital-to-analog converter (DAC).

16. A circuit device as defined in claim 12, wherein said search unit includes: a. an analogue-to-digital converter module suitable for processing the signal indicative of a forced voltage to generate a corresponding digital forced voltage signal; b. a digital comparator for generating a digital difference voltage signal dependent on the difference between the digital forced voltage signal and the digital approximation of the voltage signal at the output of the circuit device; c. a digital integrator module adapted for processing the digital difference voltage signal to derive the digital target voltage; d. an output for releasing the digital target voltage for processing by the digital-to-analog converter.

17. A circuit device as defined in claim 3, wherein said analog-to-digital converter comprises: a. an analog comparator for: i. receiving a signal indicative of the voltage at the output and a tracking voltage; ii. generating a difference signal on the basis of the signal received in i.; b. a digital integrator for receiving the difference signal and generating successive digital approximations of the voltage signal at the output of the circuit device; c. a feedback circuit for processing the successive digital approximations of the voltage signal to generate the tracking voltage and provide the tracking voltage to said analog comparator.

18. A circuit device as defined in claim 17, wherein said feedback circuit including a digital-to-analog converter.

19. A circuit device as defined in claim 3, wherein said analog-to-digital converter (ADC) comprises: a. an analog comparator for: i. receiving a signal indicative of the voltage at the output and a tracking voltage; ii. generating a difference signal on the basis of the signal received in i.; b. a successive-approximation circuit (SAR) module for receiving the difference signal and generating successive digital approximations of the voltage signal at the output of the circuit device; c. a feedback circuit for processing the successive digital approximations of the voltage signal to generate the tracking voltage and provide the tracking voltage to said analog comparator.

20. A system for providing a current measurement suitable for use in performing a DC parametric test on an external load, said system comprising: a. a voltage generating circuit device comprising: i. an input suitable for receiving a signal indicative of a forced voltage; ii. an output suitable for releasing to the external load a signal approximating the forced voltage; iϋ. a first circuit segment between said input and said output comprising:

1. a search unit; and

2. an intermediate voltage point;

3. an internal load between said intermediate voltage point and said output; iv. a second circuit segment connected in a feedback arrangement with said first circuit segment, said second circuit segment providing the search unit in the first circuit segment with a first voltage signal indicative of the voltage at the output; v. said search unit being adapted for:

1. generating a second voltage signal on the basis of said signal indicative of a forced voltage and the first voltage signal received from said second segment;

2. applying said second voltage signal to said intermediate voltage point thereby causing a change in either one of the voltage signal or the current signal at said output such that a voltage approximating the forced voltage is caused at said output; b. a current measurement circuit including: i. a first input for receiving a first signal derived from the second voltage signal; ii. a second input for receiving a second signal derived from the signal indicative of the forced voltage; iii. search logic coupled to said first and second inputs, said search logic being adapted for deriving a certain current measurement on the basis of first signal and said second signal signal; iv. an output for releasing the certain current measurement, when the system is in equilibrium, said certain current measurement being indicative of an approximation of measurement of the current flowing at the output of the voltage generating circuit when the signal indicative of the forced voltage is applied to the output of the voltage generating circuit.

21. A system as defined in claim 20, wherein the first signal derived from the second voltage signal includes a digital representation of the second voltage signal.

22. A system as defined in claim 21, wherein the second signal derived from the signal indicative of the forced voltage includes a digital approximation of the signal indicative of the forced voltage.

23. A system for providing a current measurement for use in performing a DC parametric test on an external load, said system comprising: a. a voltage generating circuit device comprising: i. a circuit input for receiving a signal indicative of a forced voltage; ii. a circuit output for connection to the external load; iii. a search unit having a first input connected to the circuit input and having a second input and an output; iv. a circuit module having digital-to-analog conversion functionality and load functionality connected between the output of the search unit and the circuit output; and v. an analog-to-digital converter (ADC) connected between the circuit output and the second input of the search unit, wherein the search unit is adapted to generate a digital target voltage at its output on the basis of a voltage at the circuit output and the signal indicative of the forced voltage whereby a signal approximating the forced voltage is applied at the circuit output; b. a current measurement circuit including: i. a first input for receiving a first signal derived from the digital target voltage; ii. a second input for receiving a second signal derived from the signal indicative of the forced voltage; iii. search logic coupled to said first and second inputs, said search logic being adapted for deriving a certain current measurement on the basis of said first signal and said second signal such that when the system is in equilibrium, said certain current measurement is indicative of an approximation of measurement of the current flowing at the output of the voltage generating circuit when the signal approximating the forced voltage is applied to the output of the voltage generating circuit; iv. an output for releasing the certain current measurement.

24. A system as defined in claim 23, wherein the second signal derived from the signal indicative of the forced voltage includes a digital approximation of the forced voltage signal.

25. A system as defined in claim 23, wherein the circuit module having digital-to- analog conversion functionality and load functionality includes: a. a low-pass filter module one side of which is connected to the circuit output; b. a pulse generator module connected between the output of the search unit and another side of the low-pass filter module.

26. A system as defined in claim 23, wherein the circuit module having digital-to- analog conversion functionality and load functionality includes: a. an internal load one side of which is connected to the circuit output; b. a digital-to-analog converter (DAC) connected between the output of the search unit and another side of the internal load.

27. A system as defined in claim 23, wherein the search logic of said current measurement circuit includes a data structure having a plurality of entries, each entry providing a mapping between a data element conveying a given target voltage and a data element conveying the forced voltage to a corresponding current measurement.

28. A system as defined in claim 27, wherein the data element conveying the target voltage includes a digital approximation of the target voltage signal.

29. A system as defined in claim 27, wherein said data structure is stored on a unit including a device selected from the set consisting of a RAM, ROM, PROM, EPROM and EEPROM.

30. A system as defined in claim 29, wherein the device includes RAM.

31. A circuit device suitable for use in performing a DC parametric test on an external load, said circuit device comprising: a. a circuit input for receiving a signal indicative of a forced current; b. a circuit output for connection to the external load; c. a search unit having a first input connected to the circuit input and having a second input and an output; d. a circuit module having digital-to-analog conversion functionality and load functionality connected between the output of the search unit and the circuit output; and e. an analog-to-digital converter (ADC) connected between the circuit output and the second input of the search unit; wherein the search unit is adapted to generate a target voltage value at its output on the basis of a voltage at the circuit output and the signal indicative of a forced current whereby a signal approximating the signal indicative of a forced current is derived at the circuit output.

32. A circuit device as defined in claim 31, wherein the circuit module having digital- to-analog conversion functionality and load functionality includes: a. a low-pass filter module one side of which is connected to the circuit output; b. a pulse generator module connected between the output of the search unit and another side of the low-pass filter module.

33. A circuit device as defined in claim 31, wherein the circuit module having digital- to-analog conversion functionality and load functionality includes: a. an internal load one side of which is connected to the circuit output; b. a digital-to-analog converter (DAC) connected between the output of the search unit and another side of the internal load.

34. A circuit device as defined in claim 31, wherein said search unit includes a data structure having a plurality of entries, each entry providing a mapping between: a. a data element conveying the voltage signal at the output of the circuit device and a data element conveying a given forced current; and b. a data element conveying a target voltage.

35. A system as defined in claim 34, wherein: a. the data element conveying the voltage signal at the output includes a digital approximation of the voltage signal at the output; b. the data element conveying the target voltage includes a digital representation of the target voltage.

36. A circuit device as defined in claim 34, wherein said data structure is stored on a unit including a device selected from the set consisting of a RAM, ROM, PROM, EPROM and EEPROM.

37. A circuit device as defined in claim 36, wherein the device includes RAM.

38. A circuit device as defined in claim 31, wherein said search unit provides a mapping between: a. data elements conveying target voltages and a data element conveying a given forced current signal; and b. data elements conveying voltage signals at the output of the circuit device.

39. A system as defined in claim 38, wherein: a. the data elements conveying target voltages include digital approximations of target voltages; b. data elements conveying voltage signals at the output of the circuit device include digital approximations of the voltage signals at the output.

40. A circuit device as defined in claim 38, wherein said data stracture is stored on a unit including a device selected from the set consisting of a RAM, ROM, PROM,

EPROM and EEPROM.

41. A circuit device as defined in claim 40, wherein the device includes RAM.

42. An IC circuit including a circuit device of the type described in claim 1.

43. An IC circuit including a plurality of circuit devices of the type described in claim 1.

44. An IC circuit including a circuit device of the type described in claim 3.

45. An IC circuit including a plurality of circuit devices of the type described in claim 3.

46. An IC circuit including a system of the type described in claim 20.

47. An IC circuit including a plurality of systems of the type described in claim 20.

48. An IC circuit including a system of the type described in claim 23.

49. An IC circuit including a plurality of systems of the type described in claim 23.

50. An IC circuit including a circuit device of the type described in claim 31.

51. An IC circuit including a plurality of circuit devices of the type described in claim 31.