WO2003071739A1

WO2003071739A1 - A method and apparatus for error controlling in high speed wireless packet data service

Info

Publication number: WO2003071739A1
Application number: PCT/CN2002/000106
Authority: WO
Inventors: Chengming Wu; Xiaohua Liu; Xiaobin Wu
Original assignee: Linkair Communications,Inc.
Priority date: 2002-02-21
Filing date: 2002-02-21
Publication date: 2003-08-28
Also published as: CN1231022C; AU2002237170A1; CN1504033A

Abstract

This invention discloses a method for error controlling in high speed wireless packet data service, wherein: adopts double channel control for transmitted packet data, implements the error controlling of the transmitted packet data by setting waiting flag bit and setting the transmitted packet counter. This invention discloses an apparatus for error controlling in high speed wireless packet data service, wherein: by setting waiting flag bit and transmitted packet counter for parity channel in double channel controller, implements DSW ARQ parity channel scheduling, implements error controlling for transmitted packet. By use of the method of this invention it advances the utilization rate of channels, thus advances the validity of the whole communication system; at the same time, it facilitates dispatch and fault diagnosis and scales down the systemic complexity congratulation and time lag.

Description

A high-speed wireless packet data service

Method and device for error control

The present invention relates to the field of electrical communication technology, and in particular to an error control method and device for high-speed wireless packet data services.

Background technique

The rapid development of communication systems and the widespread application of electronic computers require data transmission to provide unprecedented services. Whether it is traditional long-distance data communication, satellite communication, or computer network communication, there are increasingly higher requirements for the reliability of data transmission, making it an urgent problem to be solved in the field of communication.

Compared with the 2nd generation mobile communication system, the 3rd generation mobile communication system is required to support multiple services such as voice, image, and data, especially multimedia and high-bit-rate packet data services. To achieve high data rate transmission, an efficient and reliable communication mechanism must be used. Therefore, the high-dimensional modulation method is applied to the 3G (third generation mobile communication) system, thereby increasing the peak rate of the system. However, the problem is that the reliability of the system is seriously challenged. Because on the wireless channel, multipath, glare, and Doppler frequency shifts will seriously degrade the performance of high-dimensional system systems. Random errors and burst errors coexist. If effective measures are not taken, errors in data communications will not be satisfied. The bit rate is less than 10. For this reason, in 3G systems, it is recommended to use HARQ (Hybrid Auto Repeat Repeat) as a link error control technology to ensure the reliable transmission of packet data.

Window based Selective Repeat (SR) is a general ARQ technology adopted by many systems. It only retransmits packets that receive errors and is not sensitive to delay. However, it must use a sequence number to identify each packet, which increases the overhead of the frame. SR makes full use of channel resources. However, for the receiving end, the memory requirements are high, and the receiving end must ensure that the sequence number of the sent packet is reliably confirmed. Stop- and-wai t is a simple ARQ technique This method requires the least overhead, low complexity at the receiving end, and small storage requirements. But its biggest disadvantage is that the acknowledgment signal is untimely, so when the sender sends a packet, it must wait for the acknowledgment signal of this packet instead of sending the next packet, which greatly wastes channel resources and has low channel utilization. Dual channel s top-and-wait ARQ (DSW) technology absorbs the advantages of both Stop-and-wait ARQ and SR ARQ. The channel utilization is about twice that of Stop-and-wait ARQ. However, the above-mentioned prior art ARQ method does not solve how to maintain the timing of sending packet data quickly and efficiently in a high-speed mobile environment, and this is the key to successfully implementing the DSW ARQ technology.

Summary of the Invention

An object of the present invention is to provide an error control method and device for a high-speed wireless packet data service. It proposes a new method called ARQ, which adopts silent channel control for the transmitted packet data. The error control of the transmitted packet data is completed by the wait flag bit set on the dual channel and the transmitted packet counter. At the same time, the scheduling of DSW ARQ parity channels is implemented. The error control method of the present invention can also be applied to a wireless communication system for high-speed packet data services, so as to realize the timing arrangement of the parity channels in DSW technology and improve the utilization rate of channel resources. The implementation of the present invention can achieve the purposes of high channel utilization rate, convenient scheduling and fault diagnosis, and reducing the complexity and delay of the system, thereby improving the effectiveness of the entire communication system.

The technical solution of the present invention is:

The invention provides an error control method for a high-speed wireless packet data service, which includes: the transmitting end adopts dual channel control for the transmitted packet data; the receiving end receives the data transmitted from the transmitting end, and feeds back a signal to the transmitting end The transmitting end processes the packet data to be transmitted according to the signal fed back by the receiving end.

The use of dual-channel control on the transmitted packet data by the transmitting end includes: setting a wait flag bit on the dual channel, which can identify the packet data transmission status of each single channel of the dual channel.

The adopting dual-channel control on the transmitted packet data by the transmitting end includes: A packet counter is used to count packet data of each single channel of the dual channel. The use of dual-channel control on the transmitted packet data by the transmitting end includes: setting a waiting flag bit on the dual channel, where the waiting flag bit can identify a packet data transmission status of each single channel of the dual channel; A packet counter is used on the channel to count packet data of each single channel of the dual channel.

The use of dual-channel control on the transmitted packet data by the transmitting end includes: setting a wait flag bit on the dual channel, where the wait flag bit can identify a packet data transmission status of each single channel of the dual channel; A packet counter is used to count the packet data of each single channel of the Chinese channel on the channel; a retransmission counter is used to count the packet data of each single channel of the Huan channel on the dual channel.

The use of dual-channel control on the transmitted packet data by the transmitting end includes: setting a wait flag bit on the dual channel, where the wait flag bit can identify a packet data transmission status of each single channel of the dual channel; A packet counter is used to count the packet data of each single channel of the dual channel on the channel; a retransmission counter is used to count the packet data of each single channel of the dual channel on the dual channel; A channel timer is used on the channel to time the packet data of each single channel of the dual channel.

In the method, the steps include:

When the transmitting end starts to send packet data, it initializes the waiting flag bit and the packet counter set on the dual channel;

Initialize the retransmission counter set on the dual channel and set the maximum number of retransmissions; initialize the channel timer set on the default channel and set the timer length; when the receiving end correctly receives a packet on the dual channel When data is received, an ACK signal is fed back to the corresponding channel of the transmitting end, and the transmitting end selects according to the feedback ACK signal: sending new packet data or setting the waiting flag position to 1;

When the receiving end does not correctly receive a packet data on the dual channel, the NACK signal is fed back to the corresponding channel of the transmitting end, and the transmitting end according to the feedback NACK signal, the maximum number of retransmission times, and the channel Timer length selection: resend the original packet or send new packet data or set the wait flag bit to 1.

In the method, the steps include:

At the transmitting end, when the transmitting end sends a packet first, the channel timer is started. When the timer expires, it is determined whether the retransmission counter of the channel is greater than the maximum number of retransmissions of the channel. If so, it is determined whether to send a new packet. If not, retransmit the original packet on the channel; if the transmitting end receives the response frame of the receiving end as an ACK signal in (410), determine whether to send a new packet, enter (413), delete the old data and prepare Send new data; if it is a NACK signal, go to (412) to determine whether the retransmission counter of the channel is greater than the maximum number of retransmissions of the channel. If so, determine whether to send a new packet and then go to (413) to delete the old one. Data and prepare to send new data, if not, resend the original packet on the channel (414);

At the receiving end, when the receiving end receives a packet (401) on a channel, it first enters (402) to perform a CRC check. If it is received correctly, it sends an ACK signal to the transmitting end (404) on the channel. If it is not correct, Send a NACK signal to the transmitting end (403) on this channel.

In the method described above, the dual channel may be an odd channel and an even channel, and an odd channel and an even channel in a window ARQ are set by setting a waiting flag bit and a packet counter on the odd channel and the even channel. Channel timing.

In the method, the specific steps include:

Step 101, initialization at the transmitting end: the odd and even channel waiting flag positions can be set to 0, the odd and even channel transmission packet counters can be set to 0, and the odd and even channel retransmission counters can be set to 0;

Set the maximum number of retransmission counters on the odd channel and even channel according to the system requirements; determine the odd channel and The length of the timer on the even channel; In step 102, a new packet is sent on the odd channel, and the decrement counter on the odd channel is incremented by 1 _{: the} retransmission counter is set to 1, the wait flag bit is set to 0, and the timer of the odd channel is started;

Step 103: A new packet is sent on the even channel, and the packet counter on the even channel is incremented by 1: the retransmission counter is set to 1, the wait flag bit is set to 0, and the timer of the even channel is started;

Step 104: If the timer on the odd channel times out and no response frame of the sending end is received, determine whether the retransmission counter of the odd channel exceeds the maximum number of retransmissions;

Step 105: If the count of the odd channel retransmission counter is less than or equal to the maximum number of retransmissions, the original packet is retransmitted on the odd channel, and the retransmission counter of the odd channel is increased by 1, and the timer is started, and the sending packet counter is unchanged. If the count of the odd channel retransmission counter is greater than the maximum number of retransmissions, determine the status of the channel waiting flag bit on the even channel;

Step 106: If the timer on the even channel times out and no response frame of the sending end is received, determine whether the retransmission counter of the even channel exceeds the maximum number of retransmissions;

Step 107: If the count of the retransmission counter of the even channel is less than or equal to the maximum number of retransmissions, the original packet is retransmitted on the even channel, and the retransmission counter of the even channel is increased by 1, and the timer is started, and the transmission packet counter is not changed. If the count of the even channel retransmission counter is greater than the maximum number of retransmissions, determine the status of the channel waiting flag bit on the odd channel;

Step 108, if the timer on the odd channel does not expire and a response frame is received, then when the response frame is ACK, determine the status of the channel wait flag bit on the even channel; when the response frame is NACK, go to step 105;

Step 109: If the waiting flag bit on the even channel is 1, then send a new packet in turn on the odd channel and the even channel;

Step 110: If the waiting flag bit on the even channel is 0, determine whether the odd channel packet counter is equal to the even channel packet counter, and if so, send a new packet on the odd channel;

If the odd channel packet counter is equal to the even channel packet counter plus 1, the channel waiting flag position of the odd channel is 1, and go to step 111; If the odd channel packet counter is less than the even channel packet counter or the odd channel packet counter is greater than the even channel packet counter plus 1, the entire ARQ process is terminated, and an abnormal condition is diagnosed;

Step 111, if the timer on the even channel does not expire and a response frame is received, then when the response frame is ACK, determine the status of the channel waiting flag bit on the odd channel; when the response frame is NACK, go to step 107;

According to step 112, judging the odd channel waiting flag bit. If the odd channel waiting flag bit is 1, then send a new packet in turn on the even channel and the odd channel;

Step 113: If the odd channel waiting flag bit is 0, determine whether the even channel packet counter is equal to the odd channel packet counter minus 1, and if so, send a new packet on the even channel; if the even channel packet counter is equal to the odd channel packet Counter, the channel waiting flag position of the even channel is 1, go to step 108;

If the even channel packet counter is greater than the odd channel packet counter or the even channel packet counter is less than the odd channel packet counter and decremented by 1, then the entire ARQ process is terminated and an abnormal condition is diagnosed;

Step 114: On the receiving end, perform a CRC check on the received packet. 'If it is received correctly, send an ACK signal on the corresponding channel to the transmitting end, and go to step 108; if it is not received correctly, send a NACK signal on the corresponding channel. To the transmitting end, go to step 108.

The Fang Fang is characterized in that it is particularly applicable to a TDD communication system.

The present invention also provides an error control device for a high-speed wireless packet data service, including: a Chinese channel controller, a channel transmitter, and a channel receiver; wherein: the dual-channel controller sends packet data to a channel transmitter The channel transmitter transmits the transmitted signal to the channel receiver via the channel; the dual-channel controller processes the packet data to be transmitted according to the signal fed back by the receiving end.

The dual channel controller includes at least a channel waiting flag bit; the dual channel controller may set the waiting flag bit to identify a packet data transmission status of each single channel of the dual channel. The dual channel controller includes at least a packet counter; the Chinese channel controller may set the packet counter to perform packet counting on the number of packets of each single channel of the dual channel.

The dual channel controller may include a channel waiting flag bit and a packet counter; wherein: the dual channel controller may set the waiting flag bit to identify a packet data transmission status of each single channel of the dual channel;

The Chinese channel controller may set the packet counter to count packet data of each single channel of the dual channel.

The dual channel controller may include a channel waiting flag bit, a packet counter, and a retransmission counter; wherein: the dual channel controller may set the waiting flag bit to identify a packet of each single channel of the dual channel Data transmission status; the dual channel controller can set the packet counter to count packet data of each single channel of the channel; the dual channel controller can set the retransmission counter to The retransmission count is performed on the packet data of each single channel of the dual channels.

The dual channel controller may include a channel waiting flag bit, a packet counter, a retransmission counter, and a channel timer; wherein: the dual channel controller may set the waiting flag bit to identify each of the dual channels. Packet data transmission status of a single channel; the dual channel controller can set the packet counter to count packet data of each single channel of the dual channel; the Chinese channel controller can perform the retransmission counter And configured to retransmit the packet data of each single channel of the dual channel; the dual channel controller may set the channel timer to packet data of each single channel of the dual channel Perform timing.

The channel transmitter is composed of at least two channel transmitters.

The channel receiver is composed of at least two channel receivers.

The device is characterized in that it further comprises a CRC checker, and the channel receiver inputs the received signal to the CRC checker for checking. The device is characterized in that the CRC checker is composed of at least two CRC checkers.

The beneficial effects of the present invention are: providing an error control method and device for a high-speed wireless packet data service. It proposes a new DSW ARQ method, which adopts dual-channel control for the transmitted packet data. Implemented the timing of DSW ARQ parity channels. The error control method of the present invention can also be applied to a wireless communication system for high-speed packet data services, to realize the timing arrangement of parity channels in DSW technology, and to improve the utilization rate of channel resources. The implementation of the present invention has the good effects of high channel utilization, convenient scheduling and fault diagnosis, reducing system complexity and delay, and further improving the effectiveness of the entire communication system.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 shows a block diagram of DSW ARQ implementation using the method of the present invention;

FIG. 2 shows a timing diagram for implementing the method of the present invention;

3 shows a schematic diagram of setting a channel packet counter and a channel waiting flag bit according to the method of the present invention;

FIG. 4 shows a working flowchart for implementing the method of the present invention at the transmitting end and the receiving end. detailed description

As shown in FIG. 1, at the transmitting end, the packet data to be transmitted is first input into the first buffer device 101, the packet data is buffered and queued in the buffer device 101, and then enters the dual-channel controller 102, the dual-channel controller 102 The structure will be described in detail in Figure 3. + After the queued packet data is processed in the dual-channel controller, whether to send new packet data on the odd channel or even channel or resend the original packet data, select The subsequent packet data is either sent to the odd channel transmitter 103, sent to the receiving end via the odd channel 105, or sent to the even channel transmitter 104, and sent to the receiving end via the even channel 106; The channel sends packet data as an example. After the sent packet data is sent through the odd channel 105, the odd channel receiver 107 corresponding to the receiving end receives the data, and then completes the CRC check through the odd channel CRC check device 109. If it is received correctly, Then Send an ACK (ACKnowledgment) signal to the sender. If the reception is incorrect, send a NACK (Non-ACKnowledgment) to request the sender to retransmit the data. Similarly, if the packet data is sent via the even channel 106, the receiver passes The even channel receiver 108 receives and completes the CRC check in the even channel CRC checking device 110. The packet data correctly received by the odd channel CRC check device 109 or the even channel CRC check device 110 is buffered in the second buffer device 111.

Figure 2 shows a timing diagram for implementing the method of the present invention. Referring to FIG. 2, it is assumed that the time period (Round Trip Delay) when the sender receives the ACK / NACK sent by the receiver is the time taken to send 3 packets, and the packet is sent on the odd channel as an example. A new packet is sent on the odd channel, and then another new packet is sent on the even channel. After a delay of 3 packets, the sender receives the ACK / NACK signal on the odd channel of the receiver. If it is ACK, the sender further determines whether to send a new packet on the odd channel. If it is NACK, the sender According to the initially set number of channel retransmissions and the maximum number of channel retransmissions, it is determined whether to resend the original packet on the odd channel, or to discard the original packet and send a new packet. The method for the sender to make a judgment based on the received ACK / NACK is described in detail in FIG. 3. Similarly, the ACK / NACK signal is received on the even channel, and the processing process is the same as that on the odd channel. If the timer of the odd channel times out and still does not receive the ACK / NACK signal from the receiving end, the sending end determines whether to send the original packet or send a new packet on the odd channel. The processing on the even channel is the same as on the odd channel.

Fig. 3 shows a schematic diagram of setting a channel packet counter and a channel waiting flag bit according to the method of the present invention. Referring to FIG. 3, the specific implementation process and criteria of the method are described here by taking packets sent on odd channels first and packets sent on even channels as an example.

The wait flag bits are set on the odd channel transmitter and the even channel transmitter, respectively, to identify the packet data transmission status of the odd channel and the even channel in different situations.

At the transmitting end, it is first initialized, and the parity channel wait flag bits are set to ¹⁰ respectively, and the parity channel transmission packet counters are set to 0, respectively. The retransmission counters are set to 0,

Wa i tf lag [odd] = 0; Wait-flag [even] = 0;

Count-pkt [odd] = 0;

Count-pkt [even] = 0;

N-resend [odd] = 0;

N-resend [even] = 0;

At the receiving end, if a packet is received correctly on the odd channel, an ACK is sent to the transmitting end, and if an incorrect packet is received, a NACK is sent to the transmitting end on the channel. The same is true for even channels.

The following is a case-by-case discussion of the working state of the channel counter and the wait flag bit on the transmitting end. (1) Take the odd channel as an example, send a new packet on the odd channel, add 1 to the packet counter on the odd channel, and start For odd-channel timers, the retransmission counter is set to 1, and the channel wait flag is set to 0.

(2) Taking an odd channel as an example, a packet is retransmitted on the odd channel, the retransmission counter of the channel is incremented by 1, and a timer is started, and the transmitted packet counter remains unchanged.

(3) The length of the timer is based on the average time from sending a packet to receiving the response frame (ACK / NACK) on the channel plus a small delay.

(4) The maximum number of channel retransmissions (Nresend_max) should be determined based on the needs of the entire system. This is assumed to be 3.

(5) If the timer on the channel expires and no response frame (ACK / NACK) from the sender is received, determine whether the retransmission counter of the channel exceeds the maximum number of retransmissions of the channel

(Nresend-max), if yes, go to (7), otherwise retransmit the original packet on this channel.

(6) #If a response frame is received, if it is an acknowledgement frame (ACK), go to (7). If it is a NACK, determine whether the retransmission counter of the channel exceeds the maximum number of retransmissions of the channel (NresencLmax), if yes, go to (7), otherwise retransmit the packet on the channel. (7) If it is on an even channel, go to (9); if it is an odd channel, determine the channel wait flag bit on the even channel. If it is 1, then send a new packet in turn on the even channel. If it is 0, Go to (8).

(8) Determine whether Count_pkt [odd] is equal to Count_ pkt [even], and if so, send a new packet on the odd channel. If Count-pkt [odd] equals

(Count-pkt [even] + l), the channel wait flag position of the odd channel is 1 (ait_flag [odd] = 1), if Coimt—pkt [odd] is less than Count_pkt [even] or

Count-pkt [odd] is greater than (Count — pkt [even] + l), the entire ARQ process should be terminated, and abnormal conditions should be diagnosed.

(9) Determine the channel wait flag bit of the odd channel. If it is 1, then send a new packet in turn on the even and odd channels. If it is 0, go to (10).

(10) Determine whether Count_ pkt [even] is equal to (Count_ pkt [odd] -1), and if yes, send a new packet on the even channel. If Count— pkt [even] equals

Count-pkt [odd], the channel waiting flag position of the even channel is 1 (Wait_flag [even] = 1), if Coimt_pkt [even] is greater than Count_ pkt [odd] or

Count-pkt [even] is less than (Count- kt [odd] -1), the entire ARQ process is terminated, and an abnormal condition is diagnosed.

FIG. 4 shows a working flowchart for implementing the method of the present invention at a transmitting end and a receiving end.

At the sending end, when the sending end sends a packet first, the channel timer is started. When the timer expires, it is determined whether the retransmission counter of the channel is greater than the maximum retransmission number of the channel (Nresend-max). If yes, refer to The steps shown in FIG. 3 determine whether to send a new packet, and if not, retransmit the original packet on the channel. If the sender receives a response frame (ACK / NACK) from the receiver in step 410, if it is an ACK signal, determine whether to send a new packet, and proceed to step 413, delete the old data and prepare to send new data; if it is a NACK signal, then Go to step 412, determine whether the retransmission counter of the channel is greater than the maximum number of retransmissions of the channel (Nresend-max), where ^ determines the maximum number of retransmissions of the channel (Nresend_max) is 3, such as If yes, determine whether to send a new packet, and then proceed to step 413, delete the old data and prepare to send new data, and if not, resend the original packet on the channel, step 414.

At the receiving end, when the receiving end receives a packet on a channel as shown in step 401, it first enters step 4G2 to perform a CRC check. If it is received correctly, it sends an ACK signal to the transmitting end as shown in step 404. If not, the NACK signal is sent to the transmitting end on the channel as shown in step 403.

The implementation of the present invention realizes the timing arrangement of the lake ARQ parity channel. The error control method of the present invention can also be applied to a wireless communication system for high-speed packet data services, to realize the timing arrangement of parity channels in the technology, and improve the utilization rate of channel resources. The implementation of the invention has the good effects of high channel utilization, convenient scheduling and fault diagnosis, reducing system complexity and delay, and further improving the effectiveness of the entire communication system.

The above specific embodiments are only for describing the present invention, but not for limiting the present invention.

Claims

Rights request

1. An error control method for a high-speed wireless packet data service, comprising: a transmitting end using Chinese channel control for packet data sent;

The receiving end receives the data transmitted from the transmitting end, and feeds back a signal to the transmitting end;

The transmitting end processes the packet data to be transmitted according to a signal fed back by the receiving end.

2. The method according to claim 1, wherein the use of dual-channel control on the transmitted packet data by the transmitting end comprises:

A waiting flag bit is set on the dual channel, and the waiting flag bit can identify the packet data transmission status of each single channel of the dual channel.

3. The method according to claim 1, wherein the use of dual-channel control on the transmitted packet data by the transmitting end comprises:

On a dual channel, a packet counter is used to count the packet data of each single channel of the dual channel.

4. The method according to claim 1, characterized in that the use of dual channel control on the transmitted packet data by the transmitting end comprises:

A waiting flag bit is set on the dual channel, and the waiting flag bit can identify the packet data sending status of each single channel of the dual channel; using a packet counter on the dual channel Packet data is counted in packets. . '

5. The method according to claim 1, wherein the use of dual-channel control on the transmitted packet data by the transmitting end comprises:

Setting a waiting flag bit on the dual channel, where the waiting flag bit can identify the packet data transmission status of each single channel of the dual channel;

Using a packet counter on a dual channel to perform packet counting on each single channel of the dual channel;

Packet data for each single channel of the dual channel using a retransmission counter on the dual channel Retransmit count.

6. The method according to claim 1, wherein the transmitting end adopts dual-channel control for the packet data sent comprises:

Using a retransmission counter on the Chinese channel to retransmit the packet data of each single channel of the dual channel;

A channel timer is used on the two channels to time the packet data of each single channel of the two channels.

7. The method according to claim 1, comprising the steps of:

When the transmitting end starts to send packet data, the waiting flag bit and the packet counter set on the dual channel are initialized;

Initialize the retransmission counter set on the dual channel and set the maximum number of retransmissions; initialize the channel timer set on the dual channel and set the timer length; when the receiver correctly receives a packet on the Chinese channel When data is transmitted, an ACK signal is fed back to the corresponding channel of the transmitting end, and the transmitting end selects according to the feedback ACK signal: sending new packet data or setting the waiting flag position to 1;

When the receiving end does not correctly receive a packet data on the dual channel, the NACK signal is fed back to the corresponding channel of the transmitting end. The transmitting end selects according to the feedback NACK signal, the maximum number of retransmission times, and the channel timer length: resend the original packet or Send new packet data or set the wait flag to 1.

8. The method according to claim 1, comprising the steps of:

At the transmitting end, when the transmitting end sends a packet first, the channel timer is started. When the timer expires, it is determined whether the retransmission counter of the channel is greater than the maximum number of retransmissions of the channel. If yes, judge whether to send a new packet, and if not, resend the original packet on the channel; if (410) the transmitting end receives the response frame of the receiving end as an ACK signal, determine whether to send a new packet, enter (413), delete the old data and prepare to send new data; if it is a NACK signal, enter (412) to determine whether the retransmission counter of the channel is greater than the maximum number of retransmissions of the channel; if so, determine whether to send a new packet, Then enter (413), delete the old data and prepare to send new data, if not, resend the original packet on the channel (414);

At the receiving end, when the receiving end receives a packet (401) on a channel, it first enters (402) for CRC calibration. If it is received correctly, it sends an ACK signal to the transmitting end (404) on the channel. If it is not correct, Send a NACK signal to the transmitting end (403) on this channel.

9. The method according to any one of claims 1 to 8, wherein the dual channels are odd channels and even channels, and by setting wait flag bits and packet counters on the odd channels and even channels Realize the scheduling of odd and even channels in DSW ARQ.

10. The method according to claim 9, the specific steps comprising:

Set the maximum number of retransmission counters on the odd and even channels according to system requirements; determine the odd and even channels according to the average time from sending a packet to receiving a response frame on the channel plus a delay The length of the timer;

Step 102: A new packet is sent on the odd channel, the packet counter on the odd channel is incremented by 1: 1: the retransmission counter is set to 1, the waiting flag bit is set to 0, and the timer of the odd channel is started;

Step 103: A new packet is sent on the even channel, and the packet counter on the even channel is incremented by 1 _{: the} retransmission counter is set to 1, the wait flag bit is set to 0, and the timer of the even channel is started;

Step 104: If the timer on the odd channel times out and no response frame of the sending end is received, determine whether the retransmission counter of the odd channel exceeds the maximum number of retransmissions; Step 105, if the count of the odd channel retransmission counter is less than or equal to the maximum number of retransmissions, the original packet is retransmitted on the odd channel, and the retransmission counter of the odd channel is increased by 1, and a timer is started, and the sending packet counter remains unchanged. If the count of the odd channel retransmission counter is greater than the maximum number of retransmissions, determine the status of the channel waiting flag bit on the even channel;

Step 107: If the count of the retransmission counter of the even channel is less than or equal to the maximum number of retransmissions, the original packet is retransmitted on the even channel, the retransmission counter of the even channel is increased by 1, and the timer is started, and the transmission packet counter remains unchanged. If the count of the even channel retransmission counter is greater than the maximum number of retransmissions, determine the status of the channel waiting flag bit on the odd channel;

Step 108, if the timer on the odd channel does not expire and a response frame is received, when the response frame is ACK, determine the status of the channel wait flag bit on the even channel; when the response frame is NACK, go to step 105;

Step 109: If the waiting flag bit on the even channel is 1, send a new packet in turn on the odd channel and the even channel;

If the odd channel packet counter is equal to the even channel packet counter plus 1, the channel wait flag position of the odd channel is 1, and go to step 111;

If the odd-channel packet counter is smaller than the even-channel packet counter or the odd-channel packet counter is greater than the even-channel packet counter plus 1, the entire ARQ process is terminated and an abnormal condition is diagnosed;

Step 111, if the timer on the even channel does not expire, and a response frame is received, then when the response frame is ACK, determine the status of the channel wait flag bit on the odd channel; when the response frame is NACK, go to step 107;

Step 112: Determine the odd channel waiting flag bit, and if the odd channel waiting flag bit is 1, then send a new packet in turn on the even channel and the odd channel; Step 113: If the odd channel waiting flag bit is 0, determine whether the even channel packet counter is equal to the odd channel packet counter minus 1, and if so, send a new packet on the even channel; if the even channel packet counter is equal to the odd channel packet A counter, the channel waiting flag position of the even channel is 1, and go to step 108;

If the even channel packet counter is greater than the odd channel packet counter or the even channel packet counter is less than the odd channel packet counter and decremented by 1, the entire ARQ process is terminated and an abnormal condition is diagnosed;

Step 114: On the receiving end, perform a CRC check on the received packet, and if it is received correctly, send an ACK signal to the transmitting end on the corresponding channel, and go to step 108; if it is not received correctly, send a NACK signal to On the transmitting side, go to step 108.

11. The method according to any one of claims 1 to 8 or 10, characterized in that it is particularly suitable for use in a TDD communication system.

12. An error control device for a high-speed wireless packet data service, comprising: a dual-channel controller, a channel transmitter, and a channel receiver; wherein: the dual-channel controller sends packet data to a channel transmitter; and channel transmission The transmitter transmits the transmitted signal to the channel receiver through the channel; the dual-channel controller processes the packet data to be transmitted according to the signal fed back by the receiving end.

13. The device according to claim 12, wherein the dual-channel controller includes at least a channel waiting flag bit; the dual-channel controller can set the waiting flag bit to identify the happy channel. Packet data transmission status of each single channel.

14. The apparatus according to claim 12, wherein the dual-channel controller includes at least a packet counter; the dual-channel controller can set the packet counter to set each of the dual channels. The packet data of the channel is packet-counted.

15. The apparatus according to claim 12, wherein the dual-channel controller comprises a channel waiting flag bit and a packet counter; wherein:

The dual channel controller may set the waiting flag bit to identify a packet data transmission status of each single channel of the dual channel; The dual channel controller may set the packet counter to count packet data of each single channel of the dual channel.

16. The apparatus according to claim 12, wherein the dual-channel controller comprises a channel waiting flag bit, a packet counter, and a retransmission counter; wherein:

The dual-channel controller may set the waiting flag bit to identify a packet data transmission status of each single channel of the dual-channel;

The dual channel controller may set the packet counter to count packet data of each single channel of the dual channel;

The dual-channel controller may set the retransmission counter to count retransmissions of packet data of each single channel of the dual channel.

17. The apparatus according to claim 12, wherein the channel controller comprises a channel waiting flag bit, a packet counter, a retransmission counter, and a channel timer.

among them:

The channel controller may set the waiting flag bit to identify the packet data transmission status of each single channel of the dual channel;

The dual-channel controller may set the retransmission counter to retransmit the packet data of each single channel of the Chinese channel;

The dual channel controller can set the channel timer to time the packet data of each single channel of the dual channel.

18. The apparatus according to claim 12, wherein the channel transmitter is composed of at least two channel transmitters.

19. The apparatus according to claim 12, wherein the channel receiver comprises at least two channel receivers.

20. The device according to claim 12, further comprising a CRC checker, and the channel receiver inputs the received signal to the CRC checker for checking.

21. The apparatus according to claim 20, wherein the CRC checker is composed of at least two CRC checkers.