WO2003065452A1 - A lead frame - Google Patents

A lead frame Download PDF

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Publication number
WO2003065452A1
WO2003065452A1 PCT/SG2002/000014 SG0200014W WO03065452A1 WO 2003065452 A1 WO2003065452 A1 WO 2003065452A1 SG 0200014 W SG0200014 W SG 0200014W WO 03065452 A1 WO03065452 A1 WO 03065452A1
Authority
WO
WIPO (PCT)
Prior art keywords
contact members
semiconductor device
lead frame
main member
encapsulating material
Prior art date
Application number
PCT/SG2002/000014
Other languages
French (fr)
Inventor
Heng Wan Hong
Tian Siang Yip
Joo Hong Tan
Choon Muah Lee
Liang Kng Ian Koh
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Priority to PCT/SG2002/000014 priority Critical patent/WO2003065452A1/en
Priority to EP02711624A priority patent/EP1470587A1/en
Publication of WO2003065452A1 publication Critical patent/WO2003065452A1/en
Priority to US10/903,495 priority patent/US7193298B2/en
Priority to US12/408,576 priority patent/USRE41510E1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the invention relates to a lead frame, and especially a lead frame for mounting a semiconductor device thereon.
  • a lead frame comprising a first portion adapted to have a semiconductor device mounted thereon and a second portion comprising a main member, a number of first contact members and a number of second contact members, the first and second contact members depending from the main member, the second portion at least partially encircling the first portion and the first contact members extending from the main member in a direction away from the first portion and the second contact members extending from the main member in a direction towards the first portion.
  • An advantage of the invention is that by having contact members which extend both towards and away from the first portion, it is possible to increase the number of contact members for a given package size without requiring a decrease in the pitch of the contact members.
  • the ends of the first and second contact members remote from the main member are substantially co-planar.
  • the first portion may also be co-planar with the remote ends of the first and second contact members.
  • the first contact members are offset along the main member from the second contact members.
  • the spacing between the first contact members adjacent the main member is greater than the width of the second contact members adjacent to the main member.
  • the spacing between the second contact members adjacent to the main member is greater than the width of the first contact members adjacent to the main member.
  • the second portion further comprises a bond member for each of the first contact members, the bond members extending from the main member in a direction towards the first portion.
  • the bond members are in line with the first contact members and preferably each of the second contact members is separated from its adjacent second contact members by a bond member.
  • a semiconductor device package comprising a substrate, a semiconductor device mounted on the substrate and a number of electrical interconnects electrically coupling electrical contacts on the semiconductor device to contact members on the substrate, the semiconductor device and the electrical interconnects being encapsulated in an electrically insulating material, and the contact members comprising a number of contact members extending from the encapsulation material and a number of second contact members located on a surface of the encapsulating material.
  • the substrate is a lead frame in accordance with the first aspect of the present invention.
  • the second contact members located on the surface of the encapsulating material are substantially co-planar with the ends of the first contact members extending from the encapsulating material.
  • the second contact members are substantially flush with the surface of the encapsulating material. However, it is possible that they may protrude from the surface.
  • the surface of the encapsulating material on which the second electrical contact members are located is the surface of the encapsulating material adjacent to the underside of the substrate, which is the side opposite to the side on which the semiconductor device is mounted.
  • the underside of the substrate is exposed on the same surface of the encapsulating material on which the second electrical contact members are exposed, and typically, the exposed underside of the substrate is substantially co-planar with the second electrical contact members.
  • Figure 1 is plan view of part of a lead frame
  • Figure 2 is an enlarged view of detail "A" of Figure 1
  • Figure 3 is a perspective view of an upside down packaged semiconductor device
  • Figure 4 is a cross-sectional view of the packaged semiconductor device
  • Figure 5 is a bottom view of the packaged semiconductor device
  • Figure 6 is a side view of the packaged semiconductor device
  • Figure 7 is a plan view of the packaged semiconductor device.
  • Figure 1 shows a part of a lead frame 1 which includes a die pad 2 and a contact pin portion 3 which surrounds the die pad 2.
  • the die pad 2 is connected to the contact pin portion 3 by supports 4.
  • the contact pin portion 3 comprises a central section 5 commonly known as a dambar which extends substantially parallel to each of the sides of the die pad 2.
  • the dambar 5 has a set of first electrical contacts 6 extending from the dambar 5 in a direction away from the die pad 2.
  • the arrangement of the first and second contact members and the bond members 8 on the dambar 5 is shown in more detail in Figure 2.
  • the bond members 8 are arranged to be in-line with the first electrical contacts 6, and the second electrical contacts 7 are offset from the first electrical contacts 6.
  • a semiconductor chip 10 is attached to the die pad 2 using a conventional die attach adhesive (see Figure 4).
  • Wire bonds 11 , 12 are then formed, which extend from contact pads (not shown) on the chip 10 to the bond members 8 and the second contact members 7, respectively.
  • An encapsulation process is then carried out to mold an electrically insulating encapsulating material 13 around the die pad 2, the chip 10, the wire bonds 11 , 12, the second contacts 7 and the bond members 8.
  • portions 9 of the dambar 5 are punched out during a trim/form process. It can be seen from Figure 2 that after the portions 9 have been punched out of the dambar 5, the first contacts 6 are still connected to the bond members 8 but are electrically isolated from the second contacts 7, and the first contacts 6, bond members 8 and second contacts 7 are all held in their respective positions by the encapsulating material 13..
  • a finished molded semiconductor device package 20 which in this case is a quad flat package (QFP), is shown in Figures 3 to 7.
  • QFP quad flat package
  • the first contacts 6 extend from the sides of the packaged device 20 in the same way as the pins on a conventional lead frame based package.
  • ends 15 of the first contacts 6 are substantially co-planar with the exposed ends of the second contacts 7 and with the underside of the die pad 2. This helps to ensure that when the packaged device 20 is connected to a circuit board, the first contacts 6, the second contacts 7 and the underside of the die pad 2 all contact the circuit board.
  • the exposed underside of the die pad 2 is an optional feature and it is possible that the lead frame and the mold for molding the encapsulating material 13 could be configured such that the underside of the die pad 2 is not exposed but is covered with encapsulating material 13. In addition, it may be desirable to perform the molding process such that the exposed ends of the second contacts 7 and (optionally) the underside of the die pad 2 protrude from the surface of the encapsulating material 13 instead of being flush with the surface of the encapsulating material 13.
  • the pitch of the first contact members 6 is defined as "A” and the pitch of the second contact members 7 is defined as "B” (see Figure 1 ).
  • Table 1 below shows typical pin counts for a package according to the invention compared with a standard QFP for different body sizes. It can be seen from Table 1 that the invention enables a QFP of a given size to have either a higher pin count for a similar pin pitch, a greater pin pitch for a similar pin count or a combination of both.
  • the invention has the advantage of permitting a higher pin count and/or a larger pin pitch for a given package size.

Abstract

A lead frame (1) has a first portion (2) adapted to have a semiconductor device (10) mounted thereon and a second portion (3) including a main member (5), a number of first contact members (6) and a number of second contact members (7). The first and second contact members (6, 7) depend from the main member (5). The second portion (3) at least partially surrounds the first portion (6). The first contact members (6) extend form the main member (5) in a direction away for the first portion (2) and the second contact members (7) extend from the main member (5) in a direction towards the first portion (2).

Description

A LEAD FRAME
The invention relates to a lead frame, and especially a lead frame for mounting a semiconductor device thereon.
Due to higher system integration, there is a trend to increase the number of input/output pins (i.e. pin count) on integrated circuit packages. At the same time, there is also a desire to reduce the package size. However, the increase in pin count places a limitation on the reduction of the package size, unless the pitch of the pins is reduced. Reducing the pitch of the pins leads to more complication during fabrication as it requires processes, such as stamping tool fabrication, dambar cut process, testing and surface mount technology to be more accurate.
Therefore, there is a conflict between increasing system integration, which results in a higher pin count, and reducing the size of the integrated circuit package.
In accordance with a first aspect of the present invention, there is provided a lead frame comprising a first portion adapted to have a semiconductor device mounted thereon and a second portion comprising a main member, a number of first contact members and a number of second contact members, the first and second contact members depending from the main member, the second portion at least partially encircling the first portion and the first contact members extending from the main member in a direction away from the first portion and the second contact members extending from the main member in a direction towards the first portion.
An advantage of the invention is that by having contact members which extend both towards and away from the first portion, it is possible to increase the number of contact members for a given package size without requiring a decrease in the pitch of the contact members.
Preferably, the ends of the first and second contact members remote from the main member are substantially co-planar.
Typically, the first portion may also be co-planar with the remote ends of the first and second contact members.
Preferably, the first contact members are offset along the main member from the second contact members.
Typically, the spacing between the first contact members adjacent the main member is greater than the width of the second contact members adjacent to the main member. Preferably, the spacing between the second contact members adjacent to the main member is greater than the width of the first contact members adjacent to the main member.
Typically, the second portion further comprises a bond member for each of the first contact members, the bond members extending from the main member in a direction towards the first portion. Typically, the bond members are in line with the first contact members and preferably each of the second contact members is separated from its adjacent second contact members by a bond member.
In accordance with a second aspect of the present invention, there is provided a semiconductor device package comprising a substrate, a semiconductor device mounted on the substrate and a number of electrical interconnects electrically coupling electrical contacts on the semiconductor device to contact members on the substrate, the semiconductor device and the electrical interconnects being encapsulated in an electrically insulating material, and the contact members comprising a number of contact members extending from the encapsulation material and a number of second contact members located on a surface of the encapsulating material.
Preferably, the substrate is a lead frame in accordance with the first aspect of the present invention. Preferably, the second contact members located on the surface of the encapsulating material are substantially co-planar with the ends of the first contact members extending from the encapsulating material.
Preferably, the second contact members are substantially flush with the surface of the encapsulating material. However, it is possible that they may protrude from the surface.
Typically, the surface of the encapsulating material on which the second electrical contact members are located is the surface of the encapsulating material adjacent to the underside of the substrate, which is the side opposite to the side on which the semiconductor device is mounted.
In one example of the invention, the underside of the substrate is exposed on the same surface of the encapsulating material on which the second electrical contact members are exposed, and typically, the exposed underside of the substrate is substantially co-planar with the second electrical contact members.
An example of a lead frame in accordance with the present invention will now be described with reference to the accompanying drawings, in which
Figure 1 is plan view of part of a lead frame; Figure 2 is an enlarged view of detail "A" of Figure 1 ; Figure 3 is a perspective view of an upside down packaged semiconductor device;
Figure 4 is a cross-sectional view of the packaged semiconductor device; Figure 5 is a bottom view of the packaged semiconductor device; Figure 6 is a side view of the packaged semiconductor device; and
Figure 7 is a plan view of the packaged semiconductor device.
Figure 1 shows a part of a lead frame 1 which includes a die pad 2 and a contact pin portion 3 which surrounds the die pad 2. The die pad 2 is connected to the contact pin portion 3 by supports 4.
The contact pin portion 3 comprises a central section 5 commonly known as a dambar which extends substantially parallel to each of the sides of the die pad 2. The dambar 5 has a set of first electrical contacts 6 extending from the dambar 5 in a direction away from the die pad 2. In addition, there are a set of second electrical contacts 7 extending from the dambar 5 in a direction towards the die pad 2. Located between each pair of adjacent second electrical contacts 7 is a bond member 8. The arrangement of the first and second contact members and the bond members 8 on the dambar 5 is shown in more detail in Figure 2. The bond members 8 are arranged to be in-line with the first electrical contacts 6, and the second electrical contacts 7 are offset from the first electrical contacts 6. In use, a semiconductor chip 10 is attached to the die pad 2 using a conventional die attach adhesive (see Figure 4). Wire bonds 11 , 12 are then formed, which extend from contact pads (not shown) on the chip 10 to the bond members 8 and the second contact members 7, respectively. An encapsulation process is then carried out to mold an electrically insulating encapsulating material 13 around the die pad 2, the chip 10, the wire bonds 11 , 12, the second contacts 7 and the bond members 8.
After the encapsulation process, portions 9 of the dambar 5 are punched out during a trim/form process. It can be seen from Figure 2 that after the portions 9 have been punched out of the dambar 5, the first contacts 6 are still connected to the bond members 8 but are electrically isolated from the second contacts 7, and the first contacts 6, bond members 8 and second contacts 7 are all held in their respective positions by the encapsulating material 13..
A finished molded semiconductor device package 20, which in this case is a quad flat package (QFP), is shown in Figures 3 to 7. The underside of the die pad 2 and the ends of the second contacts 7, which are remote from the dambar 5, are exposed through the surface of the encapsulating material 13. The first contacts 6 extend from the sides of the packaged device 20 in the same way as the pins on a conventional lead frame based package.
It will also be noted from Figures 4 and 6 that ends 15 of the first contacts 6 are substantially co-planar with the exposed ends of the second contacts 7 and with the underside of the die pad 2. This helps to ensure that when the packaged device 20 is connected to a circuit board, the first contacts 6, the second contacts 7 and the underside of the die pad 2 all contact the circuit board.
The exposed underside of the die pad 2 is an optional feature and it is possible that the lead frame and the mold for molding the encapsulating material 13 could be configured such that the underside of the die pad 2 is not exposed but is covered with encapsulating material 13. In addition, it may be desirable to perform the molding process such that the exposed ends of the second contacts 7 and (optionally) the underside of the die pad 2 protrude from the surface of the encapsulating material 13 instead of being flush with the surface of the encapsulating material 13.
In the lead frame 1 , the pitch of the first contact members 6 is defined as "A" and the pitch of the second contact members 7 is defined as "B" (see Figure 1 ). Table 1 below shows typical pin counts for a package according to the invention compared with a standard QFP for different body sizes. It can be seen from Table 1 that the invention enables a QFP of a given size to have either a higher pin count for a similar pin pitch, a greater pin pitch for a similar pin count or a combination of both.
Accordingly, the invention has the advantage of permitting a higher pin count and/or a larger pin pitch for a given package size.
Figure imgf000010_0001
Table 1

Claims

1. A lead frame comprising a first portion adapted to have a semiconductor device mounted thereon and a second portion comprising a main member, a number of first contact members and a number of second contact members, the first and second contact members depending from the main member, the second portion at least partially surrounding the first portion, wherein the first contact members extend from the main member in a direction away from the first portion and the second contact members extend from the main member in a direction towards the first portion.
2. A lead frame according to claim 1 , wherein the ends of the first and second contact members remote from the main member are substantially co- planar.
3. A lead frame according to claim 1 or claim 2, wherein the first portion is substantially co-planar with the remote ends of the second contact members.
4. A lead frame according to any of the preceding claims, wherein the first contact members are offset along the main member from the second contact members.
5. A lead frame according to any of the preceding claims, wherein the spacing between the first contact members adjacent the main member is greater than the width of the second contact members adjacent to the main member.
6. A lead frame according to any of the preceding claims, wherein the spacing between the second contact members adjacent to the main member is greater than the width of the first contact members adjacent to the main member.
7. A lead frame according to any of the preceding claims, wherein the second portion further comprises a bond member for each of the first contact members.
8. A lead frame according to claim 7, wherein the bond members extend from the main member in a direction towards the first portion.
9. A lead frame according to claim 8, wherein the bond members are in line with the first contact members.
10. A lead frame according to claim 8 or claim 9, wherein each of the second contact members is separated from its adjacent second contact members by a bond member.
11. A semiconductor device package comprising a substrate, a semiconductor device mounted on the substrate and a number of electrical interconnects electrically coupling electrical contacts on the semiconductor device to contact members on the substrate, the semiconductor device and the electrical interconnects being encapsulated in an electrically insulating material, and the contact members comprising a number of contact members extending from the encapsulation material and a number of second contact members located on a surface of the encapsulating material.
12. A semiconductor device package according to claim 11 , wherein the substrate is a lead frame according to any of claims 1 to 10.
13. A semiconductor device package according to claim 11 or claim 12, wherein the second contact members located on the surface of the encapsulating material are substantially co-planar with the ends of the first contact members extending from the encapsulating material.
14. A semiconductor device package according to any of claims 11 to 13, wherein the second contact members are substantially flush with the surface of the encapsulating material.
15. A semiconductor device package according to any of claims 11 to 14, wherein the surface of the encapsulating material on which the second electrical contact members are located is the surface of the encapsulating material adjacent to the underside of the substrate, which is the side opposite to the side on which the semiconductor device is mounted.
16. A semiconductor device package according to any of claim 15, wherein the underside of the substrate is exposed on the same surface of the encapsulating material on which the second electrical contact members are exposed.
17. A semiconductor device package according to claim 16 wherein the exposed underside of the substrate is substantially co-planar with the second electrical contact members.
PCT/SG2002/000014 2002-02-01 2002-02-01 A lead frame WO2003065452A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/SG2002/000014 WO2003065452A1 (en) 2002-02-01 2002-02-01 A lead frame
EP02711624A EP1470587A1 (en) 2002-02-01 2002-02-01 A lead frame
US10/903,495 US7193298B2 (en) 2002-02-01 2004-07-30 Lead frame
US12/408,576 USRE41510E1 (en) 2002-02-01 2009-03-20 Lead frame

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