WO2003063242A1 - Space-saving packaging of electronic circuits - Google Patents
Space-saving packaging of electronic circuits Download PDFInfo
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- WO2003063242A1 WO2003063242A1 PCT/US2003/001277 US0301277W WO03063242A1 WO 2003063242 A1 WO2003063242 A1 WO 2003063242A1 US 0301277 W US0301277 W US 0301277W WO 03063242 A1 WO03063242 A1 WO 03063242A1
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- integrated circuit
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/14181—On opposite sides of the body
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0652—Bump or bump-like direct electrical connections from substrate to substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/53—Means to assemble or disassemble
- Y10T29/53104—Roller or ball bearing
Definitions
- the present invention is generally directed to packaging techniques for electronic circuitry and in particular vertical stacking and interconnection techniques for a plurality of integrated circuits.
- 09/677,384; 10/205,862; and 10/280,841 describe implantable medical devices and enclosed circuitry that are sized so that they are suitable for injection in a patient's body, i.e., being contained within an elongated housing having an axial dimension of less than 60 mm and a lateral dimension of less than 6 mm. With such limited outer dimensions (and accordingly even smaller inner dimensions), the space available for needed circuitry is limited.
- stacking sometimes referred to as 3D or vertical integration
- a frame see, e.g., U.S. Patent No. 6,404,043
- interconnect paths at the edge of uniformly sized chips and/or carriers see, e.g., U.S. Patent No. 4,956,694
- additional vertical interconnect members and/or wire bond interconnects see, e.g., U.S. Patent No. 6,133,626 to extend the assembly beyond two oppositely oriented flip chips, i.e., with one chip facing "up” and the other chip facing “down” so that their BGAs can mate to each other. It is believed that each of these techniques limit the use of valuable package volume.
- the present invention is directed to a packaging technique for stacking a plurality of integrated circuit substrates which provides interconnection paths through the substrates to simplify electrical connections between the integrated circuits while facilitating minimization of the volume and customization of the three dimensional package size to conform to the available internal space within a housing, e.g., one used in an implantable device where package volume is at a premium.
- an internal cavity can be created by the stacked formation that is suitable for mounting of a surface mount device, e.g., a crystal or the like.
- a preferred embodiment of a chip stack, for forming a circuit of a plurality of integrated circuits formed on discrete substrates is comprised of: (1) a first substrate having first and second faces and a first integrated circuit having one or more interconnection pads formed proximate to the first face of the first integrated circuit, wherein the substrate additionally comprises a plurality of interconnection pathways selected from the set of vias that pass directly through from the first face to the second face of the first substrate, vias that pass in a step-wise manner from the first face to the second face of the first substrate, and vias that pass from one or more of the first integrated circuit interconnection pads to pads at the second surface of the first substrate; (2) a second substrate having first and second faces and a second integrated circuit having one or more interconnection pads formed proximate to the first face of the second integrated circuit, wherein the substrate additionally comprises a plurality of interconnection pathways selected from the set of vias that pass directly through from the first face to the second face of the second substrate, vias that pass in a step-wise manner from the first face
- the chip stack may include a plurality of differently-sized substrates stacked in an order to form a stacked shape having a non- rectangular cross section, e.g., essentially round, diamond, triangular, hexagonal, etc., and this 3D configuration facilitates optimal use of available space within a housing, e.g., an elongated housing having an axial dimension of less than 60 mm and a lateral dimension of less than 6 mm.
- a housing e.g., an elongated housing having an axial dimension of less than 60 mm and a lateral dimension of less than 6 mm.
- the chip stack may be configured to form a cavity within to contain and protect a surface mount device, e.g., a crystal or the like.
- FIG. 1 is a perspective view of one chip stack portion, i.e., layer, of a chip stack comprised of a substrate having an integrated circuit formed integral to a first, e.g., upper, face and interconnection pathways from the integrated circuit to a second, e.g., lower, face of the substrate.
- FIG. 2A is a cross sectional view of chip stack portion that is flipped, i.e., having its integrated circuit face and associated ball grid array interconnects primarily on its lower face. Additionally, this figure shows lapping to facilitate the formation of vias through the substrate and the thinning of the stack portion.
- FIG. 2B is a cross sectional view of the chip stack portion of FIG. 1 taken along the line 2B-2B.
- FIG. 2C is another chip stack portion.
- FIG. 2D is a substrate that is used solely for providing interconnection pathways, i.e., without an integral integrated circuit, between its top and bottom surfaces to thereby provide additional interconnects between chip stack portions.
- FIG. 2E is another chip stack portion and an optional motherboard with wire bond interconnects therebetween.
- FIG. 3 is the cross sectional view of the exemplary chip stack of
- FIGS. 2A-2C after mating.
- FIG. 4 is the exemplary chip stack of FIGS. 2A-2C with encapsulation of the chip portions (with the exception of interconnect pads that are used for external connections).
- FIG. 5 is a perspective view of the first two chip portions, i.e., layers, of a chip stack where an optional cavity is formed within that is suitable for containing a surface mount device, e.g., a piezoelectric device, a capacitor, etc.
- FIG. 6 is a cross-sectional view of a further extended chip stack of FIG. 5, taken along the line 6-6, wherein a cavity is optionally formed within, suitable for encasing a surface mount device. Additionally, this configuration demonstrates the capability of embodiments of the present invention to form the three dimensional stack with a non-rectangular cross section.
- the present invention is directed to a packaging technique for stacking a plurality of integrated circuit substrates which provides interconnection paths through the substrates to simplify electrical connections between the integrated circuits while facilitating minimization of the volume and customization of the three dimensional package size to conform to the available internal space within a housing, e.g., one used in an implantable device where package volume is at a premium.
- an internal cavity can be created by the stacked formation that is suitable for mounting of a surface mount device, e.g., a crystal or the like.
- a surface mount device e.g., a crystal or the like.
- CMOS complementary metal-oxide-semiconductor
- the yield can be optimized by partitioning the circuitry into smaller, more easily fabricated portions.
- different technologies and portions of the circuitry may generate more noise, e.g., output drivers, and others may be more sensitive, e.g., communication circuitry, to generated noise. Accordingly, partitioning the circuitry into different chips that are then stacked, allows the quantity, source and location of noise sources to be controlled.
- a first chip stack portion 10 is comprised of a semiconductor substrate 12 having an integrated circuit 14 formed on a first face 16 opposite a second face 18.
- a semiconductor substrate 12 having an integrated circuit 14 formed on a first face 16 opposite a second face 18.
- vias may be formed from the first face 16 to the second face 18 of the semiconductor substrate 12, preferably such that the vias connect from interconnection pads 20 on the face of the integrated circuit 14 to the second face 18 of the semiconductor substrate 12 or to other portions of the first face 16 of the semiconductor substrate 12.
- each chip stack portion i.e., its Z direction vertical dimension
- its horizontal widths i.e., its X and Y dimensions.
- the drawings presented are purposely exaggerated to allow its Z direction details, e.g., the integrated circuit and vias, to be shown more clearly.
- FIG. 2B shows a cross sectional view of the chip stack portion of FIG. 1 taken along the line 2B-2B.
- bumps 22a e.g., formed from gold, solder, aluminum, etc.
- a via 24 may be formed from interconnection pad 20 in a stair case, e.g., serpentine, manner from the interconnection pad 20 on the first face 16 to the second face 18.
- bump 22b may be formed at the second face end of the via 24.
- vias 26 and 28 may be formed in the semiconductor substrate 12 to allow interconnection pathways from the first face 16 to the second face of the semiconductor substrate 12.
- Via 26 is an essentially straight through feedthrough while via 28 uses a stair case, e.g., serpentine, pathway through the semiconductor substrate 12.
- a stack of integrated circuits 14 located on discrete semiconductor substrates 12 can be formed with electrical interconnection paths between the integrated circuits 14 and external pathways when a plurality of such chip stack portions 10 are coupled together using solder, thermal compressive bonding, ultrasonic bonding, conductive epoxy, and the like to establish the electrical and mechanical interconnections of the chip stack.
- the vias are preferably formed by masking the surface of the substrate 12, i.e., a silicon wafer, except where the vias are to be positioned and these positions are etched to a depth of at least 10 microns plus an additional depth to allow for an insulation layer.
- the sidewalls of the etched wells are preferably not vertical, but instead are formed having a sufficient angle such that subsequent conductor material deposition will fill them completely.
- the surface 16 including the etched wells are coated with an appropriate insulating layer such as silicon dioxide.
- a conducting material such as metal is deposited on the substrate 12 with sufficient depth to fill the wells completely.
- the substrate 12 is thinned, i.e., lapped, by diamond grinding from the back side to a thickness of 10 microns, exposing the bottom of the wells as bonding pads for solder or gold bumping.
- FIG. 2A is essentially a flip chip, i.e., the same configuration of FIGS. 1 and 2B with a 180 degree reversal.
- the chip stack portion of FIG. 2A is intentionally made thinner by the aforementioned lapping process performed to the non active side, i.e., the side opposite the integrated circuit portion to reduce the chips stack portion's, i.e., layer's, thickness toward the dotted line shown.
- FIG. 2C is similar to that previously described with less via permutations and FIG. 2E is similar to what has been described in reference to FIG. 2B with the exception that an optional motherboard 30 and wire bonds 32 are used to supplement the interconnection scheme.
- an interconnect chip stack portion 34 (see FIG 2D) may be used which is similar to that previously described in reference to FIG. 2B with the primary difference being that an integrated circuit is not formed on the semiconductor substrate 12.
- FIG. 3 shows a chip stack 36 of the present invention comprised of a plurality of chip stack portions 10, i.e., in this example, just those shown in FIGS.2A-2C, after they have been electrically and mechanically bonded together to form a combination of integrated circuits that thus form a system or subsystem.
- This chip stack 36 may then be mounted within a housing (not shown).
- the chip stack 36 may be encapsulated (see FIG 4), e.g., with alumina or the like, to enable the chip stack 36 to be directly implanted within a patient's body since it is within encapsulation layer 38 (see, for example, U.S. Patent No. 6,259,937 which describes such an environment and methods of depositing an encapsulation layer, e.g., by ion beam deposition (IBD)).
- IBD ion beam deposition
- FIG. 5 is a perspective view of the first two layers of a chip stack 40 where differently-sized chip stack portions 42, 44 are purposely used in order to form a chip stack 40 which conforms with the available volume in a housing, e.g., the elongate housing described relative to U.S. Patent Nos. 6,164,284; 6,185,452; 6,208,894; 6,315,721; and 6,472,991. (Note that the vias and integrated circuits are purposely not shown in these FIGS. 5 and 6 for simplification purposes.) Accordingly, as shown in FIG.
- FIG. 6 which is a cross-sectional view of a further extended chip stack of FIG.5, taken along the line 6-6 and adding chip stack portions 46, 48
- selecting additional chip stack portion sizes allows one to form a desired three dimensional shape. For example, if all of the semiconductor substrates were equally sized, a rectangular cross sectional shape would result. However, as demonstrated in FIG. 6, a non-rectangular cross section can be achieved, e.g., circular, semicircular, triangular, diamond, hexagonal, etc., or whatever shape is required to conform to the available internal volume (note the optional dotted portions shown to transform the shape from a triangle to a diamond).
- 6,164,284; 6,185,452; 6,208,894; 6,315,721 ; and 6,472,991 is typically round, square, diamond, triangular, hexagonal, and other shapes are also possible and embodiments of the present invention thus allow optimal use of the internal package space.
- a cavity 50 may be formed within that is suitable for containing a surface mount device 52, e.g., a piezoelectric device (including crystals and the like as described in copending, commonly-assigned, concurrently-filed U.S. Patent Application entitled “Piezoelectric Devices Mounted On An Integrated Circuit Chip” and referenced by Attorney Docket No. A296-USA which is incorporated herein by reference in its entirety), a capacitor, etc., by design and selective placement of chip stack portions, i.e., layers, that form the cavity 50 within.
- this configuration enables the surface mount device 52, e.g., a crystal to be protected from external contact by the surrounding semiconductor chip stack portions.
- chip stack portions 54, 56 may be utilized to completely surround the cavity 50 and may, with assistance of an encapsulation layer, e.g., alumina, be used to hermetically encase such surface mount devices 52 within the chip stack 40.
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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EP03705789A EP1472730A4 (en) | 2002-01-16 | 2003-01-15 | Space-saving packaging of electronic circuits |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US34963302P | 2002-01-16 | 2002-01-16 | |
US60/349,633 | 2002-01-16 |
Publications (1)
Publication Number | Publication Date |
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WO2003063242A1 true WO2003063242A1 (en) | 2003-07-31 |
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PCT/US2003/001277 WO2003063242A1 (en) | 2002-01-16 | 2003-01-15 | Space-saving packaging of electronic circuits |
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US (1) | US7071546B2 (en) |
EP (1) | EP1472730A4 (en) |
WO (1) | WO2003063242A1 (en) |
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US8399273B2 (en) | 2008-08-18 | 2013-03-19 | Tsmc Solid State Lighting Ltd. | Light-emitting diode with current-spreading region |
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Cited By (3)
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US8264853B2 (en) | 2005-11-30 | 2012-09-11 | 3D Plus | 3D electronic module |
Also Published As
Publication number | Publication date |
---|---|
EP1472730A4 (en) | 2010-04-14 |
EP1472730A1 (en) | 2004-11-03 |
US20030192171A1 (en) | 2003-10-16 |
US7071546B2 (en) | 2006-07-04 |
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