WO2003060984A1 - Surface mounted package with die bottom spaced from support board - Google Patents
Surface mounted package with die bottom spaced from support board Download PDFInfo
- Publication number
- WO2003060984A1 WO2003060984A1 PCT/US2002/041477 US0241477W WO03060984A1 WO 2003060984 A1 WO2003060984 A1 WO 2003060984A1 US 0241477 W US0241477 W US 0241477W WO 03060984 A1 WO03060984 A1 WO 03060984A1
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- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor device
- mosfet
- die
- semiconductor package
- clip
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
- H01L23/047—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
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- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
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Definitions
- the present invention relates to a semiconductor package and more particularly to a semiconductor package for housing a power semiconductor die having a structure which reduces temperature cycling failures.
- thermal cycling causes f equent and repeated stress which in layered structures leads to cracks due to, for example, fatigue. Temperature cycling, therefore, is a material factor in causing failure in layered structures.
- temperature cycling causes failures in die-underfill bonding, underfill-substrate bonding, solder bump attachment and passivation layers among other areas. This reduces the reliability of the package. It is, therefore, desirable to provide a means to reduce failure caused by temperature cycling.
- FIGs. 1 and 2 show that semiconductor package 5 includes MOSFET 10 inside cup-shaped can 12 which functions as a drain clip.
- Can 12 is preferably made from a copper alloy and is silver-plated.
- Can 12 has internal dimensions that are greater than those of MOSFET 10; thus MOSFET 10 is readily received in the interior of can 12.
- the drain contact of MOSFET 10 is connected to the bottom of can 12 by a layer of silver-loaded conductive epoxy 14.
- a ring of low stress high adhesion epoxy 16 is applied around the edges of MOSFET 10 to seal and add extra structural strength to the package.
- Source contact 18 and gate contact 20 of MOSFET 10 which are disposed on a surface of MOSFET 10 opposing its drain contact, are exposed as shown in Fig. 1.
- Can 12 includes two rows of projections 22 disposed on two of its opposing edges. Projections are provided to make electrical contact with respective lands on a circuit board (not shown), such as an Insulated Metal Substrate or an ordinary circuit board, thereby electrically connecting the drain of MOSFET 10 to its place within a circuit.
- source contact 18 of MOSFET 10 is flush with the contact surfaces of projections 22 of can 12. Therefore, source contact 18 and gate contact 20 of MOSFET 10 will be flush with the surface of the circuit board when package 5 is mounted thereon.
- a semiconductor device package comprising a semiconductor device die having a first surface substantially parallel to a second surface, and the first surface and second surface each have a solderable planar metal electrode.
- a metal clip is disclosed that has a flat web portion comprising a first and second surface, wherein the second surface is electrically connected with the first surface of the semiconductor device die.
- the die is disposed in the interior of the clip such that the die is inwardly recessed in the interior of the clip and the second surface of the die is not flush (or co-planar) with the at least one solderable planar metal post-shaped electrode.
- the interior of the solderable planar metal post-shaped electrode is removed to a parallel plane above the plane of the second surface of the die.
- the at least one solderable planar metal post-shaped electrode is mountable to a metallized pattern on a support surface, such as a circuit board and the second surface of the die is spaced from the metallized pattern on the support surface.
- the semiconductor package according to the present invention reduces the number of failures due to thermal cycling and, thus, adds to the reliability of the package. Furthermore, the semiconductor package according to the present invention includes a vertical conduction MOS-gated die such as a MOSFET having a first major surface on which a major electrode and a control electrode are disposed and another major surface opposing the first major surface on which another major electrode is disposed.
- a vertical conduction MOS-gated die such as a MOSFET having a first major surface on which a major electrode and a control electrode are disposed and another major surface opposing the first major surface on which another major electrode is disposed.
- the first major electrode in a vertical conduction MOSFET used in a package according to the present invention is the source electrode; while, its second major electrode is the drain electrode.
- the control electrode in a vertical conduction MOSFET is conventionally referred to as the gate electrode.
- the die is described herein as a power MOSFET, it will be apparent that the die may be any desired die, including any MOS-gated device (e.g., an IGBT), a thyristor or diode, or the like.
- MOS-gated device e.g., an IGBT
- thyristor or diode e.g., a thyristor or diode, or the like.
- FIG. 1 shows a top view of a semiconductor package according to the prior art
- Fig. 2 shows a cross-section of semiconductor package of Fig. 1 looking in the direction of line 1-1;
- FIG. 3 shows a cross-section of a semiconductor package of Figs. 1 and
- semiconductor package 24 includes MOSFET 10 that is set back deeper into the interior of can 12 than in prior art packages as shown in Fig.l and Fig. 2. Therefore, source contact 18 and gate contact 20 (not shown in Fig. 3) of MOSFET 10 are no longer flush with projections 22 of can 12. This arrangement is illustrated in Fig. 3 by the gap between broken lines A, A'.
- a semiconductor package according to the present invention includes a metal can which receives in its interior space a MOSFET or other similar semiconductor type device die. The MOSFET so received is inwardly recessed in the can and oriented such that the MOSFET's drain electrode is facing the bottom of the can and is electrically connected to the same by a layer of conductive epoxy or a solder or the like.
- the edges of the MOSFET so placed are spaced from the walls of the can.
- the space between the edges of the MOSFET and the walls of the can is filled with an insulating layer.
- the can preferably includes two rows of posts on its opposing edges.
- the posts are connectable to appropriate conduction pads on a substrate, such as a circuit board, to connect the drain of the MOSFET to its appropriate place within a circuit.
- the posts can be a full or partial portion of the rim of the can.
- the source and gate electrodes of the MOSFET face the substrate when the can is mounted thereon. It has been found that if the MOSFET is positioned within the can so that the source and gate electrodes of the MOSFET become sub-flush with the surface of the substrate, failure due to thermal cycling is improved.
- the bottom surface of the MOSFET is sub-flush below the plane of the substrate by 0.001 - 0.005 inches to reduce temperature cycling failures.
- the sub-flush volume is filled by the conductive attachment material such as solder, epoxy, and the like.
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP02797504.4A EP1466357B1 (en) | 2001-12-21 | 2002-12-23 | Surface mounted package with die bottom spaced from support board |
JP2003560978A JP4535730B2 (en) | 2001-12-21 | 2002-12-23 | Semiconductor package |
AU2002361873A AU2002361873A1 (en) | 2001-12-21 | 2002-12-23 | Surface mounted package with die bottom spaced from support board |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US34233301P | 2001-12-21 | 2001-12-21 | |
US60/342,333 | 2001-12-21 | ||
US10/327,270 | 2002-12-20 | ||
US10/327,270 US6930397B2 (en) | 2001-03-28 | 2002-12-20 | Surface mounted package with die bottom spaced from support board |
Publications (1)
Publication Number | Publication Date |
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WO2003060984A1 true WO2003060984A1 (en) | 2003-07-24 |
Family
ID=26985785
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2002/041477 WO2003060984A1 (en) | 2001-12-21 | 2002-12-23 | Surface mounted package with die bottom spaced from support board |
Country Status (6)
Country | Link |
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US (2) | US6930397B2 (en) |
EP (1) | EP1466357B1 (en) |
JP (2) | JP4535730B2 (en) |
CN (1) | CN100559557C (en) |
AU (1) | AU2002361873A1 (en) |
WO (1) | WO2003060984A1 (en) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6930397B2 (en) * | 2001-03-28 | 2005-08-16 | International Rectifier Corporation | Surface mounted package with die bottom spaced from support board |
JP3879688B2 (en) * | 2003-03-26 | 2007-02-14 | 株式会社デンソー | Semiconductor device |
US7786558B2 (en) * | 2005-10-20 | 2010-08-31 | Infineon Technologies Ag | Semiconductor component and methods to produce a semiconductor component |
US7723830B2 (en) * | 2006-01-06 | 2010-05-25 | International Rectifier Corporation | Substrate and method for mounting silicon device |
US20070215997A1 (en) * | 2006-03-17 | 2007-09-20 | Martin Standing | Chip-scale package |
US7663212B2 (en) * | 2006-03-21 | 2010-02-16 | Infineon Technologies Ag | Electronic component having exposed surfaces |
US7768075B2 (en) | 2006-04-06 | 2010-08-03 | Fairchild Semiconductor Corporation | Semiconductor die packages using thin dies and metal substrates |
US7541681B2 (en) * | 2006-05-04 | 2009-06-02 | Infineon Technologies Ag | Interconnection structure, electronic component and method of manufacturing the same |
US7910992B2 (en) * | 2008-07-15 | 2011-03-22 | Maxim Integrated Products, Inc. | Vertical MOSFET with through-body via for gate |
JP5343574B2 (en) * | 2009-01-20 | 2013-11-13 | トヨタ自動車株式会社 | Brazing method of heat sink |
US8222718B2 (en) * | 2009-02-05 | 2012-07-17 | Fairchild Semiconductor Corporation | Semiconductor die package and method for making the same |
US8563360B2 (en) * | 2009-06-08 | 2013-10-22 | Alpha And Omega Semiconductor, Inc. | Power semiconductor device package and fabrication method |
US20110075392A1 (en) | 2009-09-29 | 2011-03-31 | Astec International Limited | Assemblies and Methods for Directly Connecting Integrated Circuits to Electrically Conductive Sheets |
US7939370B1 (en) * | 2009-10-29 | 2011-05-10 | Alpha And Omega Semiconductor Incorporated | Power semiconductor package |
US8906747B2 (en) * | 2012-05-23 | 2014-12-09 | Freescale Semiconductor, Inc. | Cavity-type semiconductor package and method of packaging same |
CN103629567B (en) * | 2012-08-22 | 2016-04-13 | 华夏光股份有限公司 | Lighting device |
US9536800B2 (en) | 2013-12-07 | 2017-01-03 | Fairchild Semiconductor Corporation | Packaged semiconductor devices and methods of manufacturing |
US9214419B2 (en) * | 2014-02-28 | 2015-12-15 | Alpha And Omega Semiconductor Incorporated | Power semiconductor device and preparation method thereof |
US9117809B1 (en) * | 2014-03-09 | 2015-08-25 | Alpha & Omega Semiconductor (Cayman), Ltd. | Ultra-thin semiconductor device and preparation method thereof |
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- 2002-12-23 CN CNB028252802A patent/CN100559557C/en not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
---|---|
US7285866B2 (en) | 2007-10-23 |
CN100559557C (en) | 2009-11-11 |
US6930397B2 (en) | 2005-08-16 |
EP1466357B1 (en) | 2017-12-13 |
US20050224960A1 (en) | 2005-10-13 |
US20030132531A1 (en) | 2003-07-17 |
JP2007295014A (en) | 2007-11-08 |
JP4535730B2 (en) | 2010-09-01 |
EP1466357A4 (en) | 2007-08-15 |
CN1605121A (en) | 2005-04-06 |
JP2005515635A (en) | 2005-05-26 |
AU2002361873A1 (en) | 2003-07-30 |
EP1466357A1 (en) | 2004-10-13 |
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