WO2003060603A1

WO2003060603A1 - Thin film transistor substrate for liquid crystal display(lcd) and method of manufacturing the same

Info

Publication number: WO2003060603A1
Application number: PCT/KR2003/000093
Authority: WO
Inventors: Hee-Sang Suh; Yeon-Heok You
Original assignee: Iljin Diamond Co., Ltd
Priority date: 2002-01-17
Filing date: 2003-01-16
Publication date: 2003-07-24
Also published as: KR20030062592A; WO2003060603A8; TW588408B; TW200303036A; AU2003235642A1

Abstract

Disclosed is a thin film transistor substrate having a capacitor structure capable of securing sufficient storage capacitance according to increase in data potential. The thin film transistor substrate includes a black matrix arranged between adjacent unit pixels on transparent insulating substrate, a first oxide film formed on the black matrix, a heavily doped polysilicon layer pattern formed on the first oxide film. The black matrix, the first oxide and the heavily doped polysilicon layer pattern form a capacitor. An active polysilicon layer pattern is formed on the first and second oxide films. A third oxide film is formed on an exposed surface of the active polysilicon layer pattern. A gate poly pattern is formed on the second oxide film including the first contact hole and on a selected region of the third oxide film, and is electrically connected with the underlying heavily doped polysilicon layer pattern.

Description

THIN FILM TRANSISTOR SUBSTRATE FOR LIQUID CRYSTAL DISPLAY (LCD) AND METHOD OF MANUFACTURING THE SAME

TECHNICAL FIELD The present invention relates to a thin film transistor substrate for a liquid crystal display and a manufacturing method the same, and more particularly, to a thin film transistor substrate for a liquid crystal display and a method of manufacturing the same in which storage capacitance is increased by forming a heavily doped polycrystalline silicon (or polysilicon) containing high concentration impurities on the black matrix layer formed on a thin film transistor substrate.

BACKGROUND ART

In an information-oriented society these days, the role of an electronic display is getting more important. All kinds of electronic displays are widely used in various industrial fields. As techniques of the electronic display field are continuously developed, various electronic displays having new functions are provided corresponding to diverse requirements of the information-oriented society.

Generally, electronic display is an apparatus for visually transmitting information to a person. That is, electronic display can be defined as an electronic apparatus, which converts an electrical information signal output from various electronic equipments into a visually recognizable optical information signal. Also, it may be defined as an electronic apparatus serving as a bridge for connecting the person and the electronic equipments . These electronic displays are classified into an emissive display in which the optical information signal is displayed by a light-emitting method, and a non-emissive display in which the signal is displayed by an optical modulation method such as light-reflecting, dispersing and interference phenomena, etc. As the emissive display called an active display, for example, there are a CRT (Cathode Ray Tube), a PDP (Plasma display panel), an LED (Light emitting diode) and an ELD (Eelectroluminescesnt Display), etc. And as the non-emissive display called a passive display, there are an LCD (Liquid Crystal Display) and an EPID (Eelectrophoretic Image Display), etc.

The CRT has been used in an image display such as a television and a monitor, etc., over the longest period of time. The CRT has the highest market share in an aspect of displaying quality and economical efficiency, but also has many disadvantages such as heavy weight, large volume and high power consumption.

Meanwhile, as various kinds of electronic devices are small-sized and lighter in weight along with the solidification and lower voltage and lower power driving of the electronic devices due to rapid advancement of semiconductor technologies, there is requested a flat panel type display having slimmer and lighter property as well as lower driving voltage and lower power consumption characteristic according to the new environment. Among variously developed flat panel type displays, the LCD is much slimmer and lighter than any other displays and it has the lower driving voltage and the lower power consumption. Also, it has the displaying quality similar to that in the CRT. Therefore, the LCD is widely used in various electronic devices. Further, since the LCD can be manufactured with ease, its application is gradually wider.

The liquid crystal display is comprised of two substrates in which electrodes are formed, and liquid crystal interposed therebetween. The liquid crystal display is a device for performing a displaying operation by applying a voltage to the electrodes, and it realigns molecules of the liquid crystal so as to control an amount of light passing through the liquid crystal.

In these LCDs, a general structure that is being widely used includes two substrates each of which has an electrode formed thereon and a thin film transistor (TFT) for switching a voltage applied to the electrode. Generally, the electrode is formed on either one of the two substrates .

As the resolution of these LCD panels increases with the advancement of technologies, data potential applied through data line of thin film transistor substrate increases too.

However, the conventional capacitor structure fails to sufficiently store increased data potential.

DISCLOSURE OF THE INVENTION

Accordingly, the present invention is directed to a thin film transistor substrate for a liquid crystal display and fabrication method thereof that substantially obviates one or more problems due to limitations and disadvantages of the related art.

It is an object of the invention to provide a thin film transistor substrate with a capacitor structure capable of sufficiently storing an increased data potential.

It is another object of the invention to enable doped polysilicon layer pattern used as the lower electrode of a storage capacitor and gate poly pattern to be formed by using the same mask.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings .

To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, there is provided a thin film transistor substrate for a liquid crystal display. The thin film transistor substrate includes: a black matrix arranged between adjacent unit pixels on a transparent insulating substrate, for preventing light leakage between the adjacent unit pixels; a first oxide film formed on a resultant substrate including the black matrix; a heavily doped polysilicon layer pattern formed on the first oxide film; a second oxide film formed on an exposed surface of the heavily doped polysilicon layer pattern, and having a first contact hole exposing a predetermined portion of the heavily doped polysilicon layer pattern; an active polysilicon layer pattern formed on active regions of the first oxide film and the second oxide film; a third oxide film formed on an exposed surface of the active polysilicon layer pattern; a gate poly pattern formed on the second oxide film including the first contact hole and on a selected region of the third oxide film so as to correspond with the heavily doped polysilicon layer pattern, and electrically connected with the underlying heavily doped polysilicon layer pattern; a fourth oxide film formed on a resultant substrate including the gate poly pattern and having a second contact hole formed in the fourth oxide film and the underlying third oxide film so as to expose the source region of the active polysilicon layer pattern; a data line formed on a selected portion of the fourth oxide film including the second contact hole; a planarizing film formed on the fourth oxide film including the data line; and a pixel electrode formed on the planarizing film. Preferably, the gate poly pattern comprises a gate electrode pattern of the thin film transistor, and an upper storage electrode pattern of a storage capacitor.

Alternatively, the gate electrode pattern is electrically connected with the doped polysilicon layer pattern disposed below the channel region.

According to another aspect of the invention, there is provided a method for fabricating a thin film transistor substrate for a liquid crystal display. The method includes the steps of: forming a black matrix between adjacent unit pixels on a transparent insulating substrate, for preventing light leakage between the adjacent unit pixels; forming a first oxide film on the black matrix; forming a heavily doped polysilicon layer pattern on the first oxide film; forming a second oxide film on an exposed surface of the heavily doped polysilicon layer pattern, the second oxide film having a first contact hole exposing a predetermined portion of the polysilicon layer pattern; forming an active polysilicon layer pattern on active regions of the first oxide film and the second oxide film; forming a third oxide film on an exposed surface of the active polysilicon layer pattern; forming a gate poly pattern on a predetermined portion of the third oxide film; forming a fourth oxide film on a resultant substrate including the gate poly pattern; forming a second contact hole exposing a predetermined portion of the active polysilicon layer pattern at a predetermined portion of the fourth oxide film and the underlying third oxide film; forming a data line on a selected portion of the fourth oxide film including the second contact hole; forming a planarizing film on the fourth oxide film including the data line; and forming a pixel electrode on the planarizing film. According to the invention, a high concentration impurities-doped polysilicon layer pattern is formed between the black matrix pattern and the active polysilicon pattern, and an oxide film is respectively interposed between the black matrix layer and the doped polysilicon layer pattern and between the doped polysilicon layer pattern and the active polysilicon layer pattern to form stack type capacitors, thereby sufficiently storing increased data potential.

In addition, the doped polysilicon layer pattern used as the lower electrode of a storage capacitor and the gate poly pattern are formed by using the same mask, a further mask essentially requested in forming a further capacitor is unnecessary.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

FIG. 1 is a sectional view of a thin film transistor substrate for a liquid crystal display according to an embodiment of the present invention; and

FIG. 2 is a sectional view of several unit pixel regions taken along a direction perpendicular to the data line.

BEST MODE FOR CARRYING OUT THE INVENTION

Now, exemplary embodiments of the present invention will be described in detail with reference to the annexed drawings . FIG. 1 is a sectional view for illustrating a manufacturing method of a thin film transistor substrate for a liquid crystal display and taken along the data line according to an embodiment of the present invention, and FIG. 2 is a sectional view of several unit pixel regions taken along a direction perpendicular to the data line.

Referring to FIGs. 1 and 2, a black matrix pattern 102 is formed on a transparent insulating substrate 100, such as quartz (Si0₂) or glass by a photolithography process such that the lower black matrix patterns 102 cross with each other on boundary lines of unit pixel regions (1^st mask).

Alternatively, the black matrix pattern 102 is not separated every unit pixel but is successively formed.

On the entire surface of the substrate 100 including the black matrix pattern 102 is formed a high temperature oxide (HTO) as a first oxide film 104. After that, a pair of heavily doped polysilicon layer patterns 106, 106' are formed on the first oxide film. In other words, an active layer pattern 106 is formed on the first oxide film 104. In other words, heavily doped polysilicon layer patterns 106, 106' are formed by a photolithography process such that they partially overlap with the black matrix pattern 102 of a unit pixel region (2nd mask) .

The heavily doped polysilicon layer patterns 106, 106' are separately formed every unit pixel region. Next, a second oxide film 108, 108' of silicon oxide is formed on a resultant substrate including the heavily doped polysilicon layer pattern 106, 106'.

After that, a patterning process for ion implantation of a portion to be used as storage capacitor in the heavily doped polysilicon layer patterns is performed (3^rd mask).

Afterwards, a first contact hole (HI) partially exposing the heavily doped polysilicon layer pattern 106' is formed (4^th mask).

Thereafter, an active layer 110 including source region, drain region and channel region is formed to cover the entire surface of the second oxide film pattern 108 and a predetermined portion of the second oxide film pattern 108'. In other words, the active layer 110 is formed not to cove the first contact hole (Hi) (5^th mask).

As the active layer 110, single crystalline silicon, preferably polycrystalline silicon is used.

Alternatively, the active layer 110 may have a lightly doped drain (LDD) structure.

Afterwards, a third oxide film 112 is formed on the active layer 110 at a predetermined thickness. The third oxide film 112 is formed by a wet oxidation or a dry oxidation of the active layer 110. The third oxide film 112 is formed to still expose the first contact hole.

Subsequently, a polysilicon film is deposited on the entire surface of a resultant substrate including the third oxide film 112. This polysilicon film is patterned by using the second mask that was used to form the doped polysilicon layer patterns 106, 106'. As a result, gate patterns 114, 114' are formed at corresponding portions to the doped polysilicon layer patterns 106, 106'. The gate patterns 114, 114' include a gate electrode 114 overlapping with the channel region of the active layer 110, and an upper storage electrode pattern 114' functioning as the upper electrode of the storage capacitor. The upper storage electrode pattern 114' is electrically contacted with the doped polysilicon layer pattern 106' through the first contact hole (HI) . Next, five valence or third valence impurity ions are implanted into the source region and the drain region by an ion implantation process or a doping process using the gate patterns 114, 114' as the ion implantation mask (6^th, 7^th masks) .

Subsequently, a fourth oxide film 116 is formed on a resultant substrate including the gate patterns 114, 114'. Afterwards, selected portions of the fourth oxide film 116 and the underlying third oxide film are etched by a photolithography process to form a second contact hole (H2) so that the source region of the active layer 110 is exposed (8^th mask) .

Next, metal film for data line is deposited at a predetermined thickness on the entire surface of the fourth oxide film 116 including the second contact hole (H2). This metal film for data line is patterned by a photolithography process, so that data line 118 is formed (9^th mask).

After that, a planarizing film (or passivation film)

120 is formed on the fourth oxide film 116 including the data line 118. The planarizing film 120 is patterned by a photolithography process to form a third contact hole (not shown) exposing the drain electrode (not shown) (10^th mask).

In the meanwhile, unit pixel regions are defined by the cross of the gate lines and the data lines 118. In order to form pixel electrodes on the defined unit pixel regions, a transparent conductive film such as indium tin oxide (ITO) film or indium zinc oxide (IZO) film is deposited at a predetermined thickness.

The deposited transparent conductive film is then patterned to form a pixel electrode 122 contacting with the drain electrode through the third contact hole.

In the thin film transistor substrate formed by the foregoing processes, since the heavily doped polysilicon patterns 106, 106', the active layer 110 and the pixel electrode 122 have a data potential which is inputted through the data line, and the black matrix pattern 102 and the storage gate pattern 114' have a common potential, it is possible to use all the insulating layers between the respective layers as dielectric layer. As a result, a sufficient storage capacitance capable of storing data potential can be secured.

INDUSTRIAL APPLICABILITY

As described previously, according to the invention, heavily doped polysilicon layer pattern is formed below the active layer of a thin film transistor substrate, and a black matrix pattern is formed below the doped polysilicon layer pattern with an oxide film interposed therebetween, and the formed three layers are used as a capacitor, thereby enabling to secure a sufficient storage capacitance capable of coping with the increase of the data potential.

In addition, since the heavily doped polysilicon layer pattern used as the lower electrode of the storage capacitor and the gate pattern are formed by the same mask, a further mask essentially requested in forming a further capacitor is unnecessary. Further, the doped polysilicon layer pattern is electrically connected with the gate pattern through contact hole. To this end, although the gate line is open-failed due to cracks or the like in the gate line, a flowing gate line enables redundancy, thereby reducing occurrence of failed pixels.

While the present invention has been described and illustrated herein with reference to the preferred embodiments thereof, it will be apparent to those skilled in the art that various modifications and variations can be made therein without departing from the spirit and scope of the invention. Thus, it is intended that the present invention covers the modifications and variations of this invention that come within the scope of the appended claims and their equivalents.

Claims

1. A thin film transistor substrate for a liquid crystal display, comprising: a black matrix arranged between adjacent unit pixels on a transparent insulating substrate, for preventing light leakage between the adjacent unit pixels; a first oxide film formed on a resultant substrate including the black matrix; a heavily doped polysilicon layer pattern formed on the first oxide film; a second oxide film formed on an exposed surface of the heavily doped polysilicon layer pattern, and having a first contact hole exposing a predetermined portion of the heavily doped polysilicon layer pattern; an active polysilicon layer pattern formed on active regions of the first oxide film and the second oxide film; a third oxide film formed on an exposed surface of the active polysilicon layer pattern; a gate poly pattern formed on the second oxide film including the first contact hole and on a selected region of the third oxide film so as to correspond with the heavily doped polysilicon layer pattern, and electrically connected with the underlying heavily doped polysilicon layer pattern; a fourth oxide film formed on a resultant substrate including the gate poly pattern and having a second contact hole formed in the fourth oxide film and the underlying third oxide film so as to expose the source region of the active polysilicon layer pattern; a data line formed on a selected portion of the fourth oxide film including the second contact hole; a planarizing film formed on the fourth oxide film including the data line; and a pixel electrode formed on the planarizing film.

2. The thin film transistor substrate of claim 1, wherein the gate poly pattern comprises a gate electrode pattern of the thin film transistor, and an upper storage electrode pattern of a storage capacitor.

3. The thin film transistor substrate of claim 2, wherein the upper storage electrode pattern is electrically connected with the underlying doped polysilicon layer pattern through the first contact hole.

4. The thin film transistor substrate of claim 2, wherein the gate electrode pattern is electrically connected with the doped polysilicon layer pattern disposed below the channel region.

5. A method for fabricating a thin film transistor substrate for a liquid crystal display, the method comprising the steps of: forming a black matrix between adjacent unit pixels on a transparent insulating substrate, for preventing light leakage between the adjacent unit pixels; forming a first oxide film on the black matrix; forming a heavily doped polysilicon layer pattern on the first oxide film; forming a second oxide film on an exposed surface of the heavily doped polysilicon layer pattern, the second oxide film having a first contact hole exposing a predetermined portion of the polysilicon layer pattern; forming an active polysilicon layer pattern on active regions of the first oxide film and the second oxide film; forming a third oxide film on an exposed surface of the active polysilicon layer pattern; forming a gate poly pattern on a predetermined portion of the third oxide film; forming a fourth oxide film on a resultant substrate including the gate poly pattern; forming a second contact hole exposing a predetermined portion of the active polysilicon layer pattern at a predetermined portion of the fourth oxide film and the underlying third oxide film; forming a data line on a selected portion of the fourth oxide film including the second contact hole; forming a planarizing film on the fourth oxide film including the data line; and forming a pixel electrode on the planarizing film.

6. The method of claim 5, wherein the doped polysilicon layer pattern and the gate poly pattern are formed by using the same mask.

7. The method of claim 5, wherein the active polysilicon layer pattern comprises source region, drain region and channel region, and the source region and the drain region are formed by implanting five valence or three valence impurity ions with the gate electrode of the gate poly pattern as an ion implantation mask.