WO2003052939A2 - Sigma delta a/d converter with firdac converter - Google Patents

Sigma delta a/d converter with firdac converter Download PDF

Info

Publication number
WO2003052939A2
WO2003052939A2 PCT/IB2002/004781 IB0204781W WO03052939A2 WO 2003052939 A2 WO2003052939 A2 WO 2003052939A2 IB 0204781 W IB0204781 W IB 0204781W WO 03052939 A2 WO03052939 A2 WO 03052939A2
Authority
WO
WIPO (PCT)
Prior art keywords
signal
converter
bit digital
bit
generating
Prior art date
Application number
PCT/IB2002/004781
Other languages
French (fr)
Other versions
WO2003052939A3 (en
Inventor
Bas M. Putter
Original Assignee
Koninklijke Philips Electronics N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Priority to AU2002348901A priority Critical patent/AU2002348901A1/en
Publication of WO2003052939A2 publication Critical patent/WO2003052939A2/en
Publication of WO2003052939A3 publication Critical patent/WO2003052939A3/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
    • H03M3/464—Details of the digital/analogue conversion in the feedback path
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
    • H03M3/344—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M3/424—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one

Definitions

  • the invention relates to a Sigma Delta A/D converter for generating an N-bit digital output signal on the basis of an analog input signal, comprising a control loop which comprises an N-bit A/D converter for generating the N-bit digital output signal.
  • Such a Sigma Delta A/D converter is known in actual practice and comprises a D/A converter in the feedback loop of the control loop for generating a feedback signal.
  • the linearity of the Sigma Delta A/D converter is mainly determined by the D/A converter. This offers the opportunity to simplify the overall design of the Sigma Delta A/D converter.
  • the number of bits of the D/A converter in the feedback loop is often greater than one.
  • Designers often choose the exact number of bits of the D/A converter in dependence of, for example, an expected time jitter of a system clock, an expected signal-to- noise-ratio for the Sigma Delta A/D converter, and an expected signal bandwidth.
  • the time jitter of the clock results in a signal distortion and noise in the signal of the D/A converter.
  • the more bits a D/A converter comprises the smaller the signal distortion, due to, for example, time jitter, will be.
  • providing a D/A converter with more bits will be at the expense of the linearity of the D/A converter.
  • One of the reasons of the relatively poor linearity of the known Sigma Delta A/D converter is a poor resolution of the D/A converter. Therefore, designers are faced with the awkward problem of finding an acceptable compromise between linearity and resolution of the feedback signal.
  • the Sigma Delta A/D converter comprises a FIRDAC (Finite Impulse Response D/A converter) in a feedback loop of the control loop, wherein the FIRDAC comprises a multiple of 1 -bit D/A converters which are connected in a delay line forming a FJR-f ⁇ lter, and wherein the FIRDAC generates a first analog version of the N-bit digital output signal.
  • the linearity of this Sigma Delta A/D converter according to the invention is mainly determined by the linearity of the FIRDAC in the feedback loop.
  • the FIRDAC consists of the multiple of 1-bit D/A converters which are connected in a delay line.
  • a basic property of a 1-bit D/A converter is that it possesses, at least in principle, a perfect linearity. Since the FIRDAC comprises 1-bit D/A converters and only performs summation, scaling and delay operations with the signals of these 1-bit D/A converters, the FIRDAC has a perfect or an almost perfect linear transfer function. This linearity is not influenced by mismatch conditions.
  • the Sigma Delta A/D converter according to the invention is less susceptible to timing jitter.
  • the feedback signal from the FIRDAC is a multi-level (multi-level here means more than two signal levels) signal.
  • multi-level means more than two signal levels
  • the level steps of the FIRDAC feedback signal, between subsequent time slots of the system clock can be much smaller than commensurable level steps of a single 1-bit D/A converter. Therefore, the FIRDAC feedback signal is less sensitive to timing jitter whereas the feedback signal of a 1-bit D/A converter is very sensitive to timing jitter.
  • An embodiment of the Sigma Delta A/D converter according to the invention is characterized in that the Sigma Delta A/D converter also comprises a first combiner for generating a first combined signal by combining the analog input signal with the first analog version of the N-bit digital output signal, and a first loop filter for generating a filtered first combined signal by filtering the first combined signal, wherein the N-bit A/D converter generates the N-bit digital output signal on the basis of the filtered first combined signal.
  • the transfer function of the Sigma Delta A D converter can be optimized by tuning the loop filter.
  • An embodiment of the Sigma Delta A D converter according to the invention also comprises a pre-processing unit for generating a shaped 1-bit digital signal on the basis of the N-bit digital output signal, wherein the frequency of the shaped 1-bit digital signal is higher than the frequency of the N-bit digital output signal, and wherein the FIRDAC generates the first analog version of the N-bit digital output signal on the basis of the shaped 1-bit digital signal.
  • the pre-processing unit can be a digital noise shaper, comprising:
  • a comparator for generating the shaped 1-bit digital signal by comparing the second combined signal with a pre-determined threshold value
  • a third combiner for generating a third combined signal by combining the second combined signal with the shaped 1-bit digital signal, and - a second loop filter for generating the filtered digital residue signal on the basis of the third combined signal.
  • the digital output signal of the Sigma Delta A/D converter of this embodiment is a high-frequency 1-bit output signal. This output signal can be converted, by decimation, in to any N-bit (N>1) output signal with a lower frequency.
  • Figure 1 is a schematic overview of a first embodiment of the Sigma Delta A/D converter according to the invention
  • Figure 2 is a schematic overview of a FIRDAC of the Sigma Delta A/D converter in Figure 1 ;
  • FIG 3 is a schematic overview of a pre-processing unit of the Sigma Delta A/D converter in Figure 1
  • Figure 4 is a schematic overview of a second embodiment of the Sigma Delta
  • FIG. 1 shows a Sigma Delta A/D converter (2) for generating an N-bit digital output signal (4) on the basis of an analog input signal (6).
  • the Sigma Delta A/D converter (2) comprises a first combiner (8) for generating a first combined signal (10) by combining the analog input signal (6) with the first analog version (12) of the N-bit digital output signal (4).
  • the Sigma Delta A D converter (2) also comprises a first loop filter (14) for generating a filtered first combined signal (16) by filtering the first combined signal (10), and an N-bit A/D converter (18) for generating the N-bit digital output signal (4) on the basis of the filtered first combined signal (16).
  • the Sigma Delta A/D (2) comprises a pre-processing unit (20) and a FIRDAC (22).
  • the FIRDAC (22) can generate the first analog version ( 12) of the N-bit digital output signal (4) on the basis of a shaped 1-bit digital signal (24).
  • the shaped 1-bit digital signal (24) is generated by the pre-processing unit (20) on the basis of the N-bit digital output signal (4).
  • the frequency of the shaped 1-bit digital signal is higher than the frequency of the N-bit digital output signal.
  • the first combiner (8), the first loop filter (14), the N-bit A/D converter (18), the pre-processing unit (20) and the FIRDAC (22) form a control loop of the Sigma Delta A/D converter (2), wherein the FIRDAC generates the first analog version (12) which is a feedback signal of the control loop.
  • FIG. 2 shows an embodiment of the FIRDAC (22).
  • the FIRDAC (22) comprises three 1-bit D/A converters which are connected in series in a delay line.
  • the delays in the delay line are controlled by a clock signal (29) of a system clock which is not shown in the drawings.
  • the flip-flop (26.1) generates a delayed control signal (30.1) for controlling the switch (27.1) (switch-on or switch-off like a 1-bit signal) on the basis of the shaped 1-bit digital signal (24).
  • the signal (30.1) is fed with a delay to the flip-flop (26.2) which generates a control signal (30.2) for controlling the switch (27.2).
  • the flip-flop (26.3) generates the delayed control signal (30.3) for controlling the switch (27.3) on the basis of the control signal (30.2).
  • This analog signal (12) is less sensitive to timing jitter in the clock signal (29) than, for example, a two-level analog signal, since the spacing between the subsequent signal levels of the signal (12) can be reduced. Therefore, the signal steps between the time slots determined by the system clock can likewise be smaller.
  • the respective currents (32. i) of the respective current sources (28.i) are summed (dependent on the states of the corresponding switches (27.i)) in order to generate a first analog version (12) of the N-bit digital output signal (4).
  • FIG 3 shows an embodiment of the pre-processing unit (20).
  • the preprocessing unit (20) generates a digital 1-bit signal (24) on the basis of an N-bit signal (4).
  • the frequency of the digital N-bit signal (4) is lower than the frequency of the digital 1-bit signal (24).
  • the pre-processing unit (20) is a digital noise shaper, comprising a second combiner (34), a comparator (36), a third combiner (38) and a second loop filter (40).
  • the second combiner (34) of the pre-processing unit (20) is provided for generating a second combined signal (42) by combining the N-bit digital output signal (4) with a filtered digital residue signal (44).
  • the second combined signal (42) can be compared with a pre-determined threshold value by the comparator (36) in order to generate the shaped 1-bit digital signal (24).
  • the third combiner (38) is used for generating a third combined signal (46) by combining the second combined signal (42) with the shaped 1-bit digital signal (24).
  • the second loop filter (40) can generate the filtered digital residue signal (44) on the basis of the third combined signal (46).
  • the order of the digital noise shaper is determined by the second loop filter (40).
  • Figure 4 is a schematic representation of a second embodiment of the Sigma
  • This second embodiment does not comprise an N-bit (N>1) A D converter; instead a 1-bit A/D converter (52) is used.
  • a simple and effective configuration of the Sigma Delta converter (2) is thus obtained.
  • This Sigma Delta converter (2) can generate a 1-bit digital output signal (4) on the basis of an analog input signal (6).
  • the 1-bit digital output signal (4) can be transformed in an N-bit digital output signal by means of a decimation operation. In that case the frequency of the N-bit digital output signal is lower than the frequency of the 1-bit digital output signal.
  • the Sigma Delta converter (2) in Figure 4 comprises a first combiner (8), a first loop filter (14), a fourth combiner (48), a second loop filter (50), a 1-bit A/D converter (52), a 1-bit D/A converter (54) and a FIRDAC (22).
  • the 1-bit D/A (54) can be omitted by using one of the 1-bit D/A converters of the FIRDAC (22) and by connecting this 1-bit D/A converter of the FIRDAC (22) to the fourth combiner (48).
  • the operation of the first combiner (8), the first loop filter (14) and the FIRDAC (22) of the second embodiment of Figure 4 is similar to the operation of corresponding parts of the first embodiment of Figure 1.
  • the fourth combiner (48) can be used for generating a fourth combined signal (56) by combining the filtered first combined signal (16) with a second analog version (58) of the 1-bit digital output signal (4).
  • the second loop filter (50) can generate a filtered fourth combined signal (60) by filtering the fourth combined signal (56).
  • the filtered fourth combined signal (60) is fed to the 1-bit A/D converter (52) for generating the 1-bit digital output signal (4).
  • the second 1-bit D/A converter (54) can generate the second analog version (58) of the 1-bit digital output signal (4) on the basis of the 1-bit digital output signal (4).

Abstract

The invention relates to a Sigma Delta A/D converter (2) for generating an N-bit digital output signal (4) on the basis of an analog input signal (6), comprising a control loop which comprises an N-bit A/D converter (2) for generating the N-bit digital output signal, wherein the Sigma Delta A/D converter (2) comprises a FIRDAC (22) in a feedback loop of the control loop, wherein the FIRDAC (22) comprises a multiple of 1-bit D/A converters which are connected in a delay line forming a FIR-filter, and wherein the FIRDAC (22) generates a first analog version (12) of the N-bit digital output signal (4).

Description

Sigma Delta A/D converter with FIRDAC converter
The invention relates to a Sigma Delta A/D converter for generating an N-bit digital output signal on the basis of an analog input signal, comprising a control loop which comprises an N-bit A/D converter for generating the N-bit digital output signal.
Such a Sigma Delta A/D converter is known in actual practice and comprises a D/A converter in the feedback loop of the control loop for generating a feedback signal. In this configuration the linearity of the Sigma Delta A/D converter is mainly determined by the D/A converter. This offers the opportunity to simplify the overall design of the Sigma Delta A/D converter.
A specific example of this principle can be found in United States Patent 5,818,374. In this patent a noise-limiting, switched-current delta-sigma modulator which can be used in an oversampling A/D converter is discussed.
The number of bits of the D/A converter in the feedback loop is often greater than one. Designers often choose the exact number of bits of the D/A converter in dependence of, for example, an expected time jitter of a system clock, an expected signal-to- noise-ratio for the Sigma Delta A/D converter, and an expected signal bandwidth. The time jitter of the clock results in a signal distortion and noise in the signal of the D/A converter. Generally speaking, the more bits a D/A converter comprises, the smaller the signal distortion, due to, for example, time jitter, will be. On the other hand, providing a D/A converter with more bits will be at the expense of the linearity of the D/A converter. One of the reasons of the relatively poor linearity of the known Sigma Delta A/D converter is a poor resolution of the D/A converter. Therefore, designers are faced with the awkward problem of finding an acceptable compromise between linearity and resolution of the feedback signal.
It is an object of the invention to provide a Sigma Delta A/D which has both a high resolution and a low distortion of the feedback signal. This object is achieved by means of the Sigma Delta A/D converter according to the invention which is characterized in that the Sigma Delta A/D converter comprises a FIRDAC (Finite Impulse Response D/A converter) in a feedback loop of the control loop, wherein the FIRDAC comprises a multiple of 1 -bit D/A converters which are connected in a delay line forming a FJR-fϊlter, and wherein the FIRDAC generates a first analog version of the N-bit digital output signal. The linearity of this Sigma Delta A/D converter according to the invention is mainly determined by the linearity of the FIRDAC in the feedback loop. The FIRDAC consists of the multiple of 1-bit D/A converters which are connected in a delay line. A basic property of a 1-bit D/A converter is that it possesses, at least in principle, a perfect linearity. Since the FIRDAC comprises 1-bit D/A converters and only performs summation, scaling and delay operations with the signals of these 1-bit D/A converters, the FIRDAC has a perfect or an almost perfect linear transfer function. This linearity is not influenced by mismatch conditions.
Furthermore, the Sigma Delta A/D converter according to the invention is less susceptible to timing jitter. This is a consequence of the fact that the feedback signal from the FIRDAC is a multi-level (multi-level here means more than two signal levels) signal. This means that the level steps of the FIRDAC feedback signal, between subsequent time slots of the system clock, can be much smaller than commensurable level steps of a single 1-bit D/A converter. Therefore, the FIRDAC feedback signal is less sensitive to timing jitter whereas the feedback signal of a 1-bit D/A converter is very sensitive to timing jitter.
An embodiment of the Sigma Delta A/D converter according to the invention is characterized in that the Sigma Delta A/D converter also comprises a first combiner for generating a first combined signal by combining the analog input signal with the first analog version of the N-bit digital output signal, and a first loop filter for generating a filtered first combined signal by filtering the first combined signal, wherein the N-bit A/D converter generates the N-bit digital output signal on the basis of the filtered first combined signal. The transfer function of the Sigma Delta A D converter can be optimized by tuning the loop filter.
An embodiment of the Sigma Delta A D converter according to the invention also comprises a pre-processing unit for generating a shaped 1-bit digital signal on the basis of the N-bit digital output signal, wherein the frequency of the shaped 1-bit digital signal is higher than the frequency of the N-bit digital output signal, and wherein the FIRDAC generates the first analog version of the N-bit digital output signal on the basis of the shaped 1-bit digital signal. The pre-processing unit can be a digital noise shaper, comprising:
- a second combiner for generating a second combined signal by combining the N-bit digital output signal with a filtered digital residue signal;
- a comparator for generating the shaped 1-bit digital signal by comparing the second combined signal with a pre-determined threshold value;
- a third combiner for generating a third combined signal by combining the second combined signal with the shaped 1-bit digital signal, and - a second loop filter for generating the filtered digital residue signal on the basis of the third combined signal.
An advanced embodiment of the Sigma Delta A/D converter according to the invention is characterized in that N=l and that the Sigma Delta converter also comprises: - a fourth combiner for generating a fourth combined signal by combining the filtered first combined signal with a second analog version of the 1-bit digital output signal;
- a second loop filter for generating a filtered fourth combined signal by filtering the fourth combined signal;
- a 1-bit A/D converter for generating the 1-bit digital output signal on the basis of the filtered fourth combined signal, and
- at least one second 1-bit D/A converter for generating the second analog version of the 1-bit digital output signal on the basis of the 1-bit digital output signal. An advantage of this embodiment is that the pre-processing unit is integrated with the control loop of the Sigma Delta A/D converter. Therefore, this Sigma Delta converter does not need an N-bit (N>1) A/D converter. As a result of this configuration, the Sigma Delta A/D converter can be realized with a very compact construction. The digital output signal of the Sigma Delta A/D converter of this embodiment is a high-frequency 1-bit output signal. This output signal can be converted, by decimation, in to any N-bit (N>1) output signal with a lower frequency.
The accompanying drawings show given ways of implementing the present invention for illustrative purposes. Therein:
Figure 1 is a schematic overview of a first embodiment of the Sigma Delta A/D converter according to the invention;
Figure 2 is a schematic overview of a FIRDAC of the Sigma Delta A/D converter in Figure 1 ;
Figure 3 is a schematic overview of a pre-processing unit of the Sigma Delta A/D converter in Figure 1, and Figure 4 is a schematic overview of a second embodiment of the Sigma Delta
A/D converter according to the invention. Figure 1 shows a Sigma Delta A/D converter (2) for generating an N-bit digital output signal (4) on the basis of an analog input signal (6). The Sigma Delta A/D converter (2) comprises a first combiner (8) for generating a first combined signal (10) by combining the analog input signal (6) with the first analog version (12) of the N-bit digital output signal (4). The Sigma Delta A D converter (2) also comprises a first loop filter (14) for generating a filtered first combined signal (16) by filtering the first combined signal (10), and an N-bit A/D converter (18) for generating the N-bit digital output signal (4) on the basis of the filtered first combined signal (16). Furthermore, the Sigma Delta A/D (2) comprises a pre-processing unit (20) and a FIRDAC (22). The FIRDAC (22) can generate the first analog version ( 12) of the N-bit digital output signal (4) on the basis of a shaped 1-bit digital signal (24). The shaped 1-bit digital signal (24) is generated by the pre-processing unit (20) on the basis of the N-bit digital output signal (4). The frequency of the shaped 1-bit digital signal is higher than the frequency of the N-bit digital output signal. The first combiner (8), the first loop filter (14), the N-bit A/D converter (18), the pre-processing unit (20) and the FIRDAC (22) form a control loop of the Sigma Delta A/D converter (2), wherein the FIRDAC generates the first analog version (12) which is a feedback signal of the control loop.
Figure 2 shows an embodiment of the FIRDAC (22). The FIRDAC (22) comprises three 1-bit D/A converters which are connected in series in a delay line. The FIRDAC (22) comprises respective flip-flops (26. i) which are connected to respective switches (27.i) for controlling respective current sources (28. i) (i=l,2,3). The flip-flops (26.i) (i= 1,2,3) are connected in a delay line forming a FIR-filter. The delays in the delay line are controlled by a clock signal (29) of a system clock which is not shown in the drawings. The flip-flop (26.1) generates a delayed control signal (30.1) for controlling the switch (27.1) (switch-on or switch-off like a 1-bit signal) on the basis of the shaped 1-bit digital signal (24). Next, the signal (30.1) is fed with a delay to the flip-flop (26.2) which generates a control signal (30.2) for controlling the switch (27.2). Analogously, the flip-flop (26.3) generates the delayed control signal (30.3) for controlling the switch (27.3) on the basis of the control signal (30.2). The strengths of the respective currents of the respective current sources (28. i) (i=l,2,3) are preferably different, so that the FIRDAC converter (22) can generate an analog signal (12) with up to 8 different levels. This analog signal (12) is less sensitive to timing jitter in the clock signal (29) than, for example, a two-level analog signal, since the spacing between the subsequent signal levels of the signal (12) can be reduced. Therefore, the signal steps between the time slots determined by the system clock can likewise be smaller.
Finally, the respective currents (32. i) of the respective current sources (28.i) (i=l,2,3) are summed (dependent on the states of the corresponding switches (27.i)) in order to generate a first analog version (12) of the N-bit digital output signal (4). It is, an important property of the FIRDAC (22) that it has a linearity of a very high quality. This is achieved by choosing a series of 1-bit D/A converters (operating as a FIR-filter). A 1-bit D/A converter has a perfect linearity and the operations carried out in the FIRDAC (22) preserve the linearity of the FIRDAC (the operations only being delays and summations of currents of the current sources (28.i); (i=l, 2,3).
Figure 3 shows an embodiment of the pre-processing unit (20). The preprocessing unit (20) generates a digital 1-bit signal (24) on the basis of an N-bit signal (4). The frequency of the digital N-bit signal (4) is lower than the frequency of the digital 1-bit signal (24). In this embodiment the pre-processing unit (20) is a digital noise shaper, comprising a second combiner (34), a comparator (36), a third combiner (38) and a second loop filter (40). The second combiner (34) of the pre-processing unit (20) is provided for generating a second combined signal (42) by combining the N-bit digital output signal (4) with a filtered digital residue signal (44). The second combined signal (42) can be compared with a pre-determined threshold value by the comparator (36) in order to generate the shaped 1-bit digital signal (24). The third combiner (38) is used for generating a third combined signal (46) by combining the second combined signal (42) with the shaped 1-bit digital signal (24). Finally, the second loop filter (40) can generate the filtered digital residue signal (44) on the basis of the third combined signal (46). The order of the digital noise shaper is determined by the second loop filter (40). Figure 4 is a schematic representation of a second embodiment of the Sigma
Delta converter (2 ) according to the invention. This second embodiment does not comprise an N-bit (N>1) A D converter; instead a 1-bit A/D converter (52) is used. A simple and effective configuration of the Sigma Delta converter (2) is thus obtained. This Sigma Delta converter (2) can generate a 1-bit digital output signal (4) on the basis of an analog input signal (6). The 1-bit digital output signal (4) can be transformed in an N-bit digital output signal by means of a decimation operation. In that case the frequency of the N-bit digital output signal is lower than the frequency of the 1-bit digital output signal.
The Sigma Delta converter (2) in Figure 4 comprises a first combiner (8), a first loop filter (14), a fourth combiner (48), a second loop filter (50), a 1-bit A/D converter (52), a 1-bit D/A converter (54) and a FIRDAC (22). In principle the 1-bit D/A (54) can be omitted by using one of the 1-bit D/A converters of the FIRDAC (22) and by connecting this 1-bit D/A converter of the FIRDAC (22) to the fourth combiner (48).
The operation of the first combiner (8), the first loop filter (14) and the FIRDAC (22) of the second embodiment of Figure 4 is similar to the operation of corresponding parts of the first embodiment of Figure 1. The fourth combiner (48) can be used for generating a fourth combined signal (56) by combining the filtered first combined signal (16) with a second analog version (58) of the 1-bit digital output signal (4). The second loop filter (50) can generate a filtered fourth combined signal (60) by filtering the fourth combined signal (56). Next the filtered fourth combined signal (60) is fed to the 1-bit A/D converter (52) for generating the 1-bit digital output signal (4). The second 1-bit D/A converter (54) can generate the second analog version (58) of the 1-bit digital output signal (4) on the basis of the 1-bit digital output signal (4).
The invention has been described on the basis of a few embodiments. However, it should be noted that the invention can be implemented in ways other than those specifically illustrated and described, that is, without departing from its spirit or scope.

Claims

CLAIMS:
1. A Sigma Delta A/D converter (2) for generating an N-bit digital output signal (4) on the basis of an analog input signal (6), comprising a control loop which comprises an N-bit A/D converter for generating the N-bit digital output signal, characterized in that the Sigma Delta A/D converter (2) comprises a FIRDAC (22) in a feedback loop of the control loop, wherein the FIRDAC (22) comprises a multiple of 1-bit D/A converters which are connected in a delay line forming a FIR-filter, and wherein the FIRDAC (22) generates a first analog version (12) of the N-bit digital output signal (4).
2. A Sigma Delta A D converter according to claim 1, characterized in that the Sigma Delta A/D converter also comprises a first combiner (8) for generating a first combined signal (10) by combining the analog input signal (6) with the first analog version (12) of the N-bit digital output signal, and a first loop filter (14) for generating a filtered first combined signal (16) by filtering the first combined signal (10), wherein the N-bit A/D converter (18) generates the N-bit digital output signal (4) on the basis of the filtered first combined signal (16).
3. A Sigma Delta A/D converter according to one of the preceding claims, characterized in that the Sigma Delta converter (2) also comprises a pre-processing unit (20) for generating a shaped 1-bit digital signal (24) on the basis of the N-bit digital output signal (4), wherein the frequency of the shaped 1-bit digital signal (24) is higher than the frequency of the N-bit digital output signal (4), and wherein the FIRDAC (22) generates the first analog version (12) of the N-bit digital output signal on the basis of the shaped 1-bit digital signal (24).
4. A Sigma Delta converter according to claim 3, characterized in that the preprocessing unit (20) is a digital noise shaper, comprising:
- a second combiner (34) for generating a second combined signal (42) by combining the N-bit digital output signal (4) with a filtered digital residue signal (44); - a comparator (36) for generating the shaped 1-bit digital signal (24) by comparing the second combined signal with a pre-determined threshold value;
- a third combiner (38) for generating a third combined signal (46) by combining the second combined signal (42) with the shaped 1-bit digital signal (24), and - a second loop filter (40) for generating the filtered digital residue signal (44) on the basis of the third combined signal (46).
5. A Sigma Delta converter according to claim 2, characterized in that N=l and that the Sigma Delta converter (2) also comprises: - a fourth combiner (48) for generating a fourth combined signal (56) by combining the filtered first combined signal (16') with a second analog version (58) of the 1- bit digital output signal;
- a second loop filter (50) for generating a filtered fourth combined signal (60) by filtering the fourth combined signal (56); - a 1-bit A/D converter (52) for generating the 1-bit digital output signal (4) on the basis of the filtered fourth combined signal (60), and
- at least one second 1-bit D/A converter (54) for generating the second analog version (58) of the 1-bit digital output signal (4) on the basis of the 1-bit digital output signal (4).
PCT/IB2002/004781 2001-12-18 2002-11-13 Sigma delta a/d converter with firdac converter WO2003052939A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002348901A AU2002348901A1 (en) 2001-12-18 2002-11-13 Sigma delta a/d converter with firdac converter

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP01204950.8 2001-12-18
EP01204950 2001-12-18

Publications (2)

Publication Number Publication Date
WO2003052939A2 true WO2003052939A2 (en) 2003-06-26
WO2003052939A3 WO2003052939A3 (en) 2004-01-22

Family

ID=8181457

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2002/004781 WO2003052939A2 (en) 2001-12-18 2002-11-13 Sigma delta a/d converter with firdac converter

Country Status (2)

Country Link
AU (1) AU2002348901A1 (en)
WO (1) WO2003052939A2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005043764A1 (en) * 2003-10-22 2005-05-12 Northrop Grumman Corporation Delta-sigma analog-to-digital converter
US7414557B2 (en) 2006-12-15 2008-08-19 Telefonaktiebolaget Lm Ericsson (Publ) Method and apparatus for feedback signal generation in sigma-delta analog-to-digital converters
US7852249B2 (en) 2009-02-27 2010-12-14 Freescale Semiconductor, Inc. Sigma-delta modulator with digitally filtered delay compensation
US7880654B2 (en) 2009-02-27 2011-02-01 Freescale Semiconductor, Inc. Continuous-time sigma-delta modulator with multiple feedback paths having independent delays

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0369630A2 (en) * 1988-11-15 1990-05-23 Sony Corporation Signal processing apparatus
EP0399738A2 (en) * 1989-05-26 1990-11-28 Gec-Marconi Limited Analogue to digital converter
EP0543618A2 (en) * 1991-11-20 1993-05-26 Gec-Marconi Limited Analogue-to-digital converter
US5323157A (en) * 1993-01-15 1994-06-21 Motorola, Inc. Sigma-delta digital-to-analog converter with reduced noise
EP0617516A1 (en) * 1993-03-22 1994-09-28 Motorola, Inc. Sigma-delta modulator with improved tone rejection and method therefor
US5777512A (en) * 1996-06-20 1998-07-07 Tripath Technology, Inc. Method and apparatus for oversampled, noise-shaping, mixed-signal processing
US6147634A (en) * 1998-12-15 2000-11-14 Sigmatel, Inc. Method and apparatus for digital to analog conversion with reduced noise

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0369630A2 (en) * 1988-11-15 1990-05-23 Sony Corporation Signal processing apparatus
EP0399738A2 (en) * 1989-05-26 1990-11-28 Gec-Marconi Limited Analogue to digital converter
EP0543618A2 (en) * 1991-11-20 1993-05-26 Gec-Marconi Limited Analogue-to-digital converter
US5323157A (en) * 1993-01-15 1994-06-21 Motorola, Inc. Sigma-delta digital-to-analog converter with reduced noise
EP0617516A1 (en) * 1993-03-22 1994-09-28 Motorola, Inc. Sigma-delta modulator with improved tone rejection and method therefor
US5777512A (en) * 1996-06-20 1998-07-07 Tripath Technology, Inc. Method and apparatus for oversampled, noise-shaping, mixed-signal processing
US6147634A (en) * 1998-12-15 2000-11-14 Sigmatel, Inc. Method and apparatus for digital to analog conversion with reduced noise

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
COLODRO F ET AL: "New class of multibit sigma-delta modulators using multirate architecture" ELECTRONICS LETTERS, IEE STEVENAGE, GB, vol. 36, no. 9, 27 April 2000 (2000-04-27), pages 783-784, XP006015164 ISSN: 0013-5194 *
HARRISON, J.; WESTE, N.: "A multi-bit sigma-delta ADC with an FIR DAC loop filter" INTERNET ARTICLE, [Online] XP002254943 Marsfield. Australia Retrieved from the Internet: <URL:elec.mq.edu.au/research/microelec/sig madelta> [retrieved on 2003-09-30] *
HAUSER M W: "PRINCIPLES OF OVERSAMPLING A/D CONVERSION" JOURNAL OF THE AUDIO ENGINEERING SOCIETY, AUDIO ENGINEERING SOCIETY. NEW YORK, US, vol. 39, no. 1/2, January 1991 (1991-01), pages 3-26, XP000202803 ISSN: 0004-7554 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005043764A1 (en) * 2003-10-22 2005-05-12 Northrop Grumman Corporation Delta-sigma analog-to-digital converter
US7414557B2 (en) 2006-12-15 2008-08-19 Telefonaktiebolaget Lm Ericsson (Publ) Method and apparatus for feedback signal generation in sigma-delta analog-to-digital converters
US7852249B2 (en) 2009-02-27 2010-12-14 Freescale Semiconductor, Inc. Sigma-delta modulator with digitally filtered delay compensation
US7880654B2 (en) 2009-02-27 2011-02-01 Freescale Semiconductor, Inc. Continuous-time sigma-delta modulator with multiple feedback paths having independent delays

Also Published As

Publication number Publication date
AU2002348901A1 (en) 2003-06-30
AU2002348901A8 (en) 2003-06-30
WO2003052939A3 (en) 2004-01-22

Similar Documents

Publication Publication Date Title
US7205917B2 (en) Pulse width modulator quantisation circuit
CA2562254C (en) A method and system for analog to digital conversion using digital pulse width modulation (pwm)
CN1327618C (en) Multi-level quantizer with current mode. DEM switch matrices and separate DEM decision logic for multibit sigma delta modulator
US7248193B2 (en) Delta-sigma modulator and its application to switching amplification circuit
US7557744B2 (en) PWM driver and class D amplifier using same
US5075679A (en) Analog/digital converter configuration with sigma-delta modulators
EP2149196A1 (en) Multibit digital amplifier for radio-frequency transmission
US7200187B2 (en) Modulator for digital amplifier
US9166615B2 (en) System and method for cascaded PWM digital-to-analog converter with hybrid DAC interface
EP0865158A2 (en) Sampling frequency conversion apparatus and fractional frequency dividing apparatus for sampling frequency conversion
US20160065177A1 (en) Devices and methods for converting digital signals
US5682162A (en) Oversampling digital-to-analog converter with auto-muting feature
US20080143567A1 (en) Analog digital converter (adc) having improved stability and signal to noise ratio (snr)
US20110267211A1 (en) Analog-digital converter and operating method thereof
US6741197B1 (en) Digital-to-analog converter (DAC) output stage
WO2005096502A1 (en) Multiple stage delta sigma modulators
WO2003052939A2 (en) Sigma delta a/d converter with firdac converter
US8698662B2 (en) System and method for a high resolution digital input class D amplifier with feedback
CN110022156B (en) Continuous time delta sigma modulator
EP1391039A1 (en) Dynamic element matching
US6734816B2 (en) D/A converter with high jitter resistance
US7327295B1 (en) Constant edge-rate ternary output consecutive-edge modulator (CEM) method and apparatus
KR101559456B1 (en) A low-power·low-area third order sigma-delta modulator with delayed feed-forward path
Basetas et al. An efficient hardware architecture for the implementation of multi-step look-ahead sigma-delta modulators
US7782239B2 (en) Multi-stage resettable sigma-delta converters

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SC SD SE SG SI SK SL TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LU MC NL PT SE SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase in:

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP