WO2003050850A2 - Contacting of a semiconductor chip on a substrate using flip-chip-like technology - Google Patents

Contacting of a semiconductor chip on a substrate using flip-chip-like technology Download PDF

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Publication number
WO2003050850A2
WO2003050850A2 PCT/DE2002/004398 DE0204398W WO03050850A2 WO 2003050850 A2 WO2003050850 A2 WO 2003050850A2 DE 0204398 W DE0204398 W DE 0204398W WO 03050850 A2 WO03050850 A2 WO 03050850A2
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Prior art keywords
chip
contact
substrate
contact points
points
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PCT/DE2002/004398
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German (de)
French (fr)
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WO2003050850A3 (en
Inventor
Boris Mayerhofer
Jochen Müller
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Infineon Technologies Ag
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Publication of WO2003050850A2 publication Critical patent/WO2003050850A2/en
Publication of WO2003050850A3 publication Critical patent/WO2003050850A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]

Definitions

  • the invention relates to the arrangement or contacting of a chip on a substrate in flip-chip-like technology. Arrangements of the type described have a plurality of contact areas on the substrate on a contact side for defining a contact area layout, to which the chip is electrically connected. The chip arrangements are then often installed in carrier bodies, for example in chip cards.
  • FIG. 2 It has long been known from the prior art to connect a chip using flip-chip technology to the substrate. Such an embodiment is shown in Figure 2.
  • Two contact surfaces 12 are provided as an example on a contact side 11 of a substrate 10. The contact surfaces 12 could also be flush with the surface of the contact side 11.
  • a passivation layer (not shown in the figure) for protecting the integrated components is usually provided on the front side 21 of the chip 20.
  • the contact points 23 are located in or pass through the passivation layer in order to contact the integrated components formed in the front of the chip.
  • a potting compound 31 which may be an adhesive, for example, is also provided between the front side 21 and the contact side 11 of the substrate. This serves to protect the front of the chip and the electrical connections from moisture and to improve the mechanical mounting of the chip on the substrate.
  • the potting compound 31 could - even if this is not shown in Figure 2 - completely surround the chip 20. If the chip arrangements described are installed in chip cards, there is a risk when using the chip cards that the chips or the electrical connections will be damaged due to bending loads acting on the chip card or the chip arrangement. To avoid such damage, it is known that predetermined bending points, eg. B. by targeted weakening of the substrate to provide to keep the mechanical loads away from the chip.
  • the risk of the chip or the components formed in it being damaged when subjected to a bending load is greater in chip arrangements which are constructed using flip-chip technology than in conventional chip arrangements which are used to establish electrical contact between the contact points of the chip and the contact surfaces of the substrate use bond wires.
  • the object of the present invention is therefore to provide a chip arrangement in which the chip is applied to a substrate and which has a high load capacity in the event of a bending force acting on the chip arrangement.
  • the invention is based on the finding that the breakage of a chip in a chip arrangement mainly arises from the side which is connected to the substrate.
  • the highest risk of breakage arises from the front and thus damage to the integrated components formed in the front is likely.
  • the invention therefore provides a chip arrangement with a chip having a front side and a rear side, in the front side of which at least one integrated component is formed, the chip being provided with contact points on or in its front side for contacting the integrated component. Furthermore, according to the invention, the chip has contact material elements made of a contact material, which extend in material receptacles between the contact points and contact points on the back of the chip.
  • the chip arrangement furthermore comprises a substrate with a contact side, on which contact areas for the definition of a contact area layout are formed. The chip is arranged on the substrate in such a way that the back of the chip is arranged on the contact side of the substrate and the contact surfaces come into contact with the contacts while making an electrical connection.
  • the contact points on the front of the chip do not necessarily have to be formed on the front. Rather, the contact points, which are used to contact the integrated component, can also be arranged in the front, that is to say not accessible from the outside. For example, the contact points could lie under the passivation layer mentioned at the beginning. In both cases, the contact points are designed as metallizations, so-called contact pads. However, this is not even necessary if the contact points represent a doped region buried in the front of the chip.
  • the chip is thinned on its back.
  • the back can be thinned using different methods, e.g. B. etching or polishing. By choosing suitable processing methods, it is possible to increase the breaking strength of the back. If the contact points are formed on the front side of the chip, the possibilities for increasing the front side in terms of their breaking strength are limited. The backside thinning of the chip thus serves for mechanical stabilization and to increase the breaking strength of the chip.
  • the material receptacles run through the chip.
  • the contact material elements located in the material receptacles thus represent plated-through holes or rear-side contacts.
  • the production of plated-through holes or rear-side contacts represents a proven and reliable manufacturing process.
  • the provision of plated-through holes may be dispensed with.
  • FIG. 2 shows a chip arrangement described in the prior art and described in the introduction.
  • Figure 1 shows an embodiment of the chip arrangement according to the invention.
  • two contact surfaces 12 are arranged on the contact side 11 of a substrate 10.
  • the contact surfaces 12 could also be embedded in the contact side 11, so that they are flush with its surface.
  • a chip 20 has a front side 21 and a rear side 22. At least one integrated component is formed in the front 21.
  • the front side 21 is therefore also referred to as the “active side” of the chip.
  • Two contact points 23 are provided on the front side 21 by way of example and are designed in a conventional manner. This means that a passivation layer is applied to the front side 21, on which the contact points 23 are formed. The contact points 23 then extend through the passivation layer and each contact at least one integrated component.
  • the rear side 22 of the chip 20 faces the contact side 11 of the substrate 10 and is mechanically firmly connected to it.
  • the mechanical connection can be implemented, for example, using an adhesive 31.
  • material receptacles 29 are formed in the chip, which extend from the rear side 22 to the side of the contact points 23 facing away from the front side 21.
  • the side walls 27 one each material receptacle 29 are lined with an insulating material 28.
  • the remaining area is filled with a contact material element 24 made of an electrically conductive contact material.
  • the contact material elements form contact points 26, which in turn are connected to the contact surfaces 12 of the substrate via contact metallizations 25.
  • the contact metallizations 25 can be solder bumps or bumps made of conductive adhesive, for example. After the electrical connection between the contact points 23 of the chip 20 and the contact surfaces 12 has been established via the contact material elements and the contact metallizations 25, the casting compound or the adhesive 31 is applied, so that an airtight closure of the electrical contacts is ensured. In addition, the potting compound or the adhesive 31, as already shown above, also takes over a mechanical holding of the chip on the substrate 10.
  • the material receptacles 29 with the contact material element 24 located therein are also used as a via or
  • the material receptacle 29 can be formed in various ways:
  • a trench By an appropriate etching process at a suitable point in the process control before thinning the wafer or the chip.
  • a trench (“trench”) is etched from the front side 21 at the corresponding points in the through-hole, which is slightly deeper than the later component thickness.
  • the trench is filled with the provided electrically conductive contact material and contacted with the corresponding contact points 23 of the components on the chip 20. Through the subsequent thinning process, the underside of the filled trench is exposed and forms the desired contact point on the back.
  • the chip 20 is thinned from the rear side 22 thereof.
  • a material receptacle 29 is formed in the chip 20 from the back at the points at which the contact points 23 are located on the front.
  • the formation of the material intake can, for. B. done by an etching process.
  • electrical contact can be made with them.
  • the side walls 27 of the material receptacles 29 are first lined with an insulating material. The remaining free space is then filled with an electrically conductive contact material.
  • the contact material element 24 can now be electrically contacted at the contact point formed on the rear side.
  • the contact can be made with all connection technologies known from the field of flip-chip technology.
  • the chip can be thinned by etching, polishing, grinding or other material-removing processes. Depending on the processing method, the breaking strength of the back is increased. The material damage caused by the thinning process (grinding) is also removed by etching or polishing; the Si surface produced in this way has high breaking stresses. The maximal The tensile strength of the front is determined by the generation of the components and is usually lower.
  • the present connection technology between chip and substrate naturally does not require that the contact points 23 on the front of the chip be accessible.
  • the contact points 23 could, for example, be located below a further insulation layer.
  • the invention thus creates a chip arrangement which has a higher breaking strength than the prior art, since the connection of the chip takes place via the rear side machined for maximum breaking strength.

Abstract

The invention relates to a chip assembly comprising a chip (20) having a front side (21) and a rear side (22) and in whose front side at least one integrated component is provided. The chip is provided, on or in the front side thereof, with contact locations (23) serving to contact the integrated component and has contact material elements (24) made of a contact material that extend in material receptacles (29) between the contact locations (23) and contact points (26) on the rear side of the chip. The chip assembly also comprises a substrate (10) with a contact side (11) on which contact surfaces (12) for defining a contact surface layout are provided. The chip is placed on the substrate so that the rear side (22) of the chip (20) is situated on the contact side (11) of the substrate (10), and the contact surfaces (12) rest opposite the contact points (26) while establishing an electrical connection.

Description

Beschreibungdescription
Chipanordnungchip system
Die Erfindung betrifft die Anordnung bzw. Kontaktierung eines Chips auf einem Substrat in Flip-Chip-ähnlicher Technologie. Anordnungen der beschriebenen Art weisen auf dem Substrat auf einer Kontaktseite eine Mehrzahl an Kontaktflächen zur Definition eines Kontaktflächenlayouts auf, mit denen der Chip elektrisch verbunden ist. Häufig werden die Chipanordnungen dann in Trägerkörper, beispielsweise in Chipkarten, eingebaut .The invention relates to the arrangement or contacting of a chip on a substrate in flip-chip-like technology. Arrangements of the type described have a plurality of contact areas on the substrate on a contact side for defining a contact area layout, to which the chip is electrically connected. The chip arrangements are then often installed in carrier bodies, for example in chip cards.
Aus dem Stand der Technik ist es seit langem bekannt, einen Chip in Flip-Chip-Technologie mit dem Substrat zu verbinden. Ein derartiges Ausführungsbeispiel ist in der Figur 2 dargestellt. Auf einer Kontaktseite 11 eines Substrats 10 sind beispielhaft zwei Kontaktflächen 12 vorgesehen. Die Kontaktflächen 12 könnten dabei auch bündig mit der Fläche der Kontaktseite 11 abschließen. Ein Chip 20, der auf seiner Vorder- seite 21 mit Kontaktstellen 23 versehen ist, die zur Kontaktierung eines in der Vorderseite integrierten Bauelementes dienen, ist jeweils über eine Kontaktmetallisierung 25 mit den Kontaktflächen 12 auf dem Substrat 10 verbunden. Auf der Vorderseite 21 des Chips 20 ist üblicherweise eine (in der Figur nicht dargestellte) Passivierungsschicht zum Schutz der integrierten Bauelemente vorgesehen. Die Kontaktstellen 23 sind in der Passivierungsschicht gelegen oder reichen durch diese hindurch, um die in der Vorderseite des Chips ausgebildete integrierten Bauelemente zu kontaktieren. Zwischen der Vorderseite 21 und der Kontaktseite 11 des Substrates ist weiterhin eine Vergußmasse 31, die beispielsweise ein Kleber sein kann, vorgesehen. Dieser dient dazu, die Vorderseite des Chips sowie die elektrischen Verbindungen vor Feuchte zu schützen und die mechanische Halterung des Chip auf dem Sub- strat zu verbessern. Die Vergußmasse 31 könnte - auch wenn dies in Figur 2 nicht dargestellt ist - den Chip 20 vollständig umgeben. Werden die beschriebenen Chipanordnungen in Chipkarten eingebaut, so besteht bei der Nutzung der Chipkarten die Gefahr, daß die Chips oder die elektrischen Verbindungen auf Grund auf die Chipkarte bzw. die Chipanordnung einwirkender Biege- belastungen beschädigt werden. Zur Vermeidung derartiger Beschädigungen ist es bekannt, in dem Substrat Soll- Biegestellen, z. B. durch gezielte Schwächung des Substrates, vorzusehen, um die mechanischen Belastungen von dem Chip fernzuhalten. Die Gefahr, daß der Chip bzw. die in ihm ausgebildeten Bauelemente bei einer Biegebelastung beschädigt wird, ist in Chipanordnungen, die in Flip-Chip-Technologie aufgebaut sind, größer als bei konventionellen Chipanord- nungen, die zur Herstellung eines elektrischen Kontaktes zwischen den Kontaktstellen des Chips und den Kontaktflächen des Substrates Bonddrähte verwenden.It has long been known from the prior art to connect a chip using flip-chip technology to the substrate. Such an embodiment is shown in Figure 2. Two contact surfaces 12 are provided as an example on a contact side 11 of a substrate 10. The contact surfaces 12 could also be flush with the surface of the contact side 11. A chip 20, which is provided on its front side 21 with contact points 23 which serve to contact a component integrated in the front side, is connected to the contact areas 12 on the substrate 10 via a contact metallization 25. A passivation layer (not shown in the figure) for protecting the integrated components is usually provided on the front side 21 of the chip 20. The contact points 23 are located in or pass through the passivation layer in order to contact the integrated components formed in the front of the chip. A potting compound 31, which may be an adhesive, for example, is also provided between the front side 21 and the contact side 11 of the substrate. This serves to protect the front of the chip and the electrical connections from moisture and to improve the mechanical mounting of the chip on the substrate. The potting compound 31 could - even if this is not shown in Figure 2 - completely surround the chip 20. If the chip arrangements described are installed in chip cards, there is a risk when using the chip cards that the chips or the electrical connections will be damaged due to bending loads acting on the chip card or the chip arrangement. To avoid such damage, it is known that predetermined bending points, eg. B. by targeted weakening of the substrate to provide to keep the mechanical loads away from the chip. The risk of the chip or the components formed in it being damaged when subjected to a bending load is greater in chip arrangements which are constructed using flip-chip technology than in conventional chip arrangements which are used to establish electrical contact between the contact points of the chip and the contact surfaces of the substrate use bond wires.
Die Aufgabe der vorliegenden Erfindung besteht deshalb darin, eine Chipanordnung anzugeben, bei der der Chip auf ein Substrat aufgebracht ist und welche eine hohe Belastbarkeit im Falle einer auf die Chipanordnung einwirkenden Biegekraft aufweist .The object of the present invention is therefore to provide a chip arrangement in which the chip is applied to a substrate and which has a high load capacity in the event of a bending force acting on the chip arrangement.
Diese Aufgabe wird mit den Merkmalen des Anspruches 1 gelöst. Vorteilhafte Ausgestaltungen ergeben sich aus den abhängigen Ansprüchen .This object is achieved with the features of claim 1. Advantageous configurations result from the dependent claims.
Der Erfindung liegt die Erkenntnis zu Grunde, daß der Bruch eines Chips in einer Chipanordnung hauptsächlich von der Seite ausgeht, die mit dem Substrat verbunden ist. Bei Chipanordnungen, die in Flip-Chip-Technologie auf das Substrat aufgebracht sind, bedeutet dies, daß die Vorderseite, in der die integrierten Bauelemente ausgebildet sind, mit der Kontakt- seite des Substrates verbunden ist. Dies hat zur Folge, daß von der Vorderseite die höchste Bruchgefahr ausgeht und somit eine Beschädigung der in der Vorderseite ausgebildeten integrierten Bauelemente wahrscheinlich ist.The invention is based on the finding that the breakage of a chip in a chip arrangement mainly arises from the side which is connected to the substrate. In the case of chip arrangements which are applied to the substrate using flip-chip technology, this means that the front side in which the integrated components are formed is connected to the contact side of the substrate. As a result, the highest risk of breakage arises from the front and thus damage to the integrated components formed in the front is likely.
Die Erfindung sieht deshalb eine Chipanordnung mit einem eine Vorderseite und eine Rückseite aufweisenden Chip vor, in dessen Vorderseite mindestens ein integriertes Bauelement ausgebildet ist, wobei der Chip auf oder in seiner Vorderseite zur Kontaktierung des integrierten Bauelementes mit Kontaktstellen versehen ist. Weiterhin weist der Chip erfindungsgemäß Kontaktmaterialelemente aus einem Kontaktmaterial auf, die sich in Materialaufnahmen zwischen den Kontaktstellen und Kontaktpunkten auf der Rückseite des Chips erstrecken. Die Chipanordnung umfaßt weiterhin ein Substrat mit einer Kontaktseite, auf der Kontaktflächen zur Definition eines Kon- taktflächenlayouts ausgebildet sind. Der Chip ist derart auf dem Substrat angeordnet, daß die Rückseite des Chips auf der Kontaktseite des Substrats angeordnet ist und die Kontaktflächen unter Herstellung einer elektrischen Verbindung gegenüberliegend den Kontakt unkten zum Liegen kommen.The invention therefore provides a chip arrangement with a chip having a front side and a rear side, in the front side of which at least one integrated component is formed, the chip being provided with contact points on or in its front side for contacting the integrated component. Furthermore, according to the invention, the chip has contact material elements made of a contact material, which extend in material receptacles between the contact points and contact points on the back of the chip. The chip arrangement furthermore comprises a substrate with a contact side, on which contact areas for the definition of a contact area layout are formed. The chip is arranged on the substrate in such a way that the back of the chip is arranged on the contact side of the substrate and the contact surfaces come into contact with the contacts while making an electrical connection.
Dies bedeutet, daß die Flip-Chip-ähnliche Kontaktierung des Chips mit dem Substrat über dessen Rückseite erfolgt. Da sich die integrierten Bauelemente nunmehr auf der der Kontaktseite des Substrats abgewandten Seite des Chips befinden, muß die elektrische Verbindung beispielsweise mittels einer Durchkon- taktierung oder mittels entlang der Oberfläche des Chips verlaufender Leiterzüge erfolgen, so daß auch auf der Rückseite des Chips entsprechende Kontaktpunkte zur weiteren Kontaktierung zur Verfügung stehen.This means that the flip-chip-like contacting of the chip with the substrate takes place over the back. Since the integrated components are now located on the side of the chip facing away from the contact side of the substrate, the electrical connection must be made, for example, by means of a through contact or by means of conductor runs running along the surface of the chip, so that corresponding contact points are also provided on the back of the chip further contacts are available.
Dies hat zur Folge, daß die Kontaktstellen auf der Vorderseite des Chips nicht notwendigerweise auf der Vorderseite ausgebildet sein müssen. Vielmehr können die Kontaktstellen, die zur Kontaktierung des integrierten Bauelementes dienen, auch in der Vorderseite, also nicht von außen her zugänglich, angeordnet sein. Beispielsweise könnten die Kontaktstellen unter der eingangs genannten Passivierungsschicht liegen. In beiden Fällen sind die Kontaktstellen als Metallisierungen, sogenannte Kontaktpads, ausgebildet. Jedoch ist nicht mal dies notwendig, wenn die Kontaktstellen ein dotiertes Gebiet, das in der Vorderseite des Chips vergraben ist, darstellen.As a result, the contact points on the front of the chip do not necessarily have to be formed on the front. Rather, the contact points, which are used to contact the integrated component, can also be arranged in the front, that is to say not accessible from the outside. For example, the contact points could lie under the passivation layer mentioned at the beginning. In In both cases, the contact points are designed as metallizations, so-called contact pads. However, this is not even necessary if the contact points represent a doped region buried in the front of the chip.
In einer bevorzugten Ausgestaltung ist vorgesehen, daß der Chip auf seiner Rückseite gedünnt ist . Das Dünnen der Rückseite kann mittels unterschiedlicher Methoden, z. B. Ätzen oder Polieren erfolgen. Durch die Wahl geeigneter Bearbei- tungsmethoden ist es möglich, die Bruchfestigkeit der Rückseite zu erhöhen. Sofern die Kontaktstellen auf der Vorderseite des Chips ausgebildet sind, sind die Möglichkeiten die Vorderseite in Ihrer Bruchfestigkeit zu erhöhen jedoch beschränkt. Das Rückseitendünnen des Chips dient somit zur me- chanischen Stabilisierung und zur Erhöhung der Bruchfestigkeit des Chips .In a preferred embodiment it is provided that the chip is thinned on its back. The back can be thinned using different methods, e.g. B. etching or polishing. By choosing suitable processing methods, it is possible to increase the breaking strength of the back. If the contact points are formed on the front side of the chip, the possibilities for increasing the front side in terms of their breaking strength are limited. The backside thinning of the chip thus serves for mechanical stabilization and to increase the breaking strength of the chip.
In einer weiteren vorteilhaften Ausgestaltung ist vorgesehen, daß die Materialaufnahmen durch den Chip hindurch verlaufen. Die in den Materialaufnahmen befindlichen Kontaktmaterialelemente stellen somit Durchkontaktierungen bzw. Rückseitenkontakte dar. Insbesondere im Zusammenhang mit der Rückseiten- dünnung stellt die Herstellung von Durchkontaktierungen bzw. Rückseitenkontakten ein erprobtes und zuverlässiges Herstel- lungsverfahren dar.In a further advantageous embodiment it is provided that the material receptacles run through the chip. The contact material elements located in the material receptacles thus represent plated-through holes or rear-side contacts. In particular in connection with the rear-side thinning, the production of plated-through holes or rear-side contacts represents a proven and reliable manufacturing process.
Alternativ oder zusätzlich kann vorgesehen sein, die Materialaufnahmen entlang der Vorderseite, der Rückseite und zumindest einer die Vorder- und Rückseite verbindenden Seiten- kante des Chips verlaufen zu lassen. Die Herstellung eines elektrischen Kontaktes zwischen den auf der Vorderseite befindlichen Kontaktstellen und den auf der Rückseite befindlichen Kontaktpunkten erfolgt somit über auf der Oberfläche des Chips verlaufende Leiterstrukturen. In dieser Variante kann gegebenenfalls auf das Vorsehen von Durchkontaktierungen verzichtet werden. Die Erfindung wird an Hand der Zeichnungen nachfolgend näher erläutert. Es zeigen:Alternatively or additionally, provision can be made for the material receptacles to run along the front, the rear and at least one side edge of the chip connecting the front and rear. Electrical contact between the contact points located on the front side and the contact points located on the rear side is thus established via conductor structures running on the surface of the chip. In this variant, the provision of plated-through holes may be dispensed with. The invention is explained in more detail below with reference to the drawings. Show it:
Figur 1 ein Ausführungsbeispiel der erfindungsgemäßen Chipanordnung, und1 shows an embodiment of the chip arrangement according to the invention, and
Figur 2 eine aus dem Stand der Technik und einleitend beschriebene Chipanordnung.FIG. 2 shows a chip arrangement described in the prior art and described in the introduction.
Figur 1 zeigt ein Ausführungsbeispiel der erfindungsgemäßen Chipanordnung. Auf der Kontaktseite 11 eines Substrates 10 sind beispielhaft zwei Kontaktflächen 12 angeordnet. Die Kontaktflächen 12 könnten auch in der Kontaktseite 11 eingelassen sein, so daß sie bündig mit dessen Oberfläche abschlie- ßen.Figure 1 shows an embodiment of the chip arrangement according to the invention. By way of example, two contact surfaces 12 are arranged on the contact side 11 of a substrate 10. The contact surfaces 12 could also be embedded in the contact side 11, so that they are flush with its surface.
Ein Chip 20 weist eine Vorderseite 21 und eine Rückseite 22 auf. In der Vorderseite 21 ist zumindest ein integriertes Bauelement ausgebildet. Die Vorderseite 21 wird deshalb auch als "aktive Seite" des Chips bezeichnet. Auf der Vorderseite 21 sind beispielhaft zwei Kontaktstellen 23 vorgesehen, die in konventioneller Weise ausgebildet sind. Dies bedeutet auf der Vorderseite 21 ist eine Passivierungsschicht aufgebracht, auf welcher die Kontaktstellen 23 ausgebildet sind. Die Kon- taktstellen 23 reichen dann durch die Passivierungsschicht hindurch und kontaktieren jeweils wenigstens ein integriertes Bauelement .A chip 20 has a front side 21 and a rear side 22. At least one integrated component is formed in the front 21. The front side 21 is therefore also referred to as the “active side” of the chip. Two contact points 23 are provided on the front side 21 by way of example and are designed in a conventional manner. This means that a passivation layer is applied to the front side 21, on which the contact points 23 are formed. The contact points 23 then extend through the passivation layer and each contact at least one integrated component.
Erfindungsgemäß ist die Rückseite 22 des Chips 20 der Kon- taktseite 11 des Substrates 10 zugewandt und mit dieser mechanisch fest verbunden. Die mechanische Verbindung kann beispielsweise über einen Kleber 31 realisiert sein. Zur Herstellung eines elektrischen Kontaktes zwischen den Kontaktstellen 23 und den Kontaktflächen 12 des Substrates 10 sind in dem Chip Materialaufnahmen 29 ausgebildet, die von der Rückseite 22 bis zu der von der Vorderseite 21 abgewandten Seite der Kontaktstellen 23 reichen. Die Seitenwände 27 einer jeden Materialaufnahme 29 sind mit einem isolierenden Material 28 ausgekleidet. Der übrige Bereich ist mit einem Kontakt- materialelement 24 aus einem elektrisch leitenden Kontaktmaterial ausgefüllt. An der Rückseite 22 bilden die Kontaktma- terialelemente Kontaktstellen 26, die ihrerseits über Kontaktmetallisierungen 25 mit den Kontaktflächen 12 des Substrats verbunden sind. Die Kontaktmetallisierungen 25 können beispielsweise Lotbumps oder Bumps aus leitfähigem Kleber sein. Nachdem die elektrische Verbindung zwischen den Kon- taktstellen 23 des Chips 20 und den Kontaktflächen 12 über die Kontaktmaterialelemente und die Kontaktmetallisierungen 25 hergestellt ist, wird die Vergußmasse oder der Kleber 31 aufgebracht, so daß ein luftdichter Abschluß der elektrischen Kontakte sichergestellt ist. Darüber hinaus übernimmt die Vergußmasse oder der Kleber 31, wie oben bereits dargestellt, auch eine mechanische Halterung des Chips auf dem Substrat 10.According to the invention, the rear side 22 of the chip 20 faces the contact side 11 of the substrate 10 and is mechanically firmly connected to it. The mechanical connection can be implemented, for example, using an adhesive 31. To produce an electrical contact between the contact points 23 and the contact surfaces 12 of the substrate 10, material receptacles 29 are formed in the chip, which extend from the rear side 22 to the side of the contact points 23 facing away from the front side 21. The side walls 27 one each material receptacle 29 are lined with an insulating material 28. The remaining area is filled with a contact material element 24 made of an electrically conductive contact material. On the rear side 22, the contact material elements form contact points 26, which in turn are connected to the contact surfaces 12 of the substrate via contact metallizations 25. The contact metallizations 25 can be solder bumps or bumps made of conductive adhesive, for example. After the electrical connection between the contact points 23 of the chip 20 and the contact surfaces 12 has been established via the contact material elements and the contact metallizations 25, the casting compound or the adhesive 31 is applied, so that an airtight closure of the electrical contacts is ensured. In addition, the potting compound or the adhesive 31, as already shown above, also takes over a mechanical holding of the chip on the substrate 10.
Die Materialaufnahmen 29 mit dem darin befindlichen Kontakt- materialelement 24 sind auch als Durchkontaktierung oderThe material receptacles 29 with the contact material element 24 located therein are also used as a via or
Rückseitenkontakte bekannt. Die Herstellung derartiger Durchkontakte ist aus dem Stand der Technik seit langem bekannt und soll deshalb an dieser Stelle nur kurz dargestellt werden. Das Ausbilden der Materialaufnahme 29 kann dabei auf verschiedene Arten erfolgen:Rear contacts known. The production of such through contacts has long been known from the prior art and is therefore only to be briefly described at this point. The material receptacle 29 can be formed in various ways:
a) Durch einen entsprechenden Ätzprozeß an einer geeigneten Stelle in der Prozeßführung vor dem Dünnen des Wafers bzw. des Chips. Dabei wird ein Graben ("Trench") von der Vorder- seite 21 an die entsprechende Stellen der Durchkontaktierung geätzt, der geringfügig tiefer ist als die spätere Bauteildicke.a) By an appropriate etching process at a suitable point in the process control before thinning the wafer or the chip. In this case, a trench (“trench”) is etched from the front side 21 at the corresponding points in the through-hole, which is slightly deeper than the later component thickness.
Der Graben wird mit dem vorgesehenen elektrisch leitfähigen Kontaktmaterial aufgefüllt und mit den entsprechenden Kontaktstellen 23 der Bauelemente auf dem Chip 20 kontaktiert. Durch den später folgenden Dünnungsprozeß wird die Unterseite des gefüllten Trenches freigelegt und bildet die gewünschte Kontaktstelle auf der Rückseite.The trench is filled with the provided electrically conductive contact material and contacted with the corresponding contact points 23 of the components on the chip 20. Through the subsequent thinning process, the underside of the filled trench is exposed and forms the desired contact point on the back.
b) Nach der Prozessierung des Chips 20, d. h. nach dem Aus- bilden sämtlicher integrierter Bauelemente in der Vorderseite 21, dem Aufbringen der Passivierungsschicht und dem Ausbilden der Kontaktstellen 23 erfolgt eine Dünnung des Chips 20 von dessen Rückseite 22 her. Nach dem Dünnen der Rückseite 22 wird an den Stellen, an denen die Kontaktstellen 23 auf der Vorderseite gelegen sind, eine Materialaufnahme 29 von der Rückseite her in den Chip 20 ausgebildet. Das Ausbilden der Materialaufnahme kann z. B. durch einen Ätzprozeß erfolgen. Sobald die Rückseiten der Kontaktstellen 23 erreicht sind, kann ein elektrischer Kontakt zu diesen hergestellt werden. Zu diesem Zweck werden zunächst die Seitenwände 27 der Materialaufnahmen 29 mit einem isolierendem Material ausgekleidet. Anschließend wird der verbleibende Freiraum mit einem elektrisch leitfähigem Kontaktmaterial aufgefüllt. Da das Auffüllen mit dem Kontaktmaterial von der Rückseite 22 des Chips 20 her erfolgt, kann das Kontaktmaterialelement 24 an der an der Rückseite gebildeten Kontaktstelle nunmehr elektrisch kontaktiert werden. Insbesondere ist es hier auch möglich, auf die Rückseite 22 des Chips 20 zunächst eine Umver- drahtungsebene aufzubringen, um beispielsweise ein anderes, an das Kontaktflächenlayout angepasstes Layout der Kontaktstellen zu erzielen.b) After processing the chip 20, d. H. after the formation of all integrated components in the front side 21, the application of the passivation layer and the formation of the contact points 23, the chip 20 is thinned from the rear side 22 thereof. After the back 22 has been thinned, a material receptacle 29 is formed in the chip 20 from the back at the points at which the contact points 23 are located on the front. The formation of the material intake can, for. B. done by an etching process. As soon as the rear sides of the contact points 23 are reached, electrical contact can be made with them. For this purpose, the side walls 27 of the material receptacles 29 are first lined with an insulating material. The remaining free space is then filled with an electrically conductive contact material. Since the filling with the contact material takes place from the rear side 22 of the chip 20, the contact material element 24 can now be electrically contacted at the contact point formed on the rear side. In particular, it is also possible here first to apply a rewiring level to the rear side 22 of the chip 20 in order, for example, to achieve a different layout of the contact points that is adapted to the contact area layout.
Die Kontaktierung kann mit allen aus dem Bereich der Flip- Chip-Technologie bekannten Verbindungstechnologien erfolgen.The contact can be made with all connection technologies known from the field of flip-chip technology.
Das Dünnen des Chips kann durch Ätzen, Polieren, Schleifen oder andere Material abtragende Verfahren vorgenommen werden. Abhängig von der Bearbeitungsmethode wird dabei die Bruchfestigkeit der Rückseite erhöht . Die durch den Dünnungsprozeß (Schleifen) verursachten Materialbeschädigungen werden auch durch Ätzen oder Polieren entfernt; die dadurch erzeugte Si- Oberflache weist hohe Bruchspannungen auf. Die maximale Bruchspannung der Vorderseite ist durch die Erzeugung der Bauelemente vorgegeben und in der Regel niedriger.The chip can be thinned by etching, polishing, grinding or other material-removing processes. Depending on the processing method, the breaking strength of the back is increased. The material damage caused by the thinning process (grinding) is also removed by etching or polishing; the Si surface produced in this way has high breaking stresses. The maximal The tensile strength of the front is determined by the generation of the components and is usually lower.
Auch wenn dies in der Figur 1 nicht explizit dargestellt ist, erfordert es die vorliegende Verbindungstechnologie zwischen Chip und Substrat natürlich nicht, daß die Kontaktstellen 23 auf der Vorderseite des Chips zugänglich sind. Die Kontaktstellen 23 könnten beispielsweise unterhalb einer weiteren Isolationsschicht gelegen sein.Even if this is not explicitly shown in FIG. 1, the present connection technology between chip and substrate naturally does not require that the contact points 23 on the front of the chip be accessible. The contact points 23 could, for example, be located below a further insulation layer.
Gleichfalls ist es denkbar, den elektrischen Kontakt zwischen den Kontaktstellen 23 und den Kontaktpunkten 26 auf der Rückseite des Chips über entlang der Oberfläche des Chips verlaufender Leiterstrukturen herzustellen. Denkbar ist diese Vari- ante vor allem dann, wenn gegebenenfalls manche der Kontaktstellen nicht über eine durch den Chip hindurchgehende Durchkontaktierungen kontaktiert werden können.It is also conceivable to establish the electrical contact between the contact points 23 and the contact points 26 on the back of the chip via conductor structures running along the surface of the chip. This variant is particularly conceivable if, if applicable, some of the contact points cannot be contacted via plated-through holes passing through the chip.
Die Erfindung schafft somit eine Chipanordnung, die eine ge- genüber dem Stand der Technik höhere Bruchfestigkeit aufweist, da die Verbindung des Chips über die auf maximale Bruchfestigkeit bearbeitete Rückseite erfolgt . The invention thus creates a chip arrangement which has a higher breaking strength than the prior art, since the connection of the chip takes place via the rear side machined for maximum breaking strength.
BezugszeichenlisteLIST OF REFERENCE NUMBERS
10 Substrat 11 Kontaktseite10 substrate 11 contact side
12 Kontaktfläche12 contact surface
20 Chip20 chip
21 Vorderseite 22 Rückseite21 front 22 rear
23 Kontaktstelle23 contact point
24 Kontaktmaterialelement24 contact material element
25 Kontaktmetallisierung 26 Kontakt punkt 27 Seitenwand (der Materialaufnahme )25 contact metallization 26 contact point 27 side wall (of the material holder)
28 Isolierung28 insulation
29 Materialaufnahme29 Material intake
30 Seitenkante 31 Kleber 30 side edge 31 adhesive

Claims

Patentansprüche claims
1. Chipanordnung mit einem eine Vorderseite (21) und eine Rückseite (22) aufweisenden Chip (20) , in dessen Vorderseite (21) mindestens ein integriertes Bauelement ausgebildet ist, wobei der Chip (20) auf oder in seiner Vorderseite (21) zur Kontaktierung des integrierten Bauelementes mit Kontaktstellen (23) versehen ist und Kontaktmaterialelemente (24) aus einem Kontaktmaterial aufweist, die sich in Materialaufnahmen (29) zwischen den Kontaktstellen (23) und Kontaktpunkten (26) auf der Rückseite (22) des Chips (20) erstrecken, und mit einem Substrat (10) mit einer Kontaktseite (11) , auf der Kontaktflächen (12) zur Definition eines Kontaktflächenlayouts ausgebildet sind, wobei der Chip (20) derart auf dem Substrat (10) angeordnet ist, daß die Rückseite (22) des Chips (20) auf der Kontaktseite (11) des Substrats (10) angeordnet ist und die Kontaktflächen (12) unter Herstellung einer elektrischen Verbindung gegenüberliegend den Kontakt unkten (26) zum Liegen kommen.1. Chip arrangement with a front (21) and a back (22) having chip (20), in the front (21) of which at least one integrated component is formed, the chip (20) on or in its front (21) Contacting of the integrated component is provided with contact points (23) and has contact material elements (24) made of a contact material, which are located in material receptacles (29) between the contact points (23) and contact points (26) on the back (22) of the chip (20). extend, and with a substrate (10) with a contact side (11) on which contact surfaces (12) for defining a contact surface layout are formed, the chip (20) being arranged on the substrate (10) such that the rear side (22 ) of the chip (20) is arranged on the contact side (11) of the substrate (10) and the contact surfaces (12) come into contact with the contacts (26) while making an electrical connection.
2. Chipanordnung nach Anspruch 1, bei der der Chip (20) auf seiner Rückseite (22) gedünnt ist.2. Chip arrangement according to claim 1, wherein the chip (20) on its back (22) is thinned.
3. Chipanordnung nach Anspruch 1 oder 2, bei der die Mate- rialaufnahmen (29) durch den Chip (20) hindurch verlaufen.3. Chip arrangement according to claim 1 or 2, in which the material receptacles (29) run through the chip (20).
4. Chipanordnung nach Anspruch 1, 2 oder 3, bei der die Materialaufnahmen (29) entlang der Vorderseite (21) , der Rückseite (22) und zumindest einer die Vorder- und Rückseite verbin- dende Seitenkante (30) des Chips (20) verlaufen. 4. Chip arrangement according to claim 1, 2 or 3, wherein the material receptacles (29) along the front (21), the back (22) and at least one side edge (30) connecting the front and back of the chip (20) run.
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