WO2003044841A3 - Method of dicing a complex topologically structured wafer - Google Patents

Method of dicing a complex topologically structured wafer Download PDF

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Publication number
WO2003044841A3
WO2003044841A3 PCT/GB2002/005188 GB0205188W WO03044841A3 WO 2003044841 A3 WO2003044841 A3 WO 2003044841A3 GB 0205188 W GB0205188 W GB 0205188W WO 03044841 A3 WO03044841 A3 WO 03044841A3
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
chip
etched
dicing
complex
Prior art date
Application number
PCT/GB2002/005188
Other languages
French (fr)
Other versions
WO2003044841A2 (en
Inventor
Kian Hin Victor Teo
Hwi Siong Lim
Yee Loy Lam
Original Assignee
Denselight Semiconductors Pte
Kian Hin Victor Teo
Hwi Siong Lim
Yee Loy Lam
Finnie Peter John
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denselight Semiconductors Pte, Kian Hin Victor Teo, Hwi Siong Lim, Yee Loy Lam, Finnie Peter John filed Critical Denselight Semiconductors Pte
Priority to AU2002339181A priority Critical patent/AU2002339181A1/en
Publication of WO2003044841A2 publication Critical patent/WO2003044841A2/en
Publication of WO2003044841A3 publication Critical patent/WO2003044841A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting

Abstract

In the present invention, the boundary of the or each chip on a wafer is defined by the absence of metallization and the presence of a continuous etched trench. The metallization, comprising the deposition of a metal layer, is not formed monolithically on the wafer, but is patterned to cover only the surface of the or each chip, thereby providing for electrical contact to the chip. The metal layer so deposited, contributes to the structural integrity and mechanical strength of the chip, but does not form a mechanical link between neighbouring chips. The trenches are etched to a depth that is substantially below the surface topology of the wafer. In particular, the trenches are etched to a depth that is substantially below layers in the wafer that contribute to the operation of devices fabricated on the wafer. Typically this would mean at least 3µm into the wafer substrate below the active regions grown on the substrate.
PCT/GB2002/005188 2001-11-19 2002-11-19 Method of dicing a complex topologically structured wafer WO2003044841A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002339181A AU2002339181A1 (en) 2001-11-19 2002-11-19 Method of dicing a complex topologically structured wafer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0127688.0 2001-11-19
GB0127688A GB0127688D0 (en) 2001-11-19 2001-11-19 Method of dicing a complex topologically structured wafer

Publications (2)

Publication Number Publication Date
WO2003044841A2 WO2003044841A2 (en) 2003-05-30
WO2003044841A3 true WO2003044841A3 (en) 2003-10-30

Family

ID=9926022

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2002/005188 WO2003044841A2 (en) 2001-11-19 2002-11-19 Method of dicing a complex topologically structured wafer

Country Status (3)

Country Link
AU (1) AU2002339181A1 (en)
GB (1) GB0127688D0 (en)
WO (1) WO2003044841A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2917910B1 (en) * 2007-06-22 2010-06-11 Thales Sa LIGHT DEVICE OPTIMIZED BY THE USE OF ARTIFICIAL MATERIALS AND METHOD OF MANUFACTURING THE SAME
GB2489397B (en) * 2011-03-04 2013-08-14 Univ Swansea A method of making a semiconductor wafer
US9196592B2 (en) 2014-01-10 2015-11-24 International Business Machines Corporation Methods of managing metal density in dicing channel and related integrated circuit structures

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3794883A (en) * 1973-02-01 1974-02-26 E Bylander Process for fabricating ge:hg infrared detector arrays and resulting article of manufacture
US4237601A (en) * 1978-10-13 1980-12-09 Exxon Research & Engineering Co. Method of cleaving semiconductor diode laser wafers
US5196378A (en) * 1987-12-17 1993-03-23 Texas Instruments Incorporated Method of fabricating an integrated circuit having active regions near a die edge
US6174789B1 (en) * 1998-02-20 2001-01-16 Nec Corporation Method of dividing a compound semiconductor wafer into pellets by utilizing extremely narrow scribe regions

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3794883A (en) * 1973-02-01 1974-02-26 E Bylander Process for fabricating ge:hg infrared detector arrays and resulting article of manufacture
US4237601A (en) * 1978-10-13 1980-12-09 Exxon Research & Engineering Co. Method of cleaving semiconductor diode laser wafers
US5196378A (en) * 1987-12-17 1993-03-23 Texas Instruments Incorporated Method of fabricating an integrated circuit having active regions near a die edge
US6174789B1 (en) * 1998-02-20 2001-01-16 Nec Corporation Method of dividing a compound semiconductor wafer into pellets by utilizing extremely narrow scribe regions

Also Published As

Publication number Publication date
WO2003044841A2 (en) 2003-05-30
AU2002339181A1 (en) 2003-06-10
GB0127688D0 (en) 2002-01-09

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