WO2003036884A3 - Method and apparatus for integration of communication links with a remote direct memory access protocol - Google Patents

Method and apparatus for integration of communication links with a remote direct memory access protocol Download PDF

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Publication number
WO2003036884A3
WO2003036884A3 PCT/US2002/033763 US0233763W WO03036884A3 WO 2003036884 A3 WO2003036884 A3 WO 2003036884A3 US 0233763 W US0233763 W US 0233763W WO 03036884 A3 WO03036884 A3 WO 03036884A3
Authority
WO
WIPO (PCT)
Prior art keywords
processor chips
application processor
direct memory
memory access
remote direct
Prior art date
Application number
PCT/US2002/033763
Other languages
French (fr)
Other versions
WO2003036884A2 (en
Inventor
Leslie D Kohn
Michael K Wong
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=23354532&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO2003036884(A3) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Priority to JP2003539249A priority Critical patent/JP2005508032A/en
Priority to EP02770647A priority patent/EP1466448B1/en
Priority to KR10-2004-7005904A priority patent/KR20040080431A/en
Priority to DE60239227T priority patent/DE60239227D1/en
Publication of WO2003036884A2 publication Critical patent/WO2003036884A2/en
Publication of WO2003036884A3 publication Critical patent/WO2003036884A3/en

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Classifications

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    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3889Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G06F9/3891Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters
    • GPHYSICS
    • G11INFORMATION STORAGE
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    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
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    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
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    • H04L45/745Address table lookup; Address filtering
    • HELECTRICITY
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    • H04L47/00Traffic control in data switching networks
    • H04L47/10Flow control; Congestion control
    • H04L47/24Traffic characterised by specific attributes, e.g. priority or QoS
    • H04L47/2441Traffic characterised by specific attributes, e.g. priority or QoS relying on flow classification, e.g. using integrated services [IntServ]
    • HELECTRICITY
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    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
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    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
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    • H04L49/9057Arrangements for supporting packet reassembly or resequencing
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
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    • H04L49/9084Reactions to storage capacity overflow
    • H04L49/9089Reactions to storage capacity overflow replacing packets in a storage arrangement, e.g. pushout
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
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    • H04L69/00Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/22Parsing or analysis of headers
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one embodiment, a server is provided. The server includes multiple application processor chips. Each of the multiple application processor chips includes multiple processing cores. Multiple memories corresponding to the multiple processor chips are included. The multiple memories are configured such that one processor chip is associated with one memory. A plurality of fabric chips enabling each of the multiple application processor chips to access any of the multiple memories are included. The data associated with one of the multiple application processor chips is stored across each of the multiple memories. In one embodiment, the application processor chips include a remote direct memory access (RDMA) and striping engine. The RDMA and striping engine is configured to store data in a striped manner across the multiple memories. A method for allowing multiple processors to exchange information through horizontal scaling is also provided.
PCT/US2002/033763 2001-10-22 2002-10-21 Method and apparatus for integration of communication links with a remote direct memory access protocol WO2003036884A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2003539249A JP2005508032A (en) 2001-10-22 2002-10-21 Method and apparatus for integration of multiple communication links and remote direct memory access protocols
EP02770647A EP1466448B1 (en) 2001-10-22 2002-10-21 Method and apparatus for integration of communication links with a remote direct memory access protocol
KR10-2004-7005904A KR20040080431A (en) 2001-10-22 2002-10-21 Method and apparatus for integration of communication links with a remote direct memory access protocol
DE60239227T DE60239227D1 (en) 2001-10-22 2002-10-21 METHOD AND DEVICE TO INTEGRATE COMMUNICATION CONNECTIONS WITH A REMOTE DMA ACCESS PROTOCOL

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US34531501P 2001-10-22 2001-10-22
US60/345,315 2001-10-22

Publications (2)

Publication Number Publication Date
WO2003036884A2 WO2003036884A2 (en) 2003-05-01
WO2003036884A3 true WO2003036884A3 (en) 2004-08-12

Family

ID=23354532

Family Applications (6)

Application Number Title Priority Date Filing Date
PCT/US2002/033441 WO2003036485A2 (en) 2001-10-22 2002-10-18 System and method for caching dram using an egress buffer
PCT/US2002/033321 WO2003036508A2 (en) 2001-10-22 2002-10-18 Stream processor with cryptographic co-processor
PCT/US2002/033323 WO2003036450A2 (en) 2001-10-22 2002-10-18 Dram power management
PCT/US2002/033766 WO2003036902A2 (en) 2001-10-22 2002-10-21 Method and apparatus for a packet classifier using a two-step hash matching process
PCT/US2002/033762 WO2003036482A2 (en) 2001-10-22 2002-10-21 Multi-core multi-thread processor
PCT/US2002/033763 WO2003036884A2 (en) 2001-10-22 2002-10-21 Method and apparatus for integration of communication links with a remote direct memory access protocol

Family Applications Before (5)

Application Number Title Priority Date Filing Date
PCT/US2002/033441 WO2003036485A2 (en) 2001-10-22 2002-10-18 System and method for caching dram using an egress buffer
PCT/US2002/033321 WO2003036508A2 (en) 2001-10-22 2002-10-18 Stream processor with cryptographic co-processor
PCT/US2002/033323 WO2003036450A2 (en) 2001-10-22 2002-10-18 Dram power management
PCT/US2002/033766 WO2003036902A2 (en) 2001-10-22 2002-10-21 Method and apparatus for a packet classifier using a two-step hash matching process
PCT/US2002/033762 WO2003036482A2 (en) 2001-10-22 2002-10-21 Multi-core multi-thread processor

Country Status (10)

Country Link
US (7) US7248585B2 (en)
EP (6) EP1442365A2 (en)
JP (6) JP3789454B2 (en)
KR (6) KR20040091608A (en)
CN (1) CN1286019C (en)
AT (1) ATE518192T1 (en)
AU (2) AU2002337940A1 (en)
DE (4) DE60211730T2 (en)
TW (1) TWI240163B (en)
WO (6) WO2003036485A2 (en)

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