WO2003028276A2

WO2003028276A2 - Qpsk phase ambiguity corrector

Info

Publication number: WO2003028276A2
Application number: PCT/US2002/031044
Authority: WO
Inventors: S.Joseph Campanella
Original assignee: Worldspace Corporation
Priority date: 2001-09-28
Filing date: 2002-09-30
Publication date: 2003-04-03
Also published as: WO2003028276A3; WO2003028276A9; AU2002327788A1; CN1575553A; ZA200402409B; EP1430615A2

Abstract

A system and method for determining and correcting the phase shift between the carrier signal in a QPSK modulated data signal (402) and the local oscillator signal (403) in a receiver (404, 420, 480) of the QPSK modulated data signal by correcting the receiver's symbol information phase reference to 0° relative to the received carrier phase according to an output of a correcting means (480). Use is made of the unique seed property of pseudo random sequence generators (PRSG) (486, 502) in which inputting a 'seed' of length equal to the polynomial order of the PRSG, to a first PRSG, which was taken from the output of a second identical PRSG, causes the first PRSG to output a sequence of bits which will be the same as those in the second PRSG following the seed values. By comparing the received data signals, actually the PRSG sequence output bit stream, with a sequence of bits generated by a first PRSG in the receiver, which are supposed to be identical because of the unique seed property, a determination of the phase shift ambiguity between the LO and carrier signals can be made, and subsequently corrected. The principles of the invention also work for signals that modulated using octal phase shift keying.

Description

QPSK PHASE AMBIGUITY CORRECTOR

[0001] This application claims priority from U.S. provisional patent application Serial No. 60/300,813, filed September 28, 2001, the entire contents of which are herein incorporated by reference.

Field of the Invention

[0002] The field of the invention relates generally to telecommunications and demodulation techniques. More particularly, the invention relates to a transmitter and receiver pair designed to modulate and subsequently demodulate a QPSK modulated signal to enhance phase error detection between the carrier of the QPSK modulated signal, and the local oscillator used in the receiver to demodulate the QPSK modulated signal.

Background of the Invention

[0003] Digital modulation techniques are well known in the art. For example, frequency shift keying (FSK) is a well-known technique capable of transmitting two bits of information in a given bit transmission period. In this method, the frequency of the carrier signal is defined to be f for a logical value of 0, and f₂ for a logical value of 1. Another type of digital transmission is phase shift keying (PSK). Here, instead of the frequency changing with respect to the value of the bit, the phase of the carrier frequency changes. When a logical value 0 is transmitted, the phase shift of the carrier is zero degrees. When a logical value "1" is to be transmitted, a phase shift of 180 degrees is induced in the carrier signal. This is known as Binary PSK. Demodulators for both types, FSK and Binary PSK, easily demodulate the modulated signal by well-known signal processing techniques.

[0004] A further extension in the art of digital communication is quadrature phase shift keying, or QPSK. As its name implies, the carrier is modulated to produce four phase states; doing this doubles the bandwidth capacity to 2 bits per bit transmission period. Fig. 1 illustrates the four modulated phase states of an RF carrier in a QPSK modulation scheme. These four states are all that is needed to transmit the signal information content of symbols containing two bits. [0005] , QPSK modulation operates as follows. Each individual bit represents either a logical value "1" state or a logical value "0" state. These individual bit states can be represented respectively by digital values of 1 and -1. For a two bit symbol there are four states: (1,1), (0,1), (0,0) and (1,0). In Fig. 1 these are represented by two dimensional quadrature analog vectors having the values (1,1) 102, (-1,1) 104, (- 1,-1) 106 and (1,-1) 108 respectively. The latter are coded by QPSK modulation as the four RF carrier phase states 0°, 90°, 180°, and 270°.

[0006] This form of modulation can be used at frequencies in the radio frequency band from 1452 to 1492 MHz to carry broadcast channel information over satellite repeaters using time division multiplex (TDM) form. Details of a preferred TDM signal format for satellite broadcast are given in U.S. Patent No. 6,201,798 to S. Joseph Campanella et al, which is incorporated herein by reference in its entirety. [0007] Fig. 2 illustrates a block diagram of a front end of a prior art QPSK receiver. In Fig. 2, signal 202 is applied at the receiver input to ^"quadrature demodulator 204. Input signal 202 comprises a serial time sequence of binary digital bits that have been modulated onto a radio frequency carrier using two bits per symbol Quadrature Phase Shift Keying (QPSK). Quadrature phase demodulation of the QPSK modulated RF carrier is performed by quadrature demodulator 204. In quadrature demodulator 204, input signal 202 is branched to a first mixer 206 and a second mixer 208. Both the first mixer 206 and second mixer 208 have, as a second input, local oscillator (LO) signal 213, which is generated in LO 212. LO signal 213 is branched to first mixer 206 and second mixer 208. The frequency of LO 212 is adjusted by means of a carrier recovery circuit 214 to equal the carrier frequency of the input signal 202. Several versions of the carrier recovery circuit 214 are known. [0008] The output of LO 212 directly feeds second mixer 208 while the first mixer 206 receives the LO signal 213 after it is has passed through a 90° phase shifter 210. As a result of signal multiplication in both first mixer 206 and second mixer 208, the second mixer 208 outputs the signal component in-phase (I) with the carrier and the first mixer 206 outputs the signal component in quadrature-phase (Q) with the carrier. Consequently, the I and Q output values will respectively each be +1 or -1 in correspondence with the values shown in Fig. 1, thereby identifying the carrier phase values as 0°, 90?, 180°, or 270°. The phases, of course, correspond to the two-bit symbol values (1,1), (-1,1), (-1,-1) and (1,-1).

[0009] In QPSK receiver 204, it is the nature of the action of the carrier recovery circuitry 214 to arbitrarily lock LO signal 213 to a phase state shifted by 0°, 90°, 180°, and 270° relative to the received signal (input signal 202) carrier phase. Fig. 3 illustrates the relationship between the phase of carrier signal 302 and the phase of LO signal 213 in QPSK receiver 200, in two different locked phase shifting scenarios. Signal 304 represents LO signal 213 that is "locked", but has been shifted in phase by 90° with respect to carrier signal 302. As a result of this phase shift, an ambiguity arises that presents difficulties in correctly demodulating the intended signals. Another source of ambiguity is a phase slip caused by noise corruption. Noise is ubiquitous in communication systems, and this is particularly problematic when using QPSK modulation/de-modulation techniques for transmitting digital data. Signal 306 of Fig. 3 shows the locked LO signal 313 after a noise corrupting incident has caused a further 90° phase shift relative to carrier signal 302, for a total phase shift of 180° relative to carrier signal 302.

[0010] Thus, a need exists to improve the ability of a QPSK receiver to first correctly lock the local oscillator to the carrier signal with preferably a 0° phase shift to the carrier signal. Secondly, a need exists to improve the capability of the QPSK receiver, if noise corruption causes the LO signal to slip in phase relative to the carrier signal, to quickly correct the information component of the signal back to a zero degree phase shift in relation to the carrier signal.

Summary of the Invention

[0011] The present invention relates to a method for correcting a receiver local oscillator for phase ambiguity in a QPSK modulation scheme, which comprises the steps of transmitting a QPSK modulated plurality of reference pseudo random sequence generator (PRSG) sequence signals on a carrier signal, receiving the transmitted plurality of QPSK modulated reference PRSG sequence signals at a receiver and demodulating the received plurality of QPSK modulated reference PRSG sequence signals to recover the plurality of reference PRSG signals and inputting a first set of the plurality of reference PRSG sequence signals to a PRSG in the receiver. The method then proceeds with the steps of comparing an output of the PRSG in the receiver with a second set of received and demodulated plurality of reference PRSG sequence signals, and obtaining a corrected version of received and demodulated plurality of reference PRSG sequence signals based on the comparison of the output of the PRSG in the receiver with the second set of received and demodulated plurality of reference PRSG sequence signals.

[0012] Additionally, the present invention relates to a system for correcting a receiver local oscillator for phase ambiguity in a QPSK modulation scheme, the system comprising a transmitter for transmitting a QPSK modulated plurality of reference PRSG sequence signals on a carrier signal, the transmitter comprising at least a first reference PSRG, and a receiver capable of receiving the transmitted QPSK modulated reference PRSG sequence signal and determining the correct phase state. The first reference PRSG comprises at least a demodulator, a phase correction circuit, and a phase determination circuit, which further comprises at least a plurality of comparators, a phase state selection circuit, and a second reference PRSG.

Brief Description of the Drawings

[0013] The invention, as well as other features and advantages thereof, will be best understood by reference to the detailed description of the preferred embodiment which follows, when read in conjunction with the accompanying drawings, in which:

[0014] Fig. 1 illustrates four modulated phase states of an RF carrier in a QPSK modulation scheme;

[0015] Fig. 2 illustrates a block diagram of a front end of a prior art QPSK receiver;

[0016] Fig. 3 illustrates the relationship between the phase of the carrier signal and the phase of a LO signal in a QPSK receiver, in two different locked in-phase scenarios;

[0017] Fig. 4 illustrates a block diagram of a QPSK receiver according to an embodiment of the invention; [0018] . Fig. 5 illustrates a block diagram of a QPSK transmitter according to an embodiment of the invention; and

[0019] Fig. 6 illustrates a flow diagram of a method for an exemplary embodiment of the invention.

Detailed Description of the Preferred Embodiment

[0020] The various features of the preferred embodiment will now be described with reference to the figures, in which like parts are identified with the same reference numbers.

[0021] Fig. 4 illustrates a block diagram of a QPSK receiver according to an embodiment of the invention. The QPSK receiver of Fig. 4 comprises a quadrature demodulator 404, a phase correction circuit 420, and a phase determination circuit 480. The quadrature demodulator 404 receives the QPSK modulated input signal 402 into a first mixer 406 and a second mixer 408. Local oscillator (LO) 412 outputs LO signal 413, which is multiplied directly with input signal 402 in second mixer 408, and indirectly with input signal 402 in first mixer 406. "Indirectly" means that LO signal 413 is shifted by 90° after passing through phase shifter 410 before being multiplied with input signal 402 in second mixer 408. The carrier recovery circuit 414 locks to carrier of signal 402 through the action of a Phase Lock Loop contained within it recovers the I bit and Q bit of each QPSK symbol (i.e. the information transported by the QPSK modulated carrier signal 402). The action of the Phase Lock Loop in 414 aligns the LO signal 413 such that it is phase locked with the carrier of signal 402, and the phase shift between carrier signal 402 (of input signal 402) and LO signal 413 is, ideally, 0°. Operation of the quadrature demodulator 404 was discussed previously in connection with Fig. 2, and will not be repeated here in detail. However, the outputs of quadrature demodulator 404 are an in-phase received demodulated signal (I signal) 416 and a quadrature phase demodulated received signal (Q signal) 418. These are output to phase correction circuit 420, and also to I and Q signal demultiplexer 434, located in phase determination circuit 480, which will be discussed in detail below. [0022] , Phase correction circuit 420 receives as inputs I signal 416 and Q signal 418, and these are wired to generate outputs corresponding to phase shift corrections of 0°, 90°, 180°, and 270° relative to the phase represented by the quadrature demodulator 404 output. These are available on a first phase corrector tap 426, second phase corrector tap 428, third phase corrector tap 430 and fourth phase corrector tap 432, respectively. The phase correction taps (426, 428, 430, and 432) symbolically represent the first, second, third, and fourth inputs, respectively, of corrected IQ selector (selector) 460, whose output is corrected I & Q signal 492. Selector 460 is controlled by phase state selection circuit 488. The operation of phase state selection circuit 488 will be discussed in greater detail below.

[0023] If the phase of LO signal generator 412 and the phase of the carrier signal 402 phase are in-phase relative to one another, then no phase correction is needed and the output from the 0° phase corrector tap, which corresponds to first phase corrector tap 426, is the correct one to use. However, if the difference between the phase of LO signal 413 and the carrier signal 402 phase is one of the other values (i.e., 90°, 180° and 270°) then the correct output must come from one of the other phase corrector taps: second phase corrector tap 428 (90° phase shift), third phase corrector tap 330 (180° phase shift) or fourth phase corrector tap 332 (270° phase shift). For example, if the carrier phase is shifted 270° relative to the LO then a 90° phase correction is needed and the corrected output should come from the 270° phase correction tap, or the fourth phase correction tap 432. The determination of which phase correction tap to use is controlled by phase determination circuit 480.

[0024] Phase determination circuit 480 comprises a reference PRSG 486, a first comparator 482, second comparator 484, a phase state selection circuit 488 and a demultiplexer 434. Reference PRSG 486 creates a sequence of random bits of a length controlled by the design of the generator. The sequence repeats with a period equal to the sequence length. Reference PSRG 486 belongs to a class of pseudo random sequence generators that have important seed properties. [0025] It is well known in the art that a PRSG's output is not truly "random" in the sense that if two items are known about the sequence, it can be predicted: The first is the formula used to create the sequence, and the second is the seed value. A "seed value" is that group of numbers used by the PRSG formula to generate the sequence of values output by the PRSG. This is the reason "pseudo" is part of the name of a PRSG. The output of a well-designed PRSG is, otherwise, indistinguishable from a truly random sequence of values. [0026] If a contiguous sample of the PRSGs output sequence of random bits, equal in size to the polynomial order of the PRSG, is entered into the generator's stages (or another similar generator), it will reset the PRSG output sequence to thereafter be the same as that from which the sample was taken. [0027] By way of example, suppose a first PRSG outputs the following bits:

Table 1

[0028] The first row of Table 1 represents the sequence values, and the second row represents the bit number (or position of the value in the sequence). The stream of bits output from a PSRG can, of course, be of infinite length. Table 1 above is meant to show a sampling of 15 contiguous bits. The 15 bits could be any 15 bits in the output bit stream. In this example, the PRSG has a polynomial order of 4. Therefore, if bits 5-8 are input as seed bits into a second PRSG of exactly the same type, with the same polynomial order, the output of the second PSRG will begin with those bits that follow the "seed" bits, bits 5-8, as shown in Table 1 above. For example, the "seed" bits are bits 5-8, or 1000, and the second PRSG will then output, as the beginning of its output bit stream, 1011101 (which are bits 9-15). [0029] This seed property is used in phase determination circuit 480 to synchronize the receiver's PRSG output sequence with the one carried in input signal 402 to quadrature demodulator 404. After quadrature demodulator 404 has demodulated the received signal and outputs I signal 416 and Q signal 418, these are input to demultiplexer 434, which is part of phase determination circuit 480. Demultiplexer circuit 434 demultiplexes output I signal 416 and output Q signal 418 to produce a parallel stream of data, input seed data 490, that is at least as wide as the polynomial order of reference PRSG 486 (for example, if the polynomial order was 4, 490 would be 4 bits wide). Reference PRSG 486 uses the input seed data 490 to output a stream of data that is identical to that which is being generated by a first PRSG, which is located in QPSK transmitter 500, discussed with respect to Fig. 5) and being transmitted as the I and Q bit values.

[0030] The output of reference PRSG 486 is multiplexed into two bit streams, Q bit stream 487, and I bit stream 489, which are supplied as inputs to a first comparator 482 and a second comparator 484, respectively. This comparison reveals what value of phase difference exists between the carrier signal applied at the input to quadrature demodulator 404 and LO signal 413. If there is a difference other than 0° between the received signal's carrier phase and that of LO signal 413, the comparator outputs will identify that phase difference. Table 2 gives the relation of the comparator outputs to the phase correction:

Table 2

[0031] The outputs of first comparator 482 and second comparator 484 are input to phase state selection circuit 488, which uses the outputs of first comparator 482 and second comparator 484, according to Table 2, above, to chose the proper phase correction tap which will correct the phase offset between carrier signal 302 of input signal 402 and LO signal 413. Phase state selection circuit 488 selects the phase correction tap that causes the phase of carrier signal and phase of the LO signal 413 to differ by 0°. This correction is made for every two-bit symbol of the PRS sequence. Averaging over a multiple of symbols may be used to eliminate false alarms. [0032] , Table 3 shows, by way of example, a phase correction made when two incidents occur during the transmission of signals requiring phase correction.

Table 3

[0033] The phase corrections are created by a combination of "true" I and Q signals 416, 418, and "inverted" I and Q signals 423, 425, respectively. Phase correction tap 426 (0° phase correction) takes, as its input, "true" values of both I signal 416 and Q signal 418. That is, in order to "correct" the data because of the phase shift (of 0°), no inverted signals have to be used. Obviously, in this instance, no correction is needed, so no inverted signals are used, and the original I and Q signals (416 and 418 respectively) are passed through the 0° phase correction tap 426. [0034] . If, however, phase correction tap 432 is chosen (270° phase correction), as in case of the example shown in line 3 of Table 3 above, inverted I signal 425 must be used, because it was received incorrectly, as decided in I comparator 484. 1 signal 416 should have been received as a "-1", and instead was received as a "1". Referring to Fig. 1, the signal transmitted was analog vector 106 (-1, -1), and the received signal (1, -1) is analog vector 108. 1 signal 416 needs to be corrected and therefore phase correction tap 432, which uses inverted I signal 423 and "true" Q signal 418 was selected. Phase correction taps 428 and 430 operate and would be used in a similar fashion.

[0035] Fig. 5 illustrates a block diagram of a QPSK transmitter according to an embodiment of the invention. The system and method of the preferred embodiment require transport of a reference PRSG sequence in the signal delivered by input signal 402 to quadrature demodulator 404. First PRSG 502 at the signal transmitter, is identical to the reference PRSG 486, located in phase determination circuit 480. First PRSG 502 generates the PRSG reference sequence as does reference PRSG 486. The PRSG sequence signal is carried in one of the channels transported by the input signal. In practical applications only a small fraction (e.g., 1/96) of the total channel capacity transported via the input signal is used for the PRSG sequence signal, the remaining capacity being used for data.

[0036] The output of PRSG 502 is input to both the I and Q inputs of QPSK modulator 506. The carrier input of the QPSK modulator 506 is connected to the output of LO generator 504. The output of QPSK modulator 506 is connected to 508, which represents up conversion from baseband-to-IF-to-RF frequency signals, amplification and RF selection of the 1 of 96 channels to satellite transmitter dish 510. The PRSG output signal is transported in one of 96 time domain slots in a TDM (Time Division Multiplexed) stream. It is essential that the PRSG time slots and individual information channel time slots be organized to spread the PRSG symbols and information symbols uniformly over the entire duration of each TDM frame. The signal transmitted from transmitter satellite 510 is broadcast to a satellite (not shown), which receives the signal, and re-broadcasts it to a similar receiver satellite dish located adjacent to the receiver 400, and the signal then becomes input signal 402 (after being received and down converted, the details of which are well known to those skilled in the art).

[0037] Fig. 5 shows the composite PRSG and Information Channel signal originating at a ground station and being repeated by transparent transponder on a satellite. However, in satellites having onboard baseband processing, the TDM PRSG and information streams may be generated onboard the satellite. This is the case on the WorldSpace digital audio broadcast satellites, which are now in orbit. [0038] Fig. 6 illustrates a flow diagram of a method for an exemplary embodiment of the invention. The method begins with step 602, in which a plurality of reference PRSG sequence signals, using QPSK modulation, are transmitted by transmitter 500 to QPSK receiver 400. Both QPSK transmitter 500 and QPSK receiver 400 contain the exact same PRSG, of the same polynomial order. In step 604, the QPSK receiver 400 receives the QPSK modulated plurality of reference PRSG sequence signals on a carrier signal. The plurality of reference pseudo reference sequence generator (PRSG) sequence signals are then demodulated in quadrature demodulator 404, creating I signal 416 and Q signal 418.

[0039] hi step 606, 1 and Q signal (416 and 418 respectively) are de-multiplexed in de-multiplexer 434, and then a first set of the reference PRSQ sequence signals are input to the reference PRSG 486. The first set are the "seed bits" that will generate a sequence of values from reference PRSG 486 that is identical to those sequence values that are currently being transmitted by the transmitter and received in the receiver 400. The number of "seed bits" must be the same as the polynomial order of reference PRSG 486, and the PSRG used in the generator (because they are identical). After the seed bits are input to reference PRSG 486, it will start creating a sequence of pseudo random bit values that is identical to those sequence bit values being transmitted from the transmitter.

[0040] In step 608 first comparator 482 and second comparator 484 compare the de-multiplexed output of reference PRSG 486 with Q signal 418 and I signal 416 respectively. In an ideal situation there will be no phase shift between LO signal 413 and carrier 302 and the signals input to the first comparator 482 and second comparator 484 will be identical. In that case, no adjustment is necessary in the received signals, and first comparator 482 and second comparator 484 cause phase state selection circuit 488 to choose phase correction tap 426, which indicates 0° phase shift.

[0041] However, in step 610, if first comparator 482 and second comparator 484 outputs indicate that received I signal 416 and received Q signal 418 are not the same as was generated by reference PRSG 486, then a different phase correction tap will be chosen, based on the phase shift discerned by the comparator's output. Thus, receiver 400, in using reference PRSG 486 and phase state selection circuit 488, is able to compensate for phase shifts up to 270° between carrier 302 and LO signal 413. [0042] The system and method of the invention is not limited to QPSK modulation schemes alone. For example, it is possible to insert identical pseudo random sequence generators in both the transmitter and receiver of a communications system that utilizes octal phase shift keying. The principle of the invention would remain the same, except that the possible phase shifting that could occur would, of course, be different.

[0043] The embodiment described above is merely given as an example and it should be understood that the invention is not limited thereto. It is of course possible to embody the invention in specific forms other than that described without departing from the spirit of the invention. Further modifications and improvements, which retain the basic underlying principles disclosed and claimed herein, are within the spirit and scope of this invention.

Claims

WHAT IS CLAIMED IS;

1. A method for correcting phase ambiguity in a quadrature phase shift keying (QPSK) receiver local oscillator comprising: transmitting a QPSK modulated first plurality of reference pseudo random sequence generator (PRSG) sequence signals on a carrier signal; receiving and demodulating the transmitted QPSK modulated first plurality of reference PRSG sequence signals at a receiver to recover the transmitted first plurality of reference PRSG sequence signals; and, correcting the receiver's symbol information phase reference to 0° relative to the received carrier phase using the recovered first plurality of reference PRSG sequence signals.

2. The method of claim 1 , wherein the step of correcting the receiver's symbol information phase reference to 0° relative to the received carrier phase comprises: inputting the recovered first plurality of reference PRSG sequence signals into a correcting means; and, correcting the receiver's symbol information phase reference to 0° relative to the received carrier phase according to an output of the correcting means.

3. The method of claim 2, wherein the step of correcting the receiver's symbol information phase reference to 0° relative to the received carrier phase according to an output of the correcting means comprises: generating a second plurality of reference PRSG sequence signals from a receiver PRSG based on the recovered first plurality of reference PRSG sequence signals; comparing the recovered first plurality of reference PRSG sequence signals with the second plurality of PRSG sequence signals; and correcting the receiver's symbol information phase reference to 0° relative to the received carrier phase according to an output of the correcting means on the results of the comparison between the recovered first plurality of reference PRSG sequence signals and second plurality of reference PRSG sequence signals.

4. The method of claim 3, wherein the step of correcting the receiver's symbol information phase reference to 0° relative to the received carrier phase according to an output of the correcting means based on the results of the comparison between the recovered first plurality of reference PRSG sequence signals and second plurality of reference PRSG sequence signals, comprises: choosing a first phase offset if the comparison is a first value; choosing a second phase offset if the comparison is a second value choosing a third phase offset if the comparison is a third value; and choosing a fourth offset if the comparison is a fourth value.

5. The method of claim 3 , wherein the recovered first plurality of reference PRSG signals comprises a first plurality of I value signals and a first plurality of Q value signals, and the second plurality of reference PRSG signals comprises a second plurality of I value signal and a second plurality of Q value signals.

6. The method of claim 5, wherein the step of comparing the recovered first plurality of reference PRSG sequence signals with the second plurality of PRSG sequence signals, comprises: comparing a first plurality of I signals with a second plurality of I signals, and comparing a first plurality of Q signals with a second plurality of Q signals.

7. The method according to claim 6, wherein the first value is the first comparator having a true output and the second comparator having a true output.

8. The method according to claim 6, wherein the second value is the first comparator having a true output and the second comparator having a false output.

9. The method according to claim 6, wherein the third value is the first comparator having a false output and the second comparator having a false output.

10. The method according to claim 6, wherein the fourth value is the first comparator having a false output and the second comparator having a true output.

11. A method for correcting phase ambiguity in a QPSK receiver local oscillator comprising: transmitting a QPSK modulated first plurality of reference PRSG sequence signals on a carrier signal; receiving the transmitted QPSK modulated first plurality of reference PRSG sequence signals at a receiver; demodulating the received QPSK modulated first plurality of reference PRSG sequence signals to recover a plurality of received reference PRSG signals; inputting a first set from the plurality of reference PRSG sequence signals to a receiver PRSG; generating a plurality of receiver PRSG sequence signals; comparing the plurality of receiver PRSG sequence signals to a second set from the plurality of received reference PRSG sequence signals; and correcting the receiver's symbol information phase reference to 0° relative to the received carrier phase according to an output of the correcting means based on the compared plurality of receiver PRSG sequence signals and the second set of received reference PRSG sequence signals.

12. A system for correcting phase ambiguity in a QPSK receiver local oscillator comprising: a transmitter for transmitting a QPSK modulated plurality of reference PRSG sequence signals, the transmitter comprising at least a reference PSRG; and a receiver for receiving the transmitted QPSK modulated reference PRSG sequence signals, comprising: a demodulator for demodulating the QPSK modulated plurality of reference PRSG .sequence signals, and outputting a received I channel signal and a received Q channel signal; and means for correcting the local oscillator of phase ambiguity by adjusting the receiver's symbol information phase reference to 0° relative to the received carrier phase according to an output of the correcting means.

13. The system according to claim 12, wherein the means for correcting the receiver's symbol information phase reference to 0° relative to the received carrier phase according to an output of the correcting means, thereby correcting the receiver's local oscillator of phase ambiguity, comprises: a phase correction circuit; and, a phase determination circuit.

14. The system according to claim 13, wherein the phase correction circuit comprises: a received I channel signal input; a received Q channel signal input; and means for outputting corrected I and Q channel signals.

15. The system according to claim 14, wherein the means for outputting corrected I and Q channel signals, comprises: an I channel inverter, with an input connected to the received I channel signal and outputting an inverted received I channel signal; a Q channel inverter, with an input connected to the received Q channel signal and outputting an inverted received Q channel signal; a first phase tap, connected to the received I channel signal and the received Q channel signal; a second phase tap, connected to the received I channel signal and the inverted received Q channel signal, a third phase tap, connected to the inverted received I channel signal and inverted received Q channel signal; fourth phase tap, connected to the inverted received I channel signal and received Q channel signal; and an IQ signal selector.

16. The system according to claim 13, wherein the phase determination circuit comprises: a demultiplexer, connected to a receiver PRSG; a first comparator, connected to a receiver PRSG I signal output; a second comparator, connected to a receiver PRSG Q channel output; and a phase state selection circuit, connected to an output of the first comparator and output of the second comparator.

17. The system according to claim 16, wherein the phase determination circuit further comprises: the first comparator connected to the received I channel signal; the second comparator connected to the received Q channel signal; an output of the phase state selection circuit connected to the IQ signal selector, for choosing a corrected I channel signal and corrected Q channel signal based on the comparison between the received I channel signal and receiver PRSG I signal output, and the comparison between the received Q channel signal and the receiver PRSG Q channel signal output.

18. The system according to claim 12, wherein the reference PRSG and receiver PRSG is of the same type and polynomial order.

19. A method for correcting phase ambiguity in a octal phase shift keying (OPSK) receiver local oscillator comprising: transmitting an OPSK modulated first plurality of reference pseudo random sequence generator (PRSG) sequence signals on a carrier signal; receiving and demodulating the transmitted OPSK modulated first plurality of reference PRSG sequence signals at a receiver to recover the transmitted first plurality of reference PRSG sequence signals; and, correcting the receiver's symbol information phase reference to 0° relative to the received carrier phase according to an output of the correcting means using the recovered first plurality of reference PRSG sequence signals.

20. A method for correcting phase ambiguity in an OPSK receiver local oscillator comprising: transmitting a OPSK modulated first plurality of reference PRSG sequence signals on a carrier signal; receiving the transmitted OPSK modulated first plurality of reference PRSG sequence signals at a receiver; demodulating the received OPSK modulated first plurality of reference PRSG sequence signals to recover a plurality of received reference PRSG signals; inputting a first set from the plurality of reference PRSG sequence signals to a receiver PRSG; generating a plurality of receiver PRSG sequence signals; comparing the plurality of receiver PRSG sequence signals to a second set from the plurality of received reference PRSG sequence signals; and correcting the receiver's symbol information phase reference to 0° relative to the received carrier phase according to an output of the correcting means based on the compared plurality of receiver PRSG sequence signals and the second set of received reference PRSG sequence signals.

21. A system for correcting phase ambiguity in a OPSK receiver local oscillator comprising: a transmitter for transmitting a OPSK modulated plurality of reference PRSG sequence signals, the transmitter comprising at least a reference PSRG; and a receiver for receiving the transmitted OPSK modulated reference PRSG sequence signals, comprising: a demodulator for demodulating the OPSK modulated plurality of reference PRSG sequence signals, and outputting a received I channel signal and a received ,Q channel signal; and means for correcting the local oscillator of phase ambiguity by correcting the receiver's symbol information phase reference to 0° relative to the received carrier phase according to an output of the correcting means.