WO2003023856A3 - Semiconductor structures with cavities, and methods of fabrication - Google Patents

Semiconductor structures with cavities, and methods of fabrication Download PDF

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Publication number
WO2003023856A3
WO2003023856A3 PCT/US2002/028862 US0228862W WO03023856A3 WO 2003023856 A3 WO2003023856 A3 WO 2003023856A3 US 0228862 W US0228862 W US 0228862W WO 03023856 A3 WO03023856 A3 WO 03023856A3
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WIPO (PCT)
Prior art keywords
cavity
substrate
cavities
fabrication
methods
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Application number
PCT/US2002/028862
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French (fr)
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WO2003023856A2 (en
Inventor
Patrick B Halahan
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Tru Si Technologies Inc
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Publication date
Application filed by Tru Si Technologies Inc filed Critical Tru Si Technologies Inc
Publication of WO2003023856A2 publication Critical patent/WO2003023856A2/en
Publication of WO2003023856A3 publication Critical patent/WO2003023856A3/en

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    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
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Abstract

Semiconductor dies (102) are bonded to contact pads (130C) formed in a substrate's cavity (120). Vias through the substrate (110) open into the cavity. Conductive lines (130CF) passing through the vias connect the contact pads in the cavity to contact pads on another side of the substrate. A passage (194) in the substrate opens into the cavity and provides an escape or pressure relief path for material filling the cavity. The passage can also be used to introduce material into the cavity.
PCT/US2002/028862 2001-09-13 2002-09-10 Semiconductor structures with cavities, and methods of fabrication WO2003023856A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/952,263 US6787916B2 (en) 2001-09-13 2001-09-13 Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity
US09/952,263 2001-09-13

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WO2003023856A2 WO2003023856A2 (en) 2003-03-20
WO2003023856A3 true WO2003023856A3 (en) 2004-02-12

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PCT/US2002/028862 WO2003023856A2 (en) 2001-09-13 2002-09-10 Semiconductor structures with cavities, and methods of fabrication

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JP3813079B2 (en) * 2001-10-11 2006-08-23 沖電気工業株式会社 Chip size package
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