WO2003017366A1 - Method for forming a flip chip on leadframe semiconductor package - Google Patents

Method for forming a flip chip on leadframe semiconductor package Download PDF

Info

Publication number
WO2003017366A1
WO2003017366A1 PCT/SG2002/000189 SG0200189W WO03017366A1 WO 2003017366 A1 WO2003017366 A1 WO 2003017366A1 SG 0200189 W SG0200189 W SG 0200189W WO 03017366 A1 WO03017366 A1 WO 03017366A1
Authority
WO
WIPO (PCT)
Prior art keywords
reflowable
accordance
solder
conductive material
leadframe
Prior art date
Application number
PCT/SG2002/000189
Other languages
French (fr)
Inventor
Hwee Seng Jimmy Chew
Kim Hwee Tan
Original Assignee
Advanpack Solutions Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=25464823&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO2003017366(A1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Advanpack Solutions Pte Ltd filed Critical Advanpack Solutions Pte Ltd
Publication of WO2003017366A1 publication Critical patent/WO2003017366A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1357—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/8101—Cleaning the bump connector, e.g. oxide removal step, desmearing
    • H01L2224/81011—Chemical cleaning, e.g. etching, flux
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to forming a flip chip semiconductor package on a leadframe, and more particularly to forming a flip chip semiconductor package with a bumped semiconductor die on a leadframe.
  • Packaging In semiconductor packaging, a relatively sensitive and difficult to handle semiconductor die is encapsulated in a package with external connections. Packaging allows the semiconductor die to be more conveniently handled, and it also allows external circuitry to be easily coupled thereto.
  • a known method of forming a flip chip on leadframe (FCOL) semiconductor package employs a plated leadframe.
  • a leadframe is a patterned sheet of metal, typically copper, that has been plated, usually with silver, nickel or palladium. Conventionally, a leadframe is plated to prevent the copper from oxidizing, and to provide a surface to which solder will adhere.
  • the pattern of the sheet of metal provides a leadframe for forming a semiconductor package.
  • leadframes for forming FCOL semiconductor packages have leads with inner lead portions and outer lead portions. The inner lead portions are arranged in a pattern with interconnect locations on the inner lead portions matching the pattern of pads on a semiconductor die. During the packaging process, typically eutectic solder is deposited on the interconnect locations. In addition, the pads on the semiconductor die are bumped. Bumping can comprise metal posts extending from the pads of the semiconductor die with solder balls on free ends of the metal posts. Typically, the solder balls are made of high lead solder.
  • solder balls on the die, and the semiconductor die is flipped over, and placed on the leadframe, with the solder balls abutting the solder paste deposits on the interconnect locations.
  • the assembly is then reflowed using an appropriate reflow profile.
  • the solder paste deposits melt, and with the assistance of the flux, the eutectic solder adheres to the interconnect locations on the leadframe and the high lead solder balls on the copper posts, thus forming solder interconnects between the high lead solder balls on the free ends of the metal posts and the interconnect locations on the leadframe.
  • the assembly is cleaned to remove residual flux and encapsulated in mold compound. However, when no-clean flux is employed, the cleaning step is not necessarily required.
  • the resultant package is known as a FCOL semiconductor package.
  • a disadvantage of this process is, when the solder paste melts, the molten solder tends to flows across the surface of the lead portions. This flow of solder is often referred to as overrun, and results in a variety of adverse effects in FCOL semiconductor packages.
  • a first concern is, when the solder flows away from an interconnect location, the respective solder interconnect constitutes less solder than required to provide a reliable electrical connection between the solder balls and the interconnect locations.
  • a second concern is, solder interconnects formed with the reduced amount of solder do not support the semiconductor die evenly on the leadframe. Consequently, the planarity of the semiconductor die on the leadframe is adversely affected, and a non-planar die can give rise to shorting between the metal posts on the die. This condition is sometimes referred to as a collapsed die.
  • a third concern is the overrun results in solder flowing over the edges and onto the opposite surface of the lead portions. Later, during molding mold compound will not adhere well to the affected surfaces.
  • a fourth concern is wicking, which occurs when a lead portion on a leadframe is shaped such that there is a small gap between the side of a downset die and the lead portion, and where there is an interconnect location close to the edge of the die. In this arrangement, the solder from the interconnect location can flow along the lead portion and, through capillary action, flow upwards through the small gap.
  • eutectic solder paste is disposed on the interconnect locations using a printing process.
  • This process of dispensing solder is known to suffer wide process variations. Consequently, the amount of solder paste dispensed on a leadframe can vary considerably. Such variations in the amount of solder paste dispensed for a particular semiconductor package leads to variations in the resultant solder joints, adversely affecting the reliability of the semiconductor package.
  • un-plated or bare copper leadframes simply referred to as copper leadframes, have been tried.
  • the copper leadframes suffer the same disadvantages discussed hereinabove as the plated leadframe, and in some instances to a greater degree.
  • the present invention seeks to provide a method for forming a flip chip on leadframe semiconductor package, which overcomes or at least reduces the abovementioned problems of the prior art.
  • the present invention provides a method for forming a flip chip semiconductor package, the method comprising the steps of: a) providing a patterned layer of metal conductors having a first surface for providing a pattern of interconnect locations thereon; b) providing a semiconductor die having a first surface with a corresponding pattern of pads thereon, the pads having non-reflowable material thereon; c) disposing a predetermined amount of reflowable conductive material on the non-reflowable material; d) placing the semiconductor die on the patterned layer of metal conductors, wherein the reflowable conductive material abuts the interconnect locations; and e) reflowing the reflowable conductive material, wherein a substantial portion of the reflowable conductive material remains substantially at the interconnect locations to form conductive interconnects between the non-reflowable material and the interconnect locations.
  • the present invention provides a method for determining the amount of reflowable material to be disposed on non- reflowable bumps on a semiconductor die to mount the semiconductor die on a leadframe having interconnect locations thereon, the method comprising the steps of: a) determining surface area of one of the non-reflowable bumps; b) defining a corresponding interconnect location on the leadframe having substantially the same area as the surface area of the one of the non-reflowable bumps; and c) selecting an amount of reflowable material such that a substantial portion of the selected amount of reflowable material remains at the interconnect location during reflow.
  • FIG. 1 shows a top view of a part of a leadframe
  • FIG. 2 shows a flowchart detailing a process for forming a FCOL semiconductor package with a semiconductor die and a leadframe
  • FIGS. 3A-D shows cross-sectional views of a part of the leadframe and the semiconductor die during the process in FIG. 1.
  • a predetermined amount of solder is deposited more uniformly on the free ends of copper posts extending from die pads of a semiconductor die.
  • the solder deposits are coated with flux and the semiconductor die is then placed on a leadframe with the solder deposits abutting interconnect locations on inner lead portions of the leadframe.
  • the solder deposits melt and with the assistance of the flux forms solder interconnects between the free ends of the copper posts and the interconnect locations. Due to the predetermined amount of solder deposited on the free ends of the copper posts more uniformly, the molten solder tends not to flow away from the interconnect locations.
  • advantageously allowing a substantial portion of the solder to remain at the interconnect locations resulting in more uniform solder interconnects.
  • the assembly of the semiconductor die and the leadframe is encapsulated in mold compound with outer lead portions exposed and/or extending from the FCOL semiconductor package.
  • a non-leaded version of the resultant package is often referred to as the quad non- lead package (QFN).
  • FIG. 1 shows a part of a leadframe 100, which has inner lead portions 101, outer lead portions 102 and dam bar portions 103.
  • the outline 104 indicates the location for placing a flipped semiconductor die (not shown) on the leadframe 100.
  • a FCOL semiconductor package (not shown) is formed on the leadframe 100, the inner lead portions 101, which are coupled to the semiconductor die, will be enclosed with the semiconductor die in the FCOL semiconductor package, and the outer lead portions 102 will extend from the package.
  • the dam bar portions 103 define an outline of the FCOL package, and provide a seal during the molding process that encapsulates the semiconductor die and the inner lead portions 102 in the FCOL package.
  • the dam bar portions 103 and other excess portions of the lead frame 100 are removed during a subsequent trim and form operation after encapsulation or when the FCOL semiconductor package is singulated from the leadframe 100.
  • the leadframe 100 is supplied by a vendor in a strip on which several FCOL semiconductor packages can be formed, as is known in the art. More commonly, the leadframe comprises copper and is plated with silver, nickel or palladium, however, the present invention also extends to use with un-plated leadframes, such as bare copper leadframes.
  • the leadframe 100 is a patterned metal leadframe, which provides a patterned layer of metal conductors, and can comprise a stamping from a sheet of metal, such as copper. Alternatively, the leadframe 100 can be produced by etching a copper sheet. When the thickness of the metal is relatively small, the leadframe 100 can comprise flexible circuits, also known as flex circuits, which includes a flexible substrate. In addition, the leadframe 100, as referred to herein, extends to substrates including ceramic, laminate, polyimide substrate, and tape. With reference to FIG. 2 and FIGS. 3A-D a process 200 for forming a FCOL semiconductor package, in accordance with the present invention, starts 205 with providing 210 the copper leadframe 100.
  • FIGS. 3A-D To facilitate description, only a portion of the lead frame 100 and a portion of a semiconductor die 305 are shown in FIGS. 3A-D. However, it will be appreciated by one skilled in the art, that the process 200 as described applies to all copper posts 310 on the semiconductor die 305 and all the inner lead portions 101 of the leadframe 100 that form the FCOL semiconductor package.
  • the semiconductor die 305 is provided 215, where the semiconductor die 305 includes copper posts 310 extending from pads (not shown) on the semiconductor die 305 as shown in FIG. 3A.
  • a process for forming the copper posts 310 on the semiconductor die 305 when the die is part of a semiconductor wafer was alluded to earlier.
  • a variety of other wafer bumping techniques may be employed to form non-reflowable bumps on a wafer, and the constituent bumped semiconductor dies of such wafers can be used in accordance with the present invention to form FCOL semiconductor packages.
  • non-reflowable bumps include gold, indium, tin, lead-free tin bismuth, lead free tin-copper, lead free tin-silver, and the like.
  • FIG. 3A shows the inner lead portions 101 of two adjacent leads of the leadframe 100 where each of the inner lead portions 101 has an interconnect location 335 thereon.
  • An interconnect location herein is defined as the area on the inner lead portion 101 when the copper posts 310 are aligned with the inner lead portions 101 i.e. the area bounded by the circumference of the copper posts 310 when the copper posts are aligned with the inner lead portions 101, where the circumference of the copper posts are projected onto the inner lead portions 101.
  • the broken lines in FIGS. 3A and 3C define the interconnect locations 335 on the inner lead portions 101.
  • the pattern of interconnect locations 335 on the inner lead portions 101 corresponds to the pattern of copper posts 310 that extend from the semiconductor die 305 when the semiconductor die 315 is aligned with the inner lead portions 101.
  • reflowable conductive deposits 315 such as solder
  • solder is plated on or attached in the form of solder balls, on the free ends of the copper posts 310.
  • solder deposits 315 are disposed 220 on the free ends of the copper posts 310.
  • the solder deposits 315 can be disposed by a variety of techniques, as will be known to one skilled in the art. A reference cited earlier describes a process that disposes solder on the copper posts when the copper bumps are formed by electroplating.
  • the amount of solder disposed on the end of each of the copper posts 310 of the semiconductor die 305 is predetermined, and whatever process that is employed to dispose the solder, that process must ensure that the predetermined amount of solder is disposed on each of the copper post 310.
  • a plating process is used as the plating process has a lower process variation then that of the solder printing process. This allows the amount of solder disposed on the free ends of the copper posts to be better controlled and more uniform on a semiconductor die.
  • the amount of solder disposed is dependent on a variety of factors which can include: type of solder, dimensions of the copper post, material at the interconnect location, mass of the semiconductor die, number of copper posts, reflow profile when reflowing the solder deposits 315, the expected final dimensions of the reflowed solder and copper post, and the type of flux.
  • This measured amount of the solder advantageously allows a substantial portion of the disposed solder deposits 315 to remain at the interconnect locations 335 during reflow when the solder deposits 315 are in molten state.
  • Flux 320 is then applied or coated 225 on the solder deposits 315. This is often achieved by briefly positioning the semiconductor die 305 with the solder deposits 315 immersed in a reservoir of the flux 320. At elevated temperatures, the flux 320 cleans a surface to which it is applied to enhance the adhesion of the solder deposits 315. The cleaned surfaces include the surface of the solder deposit 315 and the interconnect locations 335. After the flux 320 is applied, the semiconductor die 305 is ready to be mounted on the leadframe 100.
  • the flux 320 can be printed or disposed on the interconnect locations 335, although this would require additional equipment relative to a single handler picking up the semiconductor die 305 with the solder, dipping the solder deposits 315 on the copper posts 310 in flux 320 and then placing the semiconductor die 305 on the leadframe 100.
  • the semiconductor die 305 is positioned above the leadframe 100 with the solder deposits 315 aligned with the interconnect locations 335 on the leadframe 100.
  • the semiconductor die 305 is then placed 230 on the leadframe 100.
  • the step of placing here can include exerting and maintaining a predetermined force on the semiconductor die 305 against the leadframe 100.
  • the lower surface of the solder deposits 315 abut the interconnect locations 335, and the flux 320 on the solder deposits 315 flows around the solder deposits 315 and on the interconnect locations 335.
  • the flux 320 on the solder deposits 315 wets or adheres to the interconnect locations 335 as shown in FIG. 3B, in preparation for the next step.
  • the assembly of the semiconductor die 305, the leadframe 100, and the flux 320, is then reflowed 235.
  • Reflowing processes will be known to one skilled in the art in relation to flip chip semiconductor packages, and no further detail is provided herein, except to the extent where such detail enhances the understanding of the present invention.
  • the flux 320 cleans the interconnect locations 335 on the leadframe 100, and the solder deposits 315 change to a molten state.
  • the molten solder flows onto the cleaned interconnect locations 335, and adheres thereto forming a solder interconnect 340 between each of the copper posts 310 and the corresponding interconnect locations 335, as shown in FIG. 3C.
  • the solder interconnect 340 is sometimes called a fillet.
  • the predetermined amount of solder 315 deposited determines the formation of the solder interconnect 340, thus ensuring a substantial portion of the solder 315 deposited remains at the interconnect location 335.
  • the present invention advantageously, reduces the flow of solder away from the interconnect locations, thus, improving the coupling between the copper posts and the leadframe formed by the resultant solder interconnects.
  • the assembly After reflowing 235, when normal flux is used, the assembly is cleaned to remove any access flux 320, and the assembly is encapsulated 245 in mold compound 345 as shown in FIG. 3D, to produce a flip chip semiconductor package (not shown) on the leadframe 100. Alternatively, when no-clean flux is employed, cleaning is not necessarily required. Subsequently, after a final step of singulating the FCOLF semiconductor package from the leadframe 100, during which the dam bar portions 103 are severed, the process 200 ends 245. As will be known to one skilled in the art, there may be the additional steps of forming the external lead portions 102, and testing the functionality of the semiconductor die 320, prior to singulation.
  • An example of a semiconductor package formed in accordance with the present invention comprises a semiconductor die with copper post having a pitch of 250 microns, where the copper post has a length of 70 microns and a diameter of 100 microns.
  • the solder plated on the free ends of the copper posts has a thickness of 30 microns, and the semiconductor die was mounted on a bare copper leadframe.
  • the present invention provides a method of forming a flip chip semiconductor package on a leadframe where a predetermined amount of solder disposed on the copper posts on a semiconductor die tends to remain at interconnect locations on the leadframe.
  • the present invention provides a method for forming a flip chip on leadframe semiconductor package, which overcomes or at least reduces the abovementioned problems of the prior art.

Abstract

A predetem1ined amount of solder (315) is deposited on the free ends of copper posts (310) extending from die pads of a semiconductor die (305). The solder (315) is coated with flux (320) and the semiconductor die (305) is placed on a leadframe ( lOO) with the solder deposits (315) abutting interconnect locations (335) on inner lead portions (101). When reflowed, the solder deposits (315) melt and with the assistance of the flux (320) fom1s solder interconnects between the free ends of the copper posts (310) and the interconnect locations (335). Due to the predetem1ined amount of solder (315) deposited on the free ends of the copper posts (310), the molten solder (315) tends not to flow away from the interconnect location (335). Thus, advantageously allowing a substantial portion of the solder deposit (315) to remain at the interconnect locations (335) to fom1 solder interconnects.

Description

METHOD FOR FORMING A FLIP CHIP ON LEADFRAME SEMICONDUCTOR PACKAGE
Field of the Invention
The present invention relates to forming a flip chip semiconductor package on a leadframe, and more particularly to forming a flip chip semiconductor package with a bumped semiconductor die on a leadframe.
Background of the Invention
In semiconductor packaging, a relatively sensitive and difficult to handle semiconductor die is encapsulated in a package with external connections. Packaging allows the semiconductor die to be more conveniently handled, and it also allows external circuitry to be easily coupled thereto.
A known method of forming a flip chip on leadframe (FCOL) semiconductor package employs a plated leadframe. A leadframe is a patterned sheet of metal, typically copper, that has been plated, usually with silver, nickel or palladium. Conventionally, a leadframe is plated to prevent the copper from oxidizing, and to provide a surface to which solder will adhere. The pattern of the sheet of metal provides a leadframe for forming a semiconductor package. Currently, leadframes for forming FCOL semiconductor packages have leads with inner lead portions and outer lead portions. The inner lead portions are arranged in a pattern with interconnect locations on the inner lead portions matching the pattern of pads on a semiconductor die. During the packaging process, typically eutectic solder is deposited on the interconnect locations. In addition, the pads on the semiconductor die are bumped. Bumping can comprise metal posts extending from the pads of the semiconductor die with solder balls on free ends of the metal posts. Typically, the solder balls are made of high lead solder.
US patent application Serial No. 09/564,382 by Francisca Tung, filed on April 27, 2000, titled "Improved Pillar Connections For Semiconductor Chip", and Continuation-In-Part US patent application Serial No. 09/843,248 by Francisca Tung, filed on April 27, 2001 titled "Pillar Connections For Semiconductor Chips and Method Of Manufacture", and assigned to a common assignee as this patent application, teaches forming pillar bump structures as described herein. These patent applications are incorporated herein by reference thereto.
Subsequently, the solder balls on the die, and the semiconductor die is flipped over, and placed on the leadframe, with the solder balls abutting the solder paste deposits on the interconnect locations. The assembly is then reflowed using an appropriate reflow profile.
Under the elevated reflow temperatures, the solder paste deposits melt, and with the assistance of the flux, the eutectic solder adheres to the interconnect locations on the leadframe and the high lead solder balls on the copper posts, thus forming solder interconnects between the high lead solder balls on the free ends of the metal posts and the interconnect locations on the leadframe. After reflow, when normal flux is used the assembly is cleaned to remove residual flux and encapsulated in mold compound. However, when no-clean flux is employed, the cleaning step is not necessarily required. The resultant package is known as a FCOL semiconductor package.
A disadvantage of this process is, when the solder paste melts, the molten solder tends to flows across the surface of the lead portions. This flow of solder is often referred to as overrun, and results in a variety of adverse effects in FCOL semiconductor packages. A first concern is, when the solder flows away from an interconnect location, the respective solder interconnect constitutes less solder than required to provide a reliable electrical connection between the solder balls and the interconnect locations. A second concern is, solder interconnects formed with the reduced amount of solder do not support the semiconductor die evenly on the leadframe. Consequently, the planarity of the semiconductor die on the leadframe is adversely affected, and a non-planar die can give rise to shorting between the metal posts on the die. This condition is sometimes referred to as a collapsed die.
A third concern is the overrun results in solder flowing over the edges and onto the opposite surface of the lead portions. Later, during molding mold compound will not adhere well to the affected surfaces. A fourth concern is wicking, which occurs when a lead portion on a leadframe is shaped such that there is a small gap between the side of a downset die and the lead portion, and where there is an interconnect location close to the edge of the die. In this arrangement, the solder from the interconnect location can flow along the lead portion and, through capillary action, flow upwards through the small gap.
Further, eutectic solder paste is disposed on the interconnect locations using a printing process. This process of dispensing solder is known to suffer wide process variations. Consequently, the amount of solder paste dispensed on a leadframe can vary considerably. Such variations in the amount of solder paste dispensed for a particular semiconductor package leads to variations in the resultant solder joints, adversely affecting the reliability of the semiconductor package. In an effort to reduce costs of producing FCOL semiconductor packages, un-plated or bare copper leadframes, simply referred to as copper leadframes, have been tried. However, to a large extent, the copper leadframes suffer the same disadvantages discussed hereinabove as the plated leadframe, and in some instances to a greater degree. Brief Summary of the Invention
The present invention seeks to provide a method for forming a flip chip on leadframe semiconductor package, which overcomes or at least reduces the abovementioned problems of the prior art.
Accordingly, in one aspect, the present invention provides a method for forming a flip chip semiconductor package, the method comprising the steps of: a) providing a patterned layer of metal conductors having a first surface for providing a pattern of interconnect locations thereon; b) providing a semiconductor die having a first surface with a corresponding pattern of pads thereon, the pads having non-reflowable material thereon; c) disposing a predetermined amount of reflowable conductive material on the non-reflowable material; d) placing the semiconductor die on the patterned layer of metal conductors, wherein the reflowable conductive material abuts the interconnect locations; and e) reflowing the reflowable conductive material, wherein a substantial portion of the reflowable conductive material remains substantially at the interconnect locations to form conductive interconnects between the non-reflowable material and the interconnect locations.
In another aspect the present invention provides a method for determining the amount of reflowable material to be disposed on non- reflowable bumps on a semiconductor die to mount the semiconductor die on a leadframe having interconnect locations thereon, the method comprising the steps of: a) determining surface area of one of the non-reflowable bumps; b) defining a corresponding interconnect location on the leadframe having substantially the same area as the surface area of the one of the non-reflowable bumps; and c) selecting an amount of reflowable material such that a substantial portion of the selected amount of reflowable material remains at the interconnect location during reflow.
Brief Description of the Drawings
An embodiment of the present invention will now be more fully described, by way of example, with reference to the drawings of which:
FIG. 1 shows a top view of a part of a leadframe; FIG. 2 shows a flowchart detailing a process for forming a FCOL semiconductor package with a semiconductor die and a leadframe; and
FIGS. 3A-D shows cross-sectional views of a part of the leadframe and the semiconductor die during the process in FIG. 1.
Detail Description of the Drawings
A predetermined amount of solder is deposited more uniformly on the free ends of copper posts extending from die pads of a semiconductor die. The solder deposits are coated with flux and the semiconductor die is then placed on a leadframe with the solder deposits abutting interconnect locations on inner lead portions of the leadframe. When reflowed, the solder deposits melt and with the assistance of the flux forms solder interconnects between the free ends of the copper posts and the interconnect locations. Due to the predetermined amount of solder deposited on the free ends of the copper posts more uniformly, the molten solder tends not to flow away from the interconnect locations. Thus, advantageously allowing a substantial portion of the solder to remain at the interconnect locations resulting in more uniform solder interconnects. After forming the solder interconnects, the assembly of the semiconductor die and the leadframe is encapsulated in mold compound with outer lead portions exposed and/or extending from the FCOL semiconductor package. A non-leaded version of the resultant package is often referred to as the quad non- lead package (QFN).
FIG. 1 shows a part of a leadframe 100, which has inner lead portions 101, outer lead portions 102 and dam bar portions 103. The outline 104 indicates the location for placing a flipped semiconductor die (not shown) on the leadframe 100. After a FCOL semiconductor package (not shown) is formed on the leadframe 100, the inner lead portions 101, which are coupled to the semiconductor die, will be enclosed with the semiconductor die in the FCOL semiconductor package, and the outer lead portions 102 will extend from the package. The dam bar portions 103 define an outline of the FCOL package, and provide a seal during the molding process that encapsulates the semiconductor die and the inner lead portions 102 in the FCOL package. The dam bar portions 103 and other excess portions of the lead frame 100 are removed during a subsequent trim and form operation after encapsulation or when the FCOL semiconductor package is singulated from the leadframe 100. Typically, the leadframe 100 is supplied by a vendor in a strip on which several FCOL semiconductor packages can be formed, as is known in the art. More commonly, the leadframe comprises copper and is plated with silver, nickel or palladium, however, the present invention also extends to use with un-plated leadframes, such as bare copper leadframes.
The leadframe 100 is a patterned metal leadframe, which provides a patterned layer of metal conductors, and can comprise a stamping from a sheet of metal, such as copper. Alternatively, the leadframe 100 can be produced by etching a copper sheet. When the thickness of the metal is relatively small, the leadframe 100 can comprise flexible circuits, also known as flex circuits, which includes a flexible substrate. In addition, the leadframe 100, as referred to herein, extends to substrates including ceramic, laminate, polyimide substrate, and tape. With reference to FIG. 2 and FIGS. 3A-D a process 200 for forming a FCOL semiconductor package, in accordance with the present invention, starts 205 with providing 210 the copper leadframe 100. To facilitate description, only a portion of the lead frame 100 and a portion of a semiconductor die 305 are shown in FIGS. 3A-D. However, it will be appreciated by one skilled in the art, that the process 200 as described applies to all copper posts 310 on the semiconductor die 305 and all the inner lead portions 101 of the leadframe 100 that form the FCOL semiconductor package.
Next the semiconductor die 305 is provided 215, where the semiconductor die 305 includes copper posts 310 extending from pads (not shown) on the semiconductor die 305 as shown in FIG. 3A. A process for forming the copper posts 310 on the semiconductor die 305 when the die is part of a semiconductor wafer was alluded to earlier. A variety of other wafer bumping techniques may be employed to form non-reflowable bumps on a wafer, and the constituent bumped semiconductor dies of such wafers can be used in accordance with the present invention to form FCOL semiconductor packages. Examples of such non-reflowable bumps include gold, indium, tin, lead-free tin bismuth, lead free tin-copper, lead free tin-silver, and the like.
In addition, FIG. 3A shows the inner lead portions 101 of two adjacent leads of the leadframe 100 where each of the inner lead portions 101 has an interconnect location 335 thereon. An interconnect location herein is defined as the area on the inner lead portion 101 when the copper posts 310 are aligned with the inner lead portions 101 i.e. the area bounded by the circumference of the copper posts 310 when the copper posts are aligned with the inner lead portions 101, where the circumference of the copper posts are projected onto the inner lead portions 101. The broken lines in FIGS. 3A and 3C define the interconnect locations 335 on the inner lead portions 101. The pattern of interconnect locations 335 on the inner lead portions 101 corresponds to the pattern of copper posts 310 that extend from the semiconductor die 305 when the semiconductor die 315 is aligned with the inner lead portions 101. Subsequently, reflowable conductive deposits 315, such as solder, is plated on or attached in the form of solder balls, on the free ends of the copper posts 310. In this way the solder deposits 315 are disposed 220 on the free ends of the copper posts 310. The solder deposits 315 can be disposed by a variety of techniques, as will be known to one skilled in the art. A reference cited earlier describes a process that disposes solder on the copper posts when the copper bumps are formed by electroplating.
The amount of solder disposed on the end of each of the copper posts 310 of the semiconductor die 305 is predetermined, and whatever process that is employed to dispose the solder, that process must ensure that the predetermined amount of solder is disposed on each of the copper post 310. Here, a plating process is used as the plating process has a lower process variation then that of the solder printing process. This allows the amount of solder disposed on the free ends of the copper posts to be better controlled and more uniform on a semiconductor die. The amount of solder disposed is dependent on a variety of factors which can include: type of solder, dimensions of the copper post, material at the interconnect location, mass of the semiconductor die, number of copper posts, reflow profile when reflowing the solder deposits 315, the expected final dimensions of the reflowed solder and copper post, and the type of flux. This measured amount of the solder, advantageously allows a substantial portion of the disposed solder deposits 315 to remain at the interconnect locations 335 during reflow when the solder deposits 315 are in molten state.
Flux 320 is then applied or coated 225 on the solder deposits 315. This is often achieved by briefly positioning the semiconductor die 305 with the solder deposits 315 immersed in a reservoir of the flux 320. At elevated temperatures, the flux 320 cleans a surface to which it is applied to enhance the adhesion of the solder deposits 315. The cleaned surfaces include the surface of the solder deposit 315 and the interconnect locations 335. After the flux 320 is applied, the semiconductor die 305 is ready to be mounted on the leadframe 100. Alternatively, the flux 320 can be printed or disposed on the interconnect locations 335, although this would require additional equipment relative to a single handler picking up the semiconductor die 305 with the solder, dipping the solder deposits 315 on the copper posts 310 in flux 320 and then placing the semiconductor die 305 on the leadframe 100.
After applying the flux 320, the semiconductor die 305 is positioned above the leadframe 100 with the solder deposits 315 aligned with the interconnect locations 335 on the leadframe 100. The semiconductor die 305 is then placed 230 on the leadframe 100. The step of placing here can include exerting and maintaining a predetermined force on the semiconductor die 305 against the leadframe 100. When the semiconductor die 305 is placed on the leadframe 100, the lower surface of the solder deposits 315 abut the interconnect locations 335, and the flux 320 on the solder deposits 315 flows around the solder deposits 315 and on the interconnect locations 335. The flux 320 on the solder deposits 315 wets or adheres to the interconnect locations 335 as shown in FIG. 3B, in preparation for the next step. The assembly of the semiconductor die 305, the leadframe 100, and the flux 320, is then reflowed 235. Reflowing processes will be known to one skilled in the art in relation to flip chip semiconductor packages, and no further detail is provided herein, except to the extent where such detail enhances the understanding of the present invention. During reflow 235, the flux 320 cleans the interconnect locations 335 on the leadframe 100, and the solder deposits 315 change to a molten state. The molten solder flows onto the cleaned interconnect locations 335, and adheres thereto forming a solder interconnect 340 between each of the copper posts 310 and the corresponding interconnect locations 335, as shown in FIG. 3C. The solder interconnect 340 is sometimes called a fillet. The predetermined amount of solder 315 deposited determines the formation of the solder interconnect 340, thus ensuring a substantial portion of the solder 315 deposited remains at the interconnect location 335.
Consequently, there is more solder at the interconnect locations 335, which increases the mechanical strength of the coupling between the copper posts 310 and the leadframe 100, thus producing more reliable electrical coupling. Hence, the present invention, as described, advantageously, reduces the flow of solder away from the interconnect locations, thus, improving the coupling between the copper posts and the leadframe formed by the resultant solder interconnects.
After reflowing 235, when normal flux is used, the assembly is cleaned to remove any access flux 320, and the assembly is encapsulated 245 in mold compound 345 as shown in FIG. 3D, to produce a flip chip semiconductor package (not shown) on the leadframe 100. Alternatively, when no-clean flux is employed, cleaning is not necessarily required. Subsequently, after a final step of singulating the FCOLF semiconductor package from the leadframe 100, during which the dam bar portions 103 are severed, the process 200 ends 245. As will be known to one skilled in the art, there may be the additional steps of forming the external lead portions 102, and testing the functionality of the semiconductor die 320, prior to singulation. An example of a semiconductor package formed in accordance with the present invention comprises a semiconductor die with copper post having a pitch of 250 microns, where the copper post has a length of 70 microns and a diameter of 100 microns. The solder plated on the free ends of the copper posts has a thickness of 30 microns, and the semiconductor die was mounted on a bare copper leadframe.
The present invention, as described, provides a method of forming a flip chip semiconductor package on a leadframe where a predetermined amount of solder disposed on the copper posts on a semiconductor die tends to remain at interconnect locations on the leadframe.
This is accomplished by determining the amount of solder to be disposed taking into account a variety of factors including type of solder, the dimensions of the metal post, the material at the interconnect location, the mass of the die, the number of metal posts, the reflow profile, the expected final dimensions of the reflowed solder and copper post and the type of flux. Thus, the present invention, as described provides a method for forming a flip chip on leadframe semiconductor package, which overcomes or at least reduces the abovementioned problems of the prior art.
It will be appreciated that although only one particular embodiment of the invention has been described in detail, various modifications and improvements can be made by a person skilled in the art without departing from the scope of the present invention.

Claims

Claims
1. A method for forming a flip chip semiconductor package, the method comprising the steps of: a) providing a patterned layer of metal conductors having a first surface for providing a pattern of interconnect locations thereon; b) providing a semiconductor die having a first surface with a corresponding pattern of pads thereon, the pads having non-reflowable material thereon; c) disposing a predetermined amount of reflowable conductive material on the non-reflowable material; d) placing the semiconductor die on the patterned layer of metal conductors, wherein the reflowable conductive material abuts the interconnect locations; and e) reflowing the reflowable conductive material, wherein a substantial portion of the reflowable conductive material remains substantially at the interconnect locations to form conductive interconnects between the non-reflowable material and the interconnect locations.
2. A method in accordance with claim 1 wherein step (c) comprises the step of determining the predetermined amount of reflowable conductive material based on material composition of the reflowable conductive material.
3. A method in accordance with claim 1 wherein step (c) comprises the step of determining the predetermined amount of reflowable conductive material based on material composition of the interconnect locations.
4. A method in accordance with claim 1 wherein step (c) comprises the step of determining the predetermined amount of reflowable conductive material based on material composition of the non- reflowable material.
5. A method in accordance with claim 1 wherein step (c) comprises the step of determining the predetermined amount of reflowable conductive material based on dimensions of the non-reflowable material.
6. A method in accordance with claim 1 wherein step (c) comprises the step of determining the predetermined amount of reflowable conductive material based on mass of the semiconductor die.
7. A method in accordance with claim 1 wherein step (c) comprises the step of determining the predetermined amount of reflowable conductive material based on number of pads having non-reflowable material thereon.
8. A method in accordance with claim 1 wherein step (c) comprises the step of determining the predetermined amount of reflowable conductive material based on expected final dimensions of reflowed reflowable material.
9. A method in accordance with claim 1 wherein step (c) comprises the step of plating the predetermined amount of reflowable conductive material on the non-reflowable material
10. A method in accordance with claim 1 further comprising after step (c) and before step (d), the step of applying a cleaning agent.
11. A method in accordance with claim 10 comprising the step of applying a cleaning agent to the reflowable conductive material.
12. A method in accordance with claim 10 wherein step (c) comprises the step of determining the predetermined amount of reflowable conductive material based on material composition of the cleaning agent.
13. A method in accordance with claim 1 wherein step (a) comprises the step of providing the patterned layer of metal conductors having a first surface with a layer of plating thereon.
14. A method in accordance with claim 13 wherein step (c) comprises the step of determining the predetermined amount of reflowable conductive material based on material composition of the layer of plating.
15. A method in accordance with claim 1 wherein step (a) comprises the step of providing the patterned layer of copper conductors.
16. A method in accordance with claim 15 wherein step (a) further comprises the step of providing a layer of plating on the first surface of the patterned layer of copper conductors.
17. A method in accordance with claim 15 wherein step (b) comprises the step of providing a semiconductor die having the first surface with the corresponding pattern of pads thereon, the pads having copper posts thereon and extending therefrom.
18. A method in accordance with claim 17 wherein step (c) comprises the step of disposing a predetermined amount of solder on free ends of the copper posts.
19. A method in accordance with claim 18 after step (c) and before step (d) comprising the step of applying flux to the solder.
20. A method in accordance with claim 19 after the step of applying flux to the solder, the step of cleaning the semiconductor die and the patterned layer of copper conductors.
21. A method in accordance with claim 20 further comprising after the step of cleaning, the step of encapsulating at least a part of the semiconductor die and at least a part of the patterned layer of copper conductors to form a semiconductor package.
22. A method in accordance with claim 21 further comprising after the step of encapsulating, the step of singulating the semiconductor package from the leadframe.
23. A method in accordance with claim 21 wherein the step of encapsulating comprises the step of molding.
24. A method for determining the amount of reflowable material to be disposed on non-reflowable bumps on a semiconductor die to mount the semiconductor die on a leadframe having interconnect locations thereon, the method comprising the steps of: a) determining surface area of one of the non-reflowable bumps; b) defining a corresponding interconnect location on the leadframe having substantially the same area as the surface area of the one of the non-reflowable bumps; and c) selecting an amount of reflowable material such that a substantial portion of the selected amount of reflowable material remains at the interconnect location during reflow.
25. A method in accordance with claim 24 wherein step (a) comprises the step of determining surface area of the one of the non-reflowable bumps to which the reflowable material tends to adhere.
26. A method in accordance with claim 25 wherein step (b) comprises the step of projecting the surface area of the one of the non-reflowable bumps to which the reflowable material tends to adhere on the leadframe when the one of the non-reflowable bumps is aligned with the leadframe.
27. A method in accordance with claim 26 further comprising the step of plating the selected amount of reflowable material on the non- reflowable bumps.
PCT/SG2002/000189 2001-08-21 2002-08-20 Method for forming a flip chip on leadframe semiconductor package WO2003017366A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/934,019 US6550666B2 (en) 2001-08-21 2001-08-21 Method for forming a flip chip on leadframe semiconductor package
US09/934,019 2001-08-21

Publications (1)

Publication Number Publication Date
WO2003017366A1 true WO2003017366A1 (en) 2003-02-27

Family

ID=25464823

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/SG2002/000189 WO2003017366A1 (en) 2001-08-21 2002-08-20 Method for forming a flip chip on leadframe semiconductor package

Country Status (3)

Country Link
US (1) US6550666B2 (en)
CN (1) CN100521130C (en)
WO (1) WO2003017366A1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100755686B1 (en) * 2005-01-04 2007-09-05 삼성전자주식회사 Apparatus and method for signal amplitude
CN102049580A (en) * 2010-09-26 2011-05-11 广州金升阳科技有限公司 Welding method of lead frame
WO2020109495A1 (en) 2018-11-28 2020-06-04 Autostore Technology AS Storage container for automated storage and retrieval system
WO2023066849A1 (en) 2021-10-18 2023-04-27 Autostore Technology AS A service vehicle for an automated storage and retrieval system

Families Citing this family (124)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6826827B1 (en) * 1994-12-29 2004-12-07 Tessera, Inc. Forming conductive posts by selective removal of conductive material
DE10158770B4 (en) * 2001-11-29 2006-08-03 Infineon Technologies Ag Lead frame and component with a lead frame
TW200423344A (en) * 2002-12-31 2004-11-01 Texas Instruments Inc Composite metal column for mounting semiconductor device
US7550852B2 (en) 2002-12-31 2009-06-23 Texas Instruments Incorporated Composite metal column for mounting semiconductor device
US20040222518A1 (en) * 2003-02-25 2004-11-11 Tessera, Inc. Ball grid array with bumps
US7462936B2 (en) 2003-10-06 2008-12-09 Tessera, Inc. Formation of circuitry with modification of feature height
US7495179B2 (en) * 2003-10-06 2009-02-24 Tessera, Inc. Components with posts and pads
US8641913B2 (en) * 2003-10-06 2014-02-04 Tessera, Inc. Fine pitch microcontacts and method for forming thereof
US7462942B2 (en) * 2003-10-09 2008-12-09 Advanpack Solutions Pte Ltd Die pillar structures and a method of their formation
US8129841B2 (en) 2006-12-14 2012-03-06 Stats Chippac, Ltd. Solder joint flip chip interconnection
US8574959B2 (en) 2003-11-10 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
US20060216860A1 (en) 2005-03-25 2006-09-28 Stats Chippac, Ltd. Flip chip interconnection having narrow interconnection sites on the substrate
WO2005048311A2 (en) 2003-11-10 2005-05-26 Chippac, Inc. Bump-on-lead flip chip interconnection
US8350384B2 (en) * 2009-11-24 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US9029196B2 (en) * 2003-11-10 2015-05-12 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
USRE47600E1 (en) 2003-11-10 2019-09-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US8216930B2 (en) 2006-12-14 2012-07-10 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
US8026128B2 (en) 2004-11-10 2011-09-27 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US20050168231A1 (en) * 2003-12-24 2005-08-04 Young-Gon Kim Methods and structures for electronic probing arrays
US7709968B2 (en) * 2003-12-30 2010-05-04 Tessera, Inc. Micro pin grid array with pin motion isolation
US8207604B2 (en) * 2003-12-30 2012-06-26 Tessera, Inc. Microelectronic package comprising offset conductive posts on compliant layer
US7176043B2 (en) * 2003-12-30 2007-02-13 Tessera, Inc. Microelectronic packages and methods therefor
US7230302B2 (en) 2004-01-29 2007-06-12 Enpirion, Inc. Laterally diffused metal oxide semiconductor device and method of forming the same
US8253196B2 (en) 2004-01-29 2012-08-28 Enpirion, Inc. Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same
JP3994095B2 (en) * 2004-06-23 2007-10-17 ローム株式会社 Surface mount electronic components
US7453157B2 (en) 2004-06-25 2008-11-18 Tessera, Inc. Microelectronic packages and methods therefor
KR101313391B1 (en) 2004-11-03 2013-10-01 테세라, 인코포레이티드 Stacked packaging improvements
US7939934B2 (en) 2005-03-16 2011-05-10 Tessera, Inc. Microelectronic packages and methods therefor
US8841779B2 (en) 2005-03-25 2014-09-23 Stats Chippac, Ltd. Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate
US20060226199A1 (en) * 2005-03-30 2006-10-12 Visteon Global Technologies, Inc. Selective soldering of flat flexible cable with lead-free solder to a substrate
US8039956B2 (en) * 2005-08-22 2011-10-18 Texas Instruments Incorporated High current semiconductor device system having low resistance and inductance
US7335536B2 (en) 2005-09-01 2008-02-26 Texas Instruments Incorporated Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices
US7687925B2 (en) 2005-09-07 2010-03-30 Infineon Technologies Ag Alignment marks for polarized light lithography and method for use thereof
WO2007031298A1 (en) * 2005-09-14 2007-03-22 Htc Beteiligungs Gmbh Flip-chip module and method for the production thereof
US8067267B2 (en) * 2005-12-23 2011-11-29 Tessera, Inc. Microelectronic assemblies having very fine pitch stacking
US8058101B2 (en) * 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
DE102006006561B4 (en) * 2006-02-13 2009-03-05 Htc Beteiligungs Gmbh Flip-chip module and method for exchanging a semiconductor chip of a flip-chip module
US20070284420A1 (en) * 2006-06-13 2007-12-13 Advanpack Solutions Pte Ltd Integrated circuit chip formed on substrate
US7545029B2 (en) * 2006-08-18 2009-06-09 Tessera, Inc. Stack microelectronic assemblies
US7600667B2 (en) * 2006-09-29 2009-10-13 Intel Corporation Method of assembling carbon nanotube reinforced solder caps
US7510401B2 (en) * 2006-10-12 2009-03-31 Tessera, Inc. Microelectronic component with foam-metal posts
US7719121B2 (en) * 2006-10-17 2010-05-18 Tessera, Inc. Microelectronic packages and methods therefor
US20080150101A1 (en) * 2006-12-20 2008-06-26 Tessera, Inc. Microelectronic packages having improved input/output connections and methods therefor
US20090014852A1 (en) * 2007-07-11 2009-01-15 Hsin-Hui Lee Flip-Chip Packaging with Stud Bumps
EP2206145A4 (en) 2007-09-28 2012-03-28 Tessera Inc Flip chip interconnection with double post
US20090108443A1 (en) * 2007-10-30 2009-04-30 Monolithic Power Systems, Inc. Flip-Chip Interconnect Structure
US7691670B2 (en) 2008-05-01 2010-04-06 Gem Services, Inc. Interconnection of lead frame to die utilizing flip chip process
US20100044860A1 (en) * 2008-08-21 2010-02-25 Tessera Interconnect Materials, Inc. Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer
US8536458B1 (en) 2009-03-30 2013-09-17 Amkor Technology, Inc. Fine pitch copper pillar package and method
TWI445147B (en) * 2009-10-14 2014-07-11 Advanced Semiconductor Eng Semiconductor device
TW201113962A (en) * 2009-10-14 2011-04-16 Advanced Semiconductor Eng Chip having metal pillar structure
TWI502706B (en) * 2009-10-29 2015-10-01 Taiwan Semiconductor Mfg Co Ltd Robust joint structure for flip-chip bonding
CN101807532B (en) * 2010-03-30 2012-05-09 上海凯虹科技电子有限公司 Ultra-thin chip inversely packaging method and packaged body
US8330272B2 (en) 2010-07-08 2012-12-11 Tessera, Inc. Microelectronic packages with dual or multiple-etched flip-chip connectors
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US8580607B2 (en) 2010-07-27 2013-11-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
TWI478303B (en) 2010-09-27 2015-03-21 Advanced Semiconductor Eng Chip having metal pillar and package having the same
TWI451546B (en) 2010-10-29 2014-09-01 Advanced Semiconductor Eng Stacked semiconductor package, semiconductor package thereof and method for making a semiconductor package
KR101075241B1 (en) 2010-11-15 2011-11-01 테세라, 인코포레이티드 Microelectronic package with terminals on dielectric mass
US8853558B2 (en) 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
US20120146206A1 (en) 2010-12-13 2012-06-14 Tessera Research Llc Pin attachment
US9137903B2 (en) 2010-12-21 2015-09-15 Tessera, Inc. Semiconductor chip assembly and method for making same
US8492893B1 (en) 2011-03-16 2013-07-23 Amkor Technology, Inc. Semiconductor device capable of preventing dielectric layer from cracking
KR101128063B1 (en) 2011-05-03 2012-04-23 테세라, 인코포레이티드 Package-on-package assembly with wire bonds to encapsulation surface
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US8872318B2 (en) 2011-08-24 2014-10-28 Tessera, Inc. Through interposer wire bond using low CTE interposer with coarse slot apertures
US8836136B2 (en) 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US8884443B2 (en) 2012-07-05 2014-11-11 Advanced Semiconductor Engineering, Inc. Substrate for semiconductor package and process for manufacturing
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9177899B2 (en) 2012-07-31 2015-11-03 Mediatek Inc. Semiconductor package and method for fabricating base for semiconductor package
TWI562295B (en) 2012-07-31 2016-12-11 Mediatek Inc Semiconductor package and method for fabricating base for semiconductor package
US10991669B2 (en) 2012-07-31 2021-04-27 Mediatek Inc. Semiconductor package using flip-chip technology
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US8686568B2 (en) 2012-09-27 2014-04-01 Advanced Semiconductor Engineering, Inc. Semiconductor package substrates having layered circuit segments, and related methods
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
TWI544591B (en) 2012-11-30 2016-08-01 英力股份有限公司 Semiconductor device and method of forming the same
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9087815B2 (en) 2013-11-12 2015-07-21 Invensas Corporation Off substrate kinking of bond wire
US9082753B2 (en) 2013-11-12 2015-07-14 Invensas Corporation Severing bond wire by kinking and twisting
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9673192B1 (en) 2013-11-27 2017-06-06 Altera Corporation Semiconductor device including a resistor metallic layer and method of forming the same
US9536938B1 (en) 2013-11-27 2017-01-03 Altera Corporation Semiconductor device including a resistor metallic layer and method of forming the same
US10020739B2 (en) 2014-03-27 2018-07-10 Altera Corporation Integrated current replicator and method of operating the same
US9793877B2 (en) 2013-12-17 2017-10-17 Avago Technologies General Ip (Singapore) Pte. Ltd. Encapsulated bulk acoustic wave (BAW) resonator device
CN103752970B (en) * 2013-12-24 2017-09-22 广州金升阳科技有限公司 A kind of welding method of lead frame
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9642261B2 (en) * 2014-01-24 2017-05-02 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Composite electronic structure with partially exposed and protruding copper termination posts
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
CN104392941B (en) * 2014-10-31 2017-11-03 通富微电子股份有限公司 The method for forming flip chip semiconductor package
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
TWI556368B (en) * 2015-01-16 2016-11-01 南茂科技股份有限公司 Chip package structure and manufacturing method thereof
US10103627B2 (en) 2015-02-26 2018-10-16 Altera Corporation Packaged integrated circuit including a switch-mode regulator and method of forming the same
US9888579B2 (en) * 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US9633971B2 (en) 2015-07-10 2017-04-25 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
US10636758B2 (en) * 2017-10-05 2020-04-28 Texas Instruments Incorporated Expanded head pillar for bump bonds

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2142568A (en) * 1983-06-30 1985-01-23 Raychem Corp Assembly of electronic components
EP0304118A2 (en) * 1987-08-19 1989-02-22 Gec-Marconi Limited Alignment of fibre arrays
WO1996002845A1 (en) * 1994-07-19 1996-02-01 Liang Louis H Methods and apparatus for test and burn-in of integrated circuit devices
US5759910A (en) * 1996-12-23 1998-06-02 Motorola, Inc. Process for fabricating a solder bump for a flip chip integrated circuit
EP0899787A2 (en) * 1997-07-25 1999-03-03 Mcnc Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structurs formed thereby
US6180265B1 (en) * 1997-06-27 2001-01-30 Delco Electronics Corporation Flip chip solder bump pad
WO2001043518A1 (en) * 1999-12-13 2001-06-14 Hestia Technologies, Inc. Chip package with molded underfill
US6274474B1 (en) * 1999-10-25 2001-08-14 International Business Machines Corporation Method of forming BGA interconnections having mixed solder profiles

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4914814A (en) * 1989-05-04 1990-04-10 International Business Machines Corporation Process of fabricating a circuit package
JP2716336B2 (en) * 1993-03-10 1998-02-18 日本電気株式会社 Integrated circuit device
JPH06268020A (en) * 1993-03-10 1994-09-22 Sumitomo Electric Ind Ltd Semiconductor device
US5543585A (en) * 1994-02-02 1996-08-06 International Business Machines Corporation Direct chip attachment (DCA) with electrically conductive adhesives
US6177636B1 (en) * 1994-12-29 2001-01-23 Tessera, Inc. Connection components with posts
US5634268A (en) * 1995-06-07 1997-06-03 International Business Machines Corporation Method for making direct chip attach circuit card
US5796591A (en) * 1995-06-07 1998-08-18 International Business Machines Corporation Direct chip attach circuit card
US6344234B1 (en) * 1995-06-07 2002-02-05 International Business Machines Corportion Method for forming reflowed solder ball with low melting point metal cap
US5872051A (en) * 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate
US5889326A (en) * 1996-02-27 1999-03-30 Nec Corporation Structure for bonding semiconductor device to substrate
US6114187A (en) * 1997-01-11 2000-09-05 Microfab Technologies, Inc. Method for preparing a chip scale package and product produced by the method
US5907492A (en) * 1997-06-06 1999-05-25 Micron Technology, Inc. Method for using data regarding manufacturing procedures integrated circuits (IC's) have undergone, such as repairs, to select procedures the IC's will undergo, such as additional repairs
KR100278219B1 (en) * 1997-06-18 2001-01-15 클라크 3세 존 엠. Method of making flip chip and bga interconnections
US6082610A (en) * 1997-06-23 2000-07-04 Ford Motor Company Method of forming interconnections on electronic modules
US6303872B1 (en) * 1997-06-25 2001-10-16 Visteon Global Tech. Anti-tombstoning solder joints
US6025649A (en) * 1997-07-22 2000-02-15 International Business Machines Corporation Pb-In-Sn tall C-4 for fatigue enhancement
US6372624B1 (en) * 1997-08-04 2002-04-16 Micron Technology, Inc. Method for fabricating solder bumps by wave soldering
US6107180A (en) * 1998-01-30 2000-08-22 Motorola, Inc. Method for forming interconnect bumps on a semiconductor die
US6337445B1 (en) * 1998-03-16 2002-01-08 Texas Instruments Incorporated Composite connection structure and method of manufacturing
US6181569B1 (en) * 1999-06-07 2001-01-30 Kishore K. Chakravorty Low cost chip size package and method of fabricating the same
JP4331834B2 (en) * 1999-09-06 2009-09-16 富士機械製造株式会社 Screen printing method and apparatus
US6395097B1 (en) * 1999-12-16 2002-05-28 Lsi Logic Corporation Method and apparatus for cleaning and removing flux from an electronic component package
US6380555B1 (en) * 1999-12-24 2002-04-30 Micron Technology, Inc. Bumped semiconductor component having test pads, and method and system for testing bumped semiconductor components

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2142568A (en) * 1983-06-30 1985-01-23 Raychem Corp Assembly of electronic components
EP0304118A2 (en) * 1987-08-19 1989-02-22 Gec-Marconi Limited Alignment of fibre arrays
WO1996002845A1 (en) * 1994-07-19 1996-02-01 Liang Louis H Methods and apparatus for test and burn-in of integrated circuit devices
US5759910A (en) * 1996-12-23 1998-06-02 Motorola, Inc. Process for fabricating a solder bump for a flip chip integrated circuit
US6180265B1 (en) * 1997-06-27 2001-01-30 Delco Electronics Corporation Flip chip solder bump pad
EP0899787A2 (en) * 1997-07-25 1999-03-03 Mcnc Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structurs formed thereby
US6274474B1 (en) * 1999-10-25 2001-08-14 International Business Machines Corporation Method of forming BGA interconnections having mixed solder profiles
WO2001043518A1 (en) * 1999-12-13 2001-06-14 Hestia Technologies, Inc. Chip package with molded underfill

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100755686B1 (en) * 2005-01-04 2007-09-05 삼성전자주식회사 Apparatus and method for signal amplitude
CN102049580A (en) * 2010-09-26 2011-05-11 广州金升阳科技有限公司 Welding method of lead frame
CN102049580B (en) * 2010-09-26 2013-04-24 广州金升阳科技有限公司 Welding method of lead frame
WO2020109495A1 (en) 2018-11-28 2020-06-04 Autostore Technology AS Storage container for automated storage and retrieval system
WO2023066849A1 (en) 2021-10-18 2023-04-27 Autostore Technology AS A service vehicle for an automated storage and retrieval system

Also Published As

Publication number Publication date
US20030038162A1 (en) 2003-02-27
CN1486510A (en) 2004-03-31
CN100521130C (en) 2009-07-29
US6550666B2 (en) 2003-04-22

Similar Documents

Publication Publication Date Title
US6550666B2 (en) Method for forming a flip chip on leadframe semiconductor package
US6510976B2 (en) Method for forming a flip chip semiconductor package
US6732913B2 (en) Method for forming a wafer level chip scale package, and package formed thereby
US7397114B2 (en) Semiconductor integrated circuit device and method of manufacturing the same
KR100545008B1 (en) Semiconductor element and a producing method for the same, and a semiconductor device and a producing method for the same
KR100239406B1 (en) Surface mounted semiconductor package and method of manufacturing the same
US6350386B1 (en) Method of making a support circuit with a tapered through-hole for a semiconductor chip assembly
KR100430330B1 (en) A method of forming conductive bumps on an electrode of a semiconductor chip using a wrapping technique and the bumps produced thereby
US20040130009A1 (en) Method for maintaining solder thickness in flipchip attach packaging processes
US10593640B2 (en) Flip chip integrated circuit packages with spacers
KR20030051222A (en) Semiconductor device and method of manufacturing the same
JP3450236B2 (en) Semiconductor device and manufacturing method thereof
US7032807B2 (en) Solder contact reworking using a flux plate and squeegee
US20020089836A1 (en) Injection molded underfill package and method of assembly
US20170053883A1 (en) Integrated circuit package
JP3836349B2 (en) Semiconductor device and manufacturing method thereof
KR100234694B1 (en) Manufacturing method of bga package
US20230260958A1 (en) Flip-Chip Package Assembly
KR20000008347A (en) Method for manufacturing flip chip bga package
JP3417292B2 (en) Semiconductor device
McCann et al. Package characterization and development of a flip chip QFN package: fcMLF
US20210375808A1 (en) Packaged semiconductor device with electroplated pillars
WO2002101829A1 (en) Method for forming a wafer level chip scale package, and package formed thereby
Vandecasteele et al. Lead-free Flip Chip: a comparison between lead-free solder and adhesives

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BY BZ CA CH CN CO CR CU CZ DE DM DZ EC EE ES FI GB GD GE GH HR HU ID IL IN IS JP KE KG KP KR LC LK LR LS LT LU LV MA MD MG MN MW MX MZ NO NZ OM PH PL PT RU SD SE SG SI SK SL TJ TM TN TR TZ UA UG UZ VN YU ZA ZM

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SD SE SG SI SK SL TJ TM TN TR TT TZ UA UG UZ VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LU MC NL PT SE SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ UG ZM ZW AM AZ BY KG KZ RU TJ TM AT BE BG CH CY CZ DK EE ES FI FR GB GR IE IT LU MC PT SE SK TR BF BJ CF CG CI GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 028038002

Country of ref document: CN

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP