WO2003012851A3 - Method of etching ferroelectric layers - Google Patents

Method of etching ferroelectric layers Download PDF

Info

Publication number
WO2003012851A3
WO2003012851A3 PCT/US2002/024346 US0224346W WO03012851A3 WO 2003012851 A3 WO2003012851 A3 WO 2003012851A3 US 0224346 W US0224346 W US 0224346W WO 03012851 A3 WO03012851 A3 WO 03012851A3
Authority
WO
WIPO (PCT)
Prior art keywords
containing gas
etching
ferroelectric layers
gas
nitrogen
Prior art date
Application number
PCT/US2002/024346
Other languages
French (fr)
Other versions
WO2003012851A2 (en
Inventor
Hideyuki Yamauchi
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of WO2003012851A2 publication Critical patent/WO2003012851A2/en
Publication of WO2003012851A3 publication Critical patent/WO2003012851A3/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • H01L21/31122Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/55Capacitors with a dielectric comprising a perovskite structure material

Abstract

A method of etching a ferroelectric layer comprises etching a ferroelectric layer using boron trichloride gas and at least one auxiliary gas selected from the group consisting of a carbon-containing gas and a nitrogen-containing gas. The carbon-containing gas may include CHF3 or C2H4. The nitrogen-containing gas may include N2 or NF3. The method reduces side etching of ferroelectric layers, and in particular, PZT-based ferroelectric layers and thereby improves electrical performance and reliability of devices made therefrom.
PCT/US2002/024346 2001-07-31 2002-07-31 Method of etching ferroelectric layers WO2003012851A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001232528A JP2003059906A (en) 2001-07-31 2001-07-31 Etching method, and method of forming capacitor
JP2001-232528 2001-07-31

Publications (2)

Publication Number Publication Date
WO2003012851A2 WO2003012851A2 (en) 2003-02-13
WO2003012851A3 true WO2003012851A3 (en) 2003-04-24

Family

ID=19064442

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/024346 WO2003012851A2 (en) 2001-07-31 2002-07-31 Method of etching ferroelectric layers

Country Status (4)

Country Link
US (1) US20030047532A1 (en)
JP (1) JP2003059906A (en)
TW (1) TW565886B (en)
WO (1) WO2003012851A2 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7217665B2 (en) 2002-11-20 2007-05-15 Applied Materials, Inc. Method of plasma etching high-K dielectric materials with high selectivity to underlying layers
CN100559592C (en) * 2003-04-15 2009-11-11 富士通微电子株式会社 The manufacture method of semiconductor device
EP1629529A2 (en) * 2003-05-30 2006-03-01 Tokyo Electron Limited Method and system for etching a high-k dielectric material
US6867053B2 (en) * 2003-07-28 2005-03-15 Infineon Technologies Ag Fabrication of a FeRAM capacitor using a noble metal hardmask
KR100732026B1 (en) 2005-04-08 2007-06-27 후지쯔 가부시끼가이샤 Method for fabricating semiconductor device
JP4515956B2 (en) * 2005-05-02 2010-08-04 株式会社日立ハイテクノロジーズ Sample etching method
US20100003828A1 (en) * 2007-11-28 2010-01-07 Guowen Ding Methods for adjusting critical dimension uniformity in an etch process with a highly concentrated unsaturated hydrocarbon gas
JP2009266952A (en) * 2008-04-23 2009-11-12 Seiko Epson Corp Method for manufacturing and manufacturing apparatus for device
DE112010003598T5 (en) * 2009-09-09 2013-01-24 Ulvac, Inc. Method for operating a substrate processing device
US10692759B2 (en) * 2018-07-17 2020-06-23 Applied Materials, Inc. Methods for manufacturing an interconnect structure for semiconductor devices

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5443688A (en) * 1993-12-02 1995-08-22 Raytheon Company Method of manufacturing a ferroelectric device using a plasma etching process
EP1001459A2 (en) * 1998-09-09 2000-05-17 Texas Instruments Incorporated Integrated circuit comprising a capacitor and method
US6100201A (en) * 1997-03-05 2000-08-08 Nec Corporation Method of forming a semiconductor memory device
WO2000049649A2 (en) * 1999-02-17 2000-08-24 Applied Materials, Inc. Method for preventing corrosion of a dielectric material
WO2001082344A2 (en) * 2000-04-21 2001-11-01 Applied Materials, Inc. Method of patterning lead zirconium titanate and barium strontium titanate
WO2002015250A1 (en) * 2000-08-11 2002-02-21 Infineon Technologies Ag Structuring of ferroelectric layers

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6232174B1 (en) * 1998-04-22 2001-05-15 Sharp Kabushiki Kaisha Methods for fabricating a semiconductor memory device including flattening of a capacitor dielectric film
US6620733B2 (en) * 2001-02-12 2003-09-16 Lam Research Corporation Use of hydrocarbon addition for the elimination of micromasking during etching of organic low-k dielectrics
US6559001B2 (en) * 2001-05-30 2003-05-06 International Business Machines Corporation Methods of patterning a multi-layer film stack and forming a lower electrode of a capacitor

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5443688A (en) * 1993-12-02 1995-08-22 Raytheon Company Method of manufacturing a ferroelectric device using a plasma etching process
US6100201A (en) * 1997-03-05 2000-08-08 Nec Corporation Method of forming a semiconductor memory device
EP1001459A2 (en) * 1998-09-09 2000-05-17 Texas Instruments Incorporated Integrated circuit comprising a capacitor and method
WO2000049649A2 (en) * 1999-02-17 2000-08-24 Applied Materials, Inc. Method for preventing corrosion of a dielectric material
WO2001082344A2 (en) * 2000-04-21 2001-11-01 Applied Materials, Inc. Method of patterning lead zirconium titanate and barium strontium titanate
WO2002015250A1 (en) * 2000-08-11 2002-02-21 Infineon Technologies Ag Structuring of ferroelectric layers

Also Published As

Publication number Publication date
JP2003059906A (en) 2003-02-28
WO2003012851A2 (en) 2003-02-13
TW565886B (en) 2003-12-11
US20030047532A1 (en) 2003-03-13

Similar Documents

Publication Publication Date Title
WO2004059751A3 (en) Methods of forming semiconductor mesa structures including self-aligned contact layers and related devices
CA2157257A1 (en) Semiconductor Device with Amorphous Carbon Layer and Method of Fabricating the Same
WO2004082010A3 (en) Method of improving interlayer adhesion
WO2002007233A3 (en) Group iii nitride compound semiconductor device
WO2004066345A3 (en) Doped semiconductor nanocrystal layers and preparation thereof
WO2005050716A3 (en) High-temperature devices on insulator substrates
AU2003235902A1 (en) Semiconductor substrate manufacturing method and semiconductor device manufacturing method, and semiconductor substrate and semiconductor device manufactured by the methods
WO2003095358A3 (en) Method of forming manofluidic channels
WO2004051708A3 (en) Method and device for machining a wafer, in addition to a wafer comprising a separation layer and a support layer
WO2004070817A3 (en) Method of eliminating residual carbon from flowable oxide fill material
WO2001082336A3 (en) Laminate comprising barrier layers on a substrate
AU2002301853A1 (en) Locking device, locker, key and locking method
EP1394865A4 (en) Iii group nitride based semiconductor element and method for manufacture thereof
WO2002003474A3 (en) N-type nitride semiconductor laminate and semiconductor device using same
WO2003012851A3 (en) Method of etching ferroelectric layers
EP1777739A3 (en) Semiconductor device and fabrication method therefor
WO2002082510A8 (en) Single transistor rare earth manganite ferroelectric nonvolatile memory cell
WO2004064090A3 (en) Methods and structure for improving wafer bow control
AU2001218182A1 (en) Methods of fabricating gallium nitride semiconductor layers on substrates including non-gallium nitride posts, and gallium nitride semiconductor structures fabricated thereby
AU2002365488A1 (en) Method for the fabrication of silicon nitride, silicon oxynitride, and silicon oxide films by chemical vapor deposition
WO2003100843A3 (en) Etching gas and method for dry etching
TW350972B (en) Semiconductor and the manufacturing method
EP1396884A3 (en) Interlayer insulation film used for multilayer interconnect of semiconductor integrated circuit and method of manufacturing the same
WO2003010814A1 (en) Production method for semiconductor device
WO2003054964A3 (en) Monos device having buried metal silicide bit line

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): CN KR

Kind code of ref document: A2

Designated state(s): CN