WO2003009482A1

WO2003009482A1 - Superregenerative low-power receiver

Info

Publication number: WO2003009482A1
Application number: PCT/IL2002/000567
Authority: WO
Inventors: Vadim Leibman
Original assignee: Vadim Leibman
Priority date: 2001-07-15
Filing date: 2002-07-14
Publication date: 2003-01-30

Abstract

A superregenerative radio receiver (22) includes an antenna (24), configured to receive a radio frequency (RF) input signal. A pulse generator (30,46) generates a sequence of pulses at a sampling frequency, the pulses having a smooth rising edge and a fast falling edge. An RF oscillator (42), driven by the pulses generated by the pulse generator, has a positive feedback loop (64) coupled to the antenna, so that a characteristic of oscillation of the RF oscillator, when driven by the pulses, varies responsive to the RF input signal. Amplification circuitry (48) is coupled to the RF oscillator so as to generate an output signal having a level that varies responsive to the characteristic of the oscillation.

Description

SUPERREGENERATIVE LOW-POWER RECEIVER

FIELD OF THE INVENTION

The present invention relates generally to low-power radio devices, and specifically to ultra-low power superregenerative radio frequency (RF) data receivers. BACKGROUND OF THE INVENTION

Low-power radio data receiver devices are commonly used in a growing range of applications. The typical design of such a device includes a low-power RF receiver circuit coupled to an antenna for receiving RF data signals transmitted over the air. The receiver outputs a data signal corresponding to modulated data carried by the RF input signal. The data signal is input to a digital microcontroller, which processes the data contained in the signal and performs some function in response to the data. In order to carry out this task, the microcontroller must typically sample and process the signal much faster then the data rate. Alternatively, much larger data volumes may be transmitted, in order to allow the microcontroller to perform error correction algorithms on the data. In many applications, the data receiver device (including the antenna, RF receiver and microcontroller) is produced as part of a wireless transponder, which returns a response signal when interrogated with the proper RF input signal.

The useful life of a wireless data receiver device is typically limited by the lifetime of its battery. To extend battery life, it is clearly desirable to reduce the power consumption of all elements of the receiver device, including both the RF receiver and the microcontroller. One way to reduce power consumption is to power up the device only intermittently, on demand or on some predetermined schedule. When continuous availability of the receiver device is required, however, this approach is infeasible.

Superregenerative radio receiver circuits are commonly used in applications, such as wireless data receiver devices, that call for low-power detection of radio signals without requiring high-fidelity signal reproduction. A superregenerative receiver is built around a high-frequency oscillator, which is set to oscillate at the frequency of the signal to be received. The high-frequency oscillator is driven between oscillating and non-oscillating states at an IF switching frequency, much lower than the RF oscillation frequency. This switching frequency is known as the quenching frequency, and it is typically provided by an oscillator, known as the quench oscillator. When an RF signal at the proper frequency is present on the receiver antenna, it generates positive feedback in the high-frequency oscillator, causing stronger oscillation in the oscillating state. The strength of the oscillation provides a measure of the presence (or absence) of the signal at the selected oscillation frequency. Although superregenerative receivers are simple and inexpensive to produce, their power consumption is still too high for many applications. Even though the high-frequency oscillator is active (in the oscillating state) for only a short portion of the quenching cycle, it is under power and driven by the quench oscillator continuously. McEwan suggests a possible solution to this problem in U.S. Patent 5,630,216, whose disclosure is incorporated herein by reference. This patent describes a superregenerative receiver in which the quench oscillator applies a waveform that rises sharply and then decays exponentially, rather than providing a sinusoidal quenching waveform, as is usually applied in such receivers. As a result of this choice of waveform, the high-frequency oscillator is driven by the quench oscillator during only a short part of the quenching cycle, and power consumption of the receiver is reduced. SUMMARY OF THE INVENTION

It is an object of some aspects of the present invention to provide an ultra-low power superregenerative radio data receiver device.

It is a further object of some aspects of the present invention to provide a superregenerative receiver that provides continuous, reliable detection of radio signals while requiring very low power.

It is still a further object of some aspects of the present invention to provide digital signal processing circuits that reduce the computing burden imposed on a microcontroller in a data receiver device, and thus allow the microcontroller to operate at a lower rate, with reduced power consumption. In preferred embodiments of the present invention, a radio data receiver device comprises a superregenerative receiver circuit, an integration circuit and a microcontroller.

The receiver circuit senses RF data signals transmitted over the air using a high-frequency oscillator, which is driven by a train of pulses at the quenching frequency. The rising edge of each pulse is smoothed to prevent undesired ringing of the oscillator, while the falling edge drops quickly to minimize the duty cycle (and hence the power consumption) of the oscillator.

The smooth rising edge (in contrast to the sharp rising edge of the pulses in the above- mentioned U.S. Patent 5,630,216) gives the oscillator high sensitivity to RF signals over a broad band of frequencies. The smooth pulse is particularly advantageous in enhancing oscillator sensitivity on account of the non-linear collector-base capacitance of the transistor used in the oscillator. The pulse is preferably supplied to the oscillator through a diode so as to prevent full discharge of the voltage after the end of the pulse. Additionally or alternatively, a capacitor is coupled to sample and hold the voltage level provided to the oscillator during the pulse, and is then disconnected at the end of the pulse. As a result, the oscillator is held near (but below) the oscillation threshold until the next pulse.

The oscillator output charges a capacitor, which samples and holds the level of the modulated data carried by the RF signals during each pulse. The capacitor is disconnected in between the driving pulses, in order to save energy and maintain its level value from pulse to pulse. Since the oscillator typically has a high output impedance, a voltage follower stage is preferably interposed between the oscillator and this capacitor, in order to avoid loading the oscillator. The capacitor output is preferably smoothed by a low-pass filter and is then converted by a level discriminator into a stream of binary data samples for input to the integration circuit.

Typically, the binary data samples are generated at the quenching frequency of the receiver circuit, which is considerably higher than the data modulation frequency of the RF signals transmitted over the air. Therefore, a binary "one" carried by the RF signal will give rise to a string of ones in the receiver circuit output, while a binary "zero" will give a string of zeroes in the output. Noise in the receiver, in the absence of an actual RF signal, may give rise to a random mixture of ones and zeroes. In data receivers known in the art, the microcontroller must receive and process all the binary data samples at the frequency at which these samples are generated by the receiver circuit (i.e., the quenching frequency, in the present embodiment) in order to determine whether it is dealing with valid data or only noise.

By contrast, in preferred embodiments of the present invention, the integration circuit sums together sequences of the bits in the sample stream. The summation is performed over a sliding window, which is preferably implemented using a shift register with an analog summing circuit. If the window contains a string of ones, corresponding to a "one" in the modulated data, then the sum output by the integration circuit will be high, above an upper threshold level. On the other hand, if the window contains a string of zeroes, corresponding to a "zero" in the modulated data, the sum will be low, below a lower threshold level. An intermediate sum, between the upper and lower thresholds, is indicative of a mixture of ones and zeroes in the window. The sum of the samples in the window is input to comparator logic, which outputs a one or a zero to the microcontroller only if the sum is above or below the upper or lower threshold, respectively. Thus, when a data signal is actually present at the receiver circuit, the binary output level of the comparator logic changes at a rate that is roughly equal to the modulation frequency of the RF signals. When only noise is present, the comparator logic gives an invalid output.

As a result of this integration process, the microcontroller is relieved of the burden of processing all the samples output by the receiver circuit. Instead, the microcontroller processes only the integrated data, which changes at a rate that is roughly equal to the modulation frequency of the transmitted data. This data rate is typically about an order of magnitude less than the sampling rate used by the receiver. The microcontroller can therefore operate at a much lower clock frequency than would be required if the microcontroller had to actually receive and process all the samples, as in data receivers known in the art. This reduction in the clock frequency of the microcontroller allows the power consumed by the microcontroller to be substantially reduced. The additional power needed by the integration circuit is minimal.

Although the preferred embodiments described herein use a combination of novel elements, including a low-power superregenerative receiver circuit and an integration circuit, each of these elements may also be used individually, without the other. It is also noted that the design of the -superregenerative receiver circuit described herein may be adapted in a straightforward way for receiving analog, rather than digital, RF signals.

There is therefore provided, in accordance with a preferred embodiment of the present invention, a superregenerative radio receiver, including: an antenna, configured to receive a radio frequency (RF) input signal; a pulse generator, adapted to generate a sequence of pulses at a sampling frequency, the pulses having a smooth rising edge and a fast falling edge; a RF oscillator, coupled to be driven by the pulses generated by the pulse generator, and having a positive feedback loop coupled to the antenna, so that a characteristic of oscillation of the RF oscillator, when driven by the pulses, varies responsive to the RF input signal; and amplification circuitry coupled to the RF oscillator so as to generate an output signal having a level that varies responsive to the characteristic of the oscillation. Typically, the RF input signal includes data modulated onto a carrier frequency by amplitude modulation (AM), and the RF oscillator is configured to oscillate at the carrier frequency so that an amplitude of the oscillation varies responsive to the modulation of the carrier frequency.

Preferably, the pulse generator includes a RC low-pass filter for smoothing the leading edge of the pulses.

Additionally or alternatively, the RF oscillator includes a switch, which is adapted to open and close in synchronization with the sequence of the pulses, so as to sample and hold a voltage level in the oscillator between the pulses in the sequence. Preferably, the RF oscillator includes a capacitor, which is coupled to the switch so that the capacitor samples and holds the level of the output signal between the pulses that drive the oscillator. Most preferably, the RF oscillator further includes a voltage follower circuit, which is coupled between the oscillator and the capacitor, and which is also driven by the sequence of pulses. Further additionally or alternatively, the RF oscillator includes a capacitor, which is coupled to the switch so that the capacitor samples and holds a bias level of the oscillator between the pulses that drive the oscillator.

In a preferred embodiment, the RF input signal includes binary data modulated onto a carrier frequency, and the receiver includes a comparator, which is coupled to compare the level of the output signal to a dynamic threshold in order to recover the binary data.

There is also provided, in accordance with a preferred embodiment of the present invention, a radio data receiver device, including: an antenna, configured to receive a radio frequency (RF) input signal, which is modulated with a sequence of digital data including first and second binary values at a predetermined modulation frequency;

RF receiver circuitry, coupled to the antenna and adapted to amplify and sample the input signal at a sampling frequency, which is substantially greater than the modulation frequency, so as to output a voltage level indicative of the modulated digital data; a digitizer, which is coupled to generate a train of digital samples based on the voltage level; an integrator, which is adapted to integrate the samples in the train so as to output the sequence of the digital data at an output frequency that is substantially less than the sampling frequency, the integrator including a shift register, having a plurality of cells, which are coupled to receive the samples in the train; summing circuitry, coupled to sum the samples in at least a group of the cells in the shift register so as to determine a sum value; and comparator logic, adapted to output the first binary value if the sum value is above a first threshold, and to output the second binary value if the sum value is below a second threshold, which is substantially less than the first threshold.

Preferably, the RF receiver circuitry includes a superregenerative receiver circuit, which is driven to oscillate, responsive to the RF input signal, by driving pulses provided to the receiver circuit at the sampling frequency, the pulses having a smooth rising edge and a fast falling edge. Typically, the device includes a microprocessor, which is coupled to receive and process the digital data output by the integrator. Preferably, the device includes a clock generator, which is adapted to generate a clock signal at the sampling frequency, so as to drive the RF receiver circuit, the integrator and the microprocessor.

Preferably, the output frequency of the integrator is substantially equal to the modulation frequency of the digital data.

Additionally or alternatively, the comparator logic is adapted to output a null value if the sum value is between the first and second thresholds.

In a preferred embodiment, the integrator further includes an inverter, which is operative to invert a sub-group of the samples in the group of the cells, before the samples are summed by the summing circuitry. Additionally or alternatively, the shift register includes first and second shift registers, and the summing circuitry includes first and second summing circuits, coupled to sum the samples in first and second groups of the cells to generate first and second sum values, respectively, and wherein the comparator logic is coupled to process the first and second sum values together in order to determine the binary value to output. There is additionally provided, in accordance with a preferred embodiment of the present invention, a radio data receiver device, including: a clock generator, which is adapted to generate a clock signal at a clock frequency; an antenna, configured to receive a radio frequency (RF) input signal, which is modulated with a sequence of digital data including first and second binary values at a predetermined modulation frequency, which is substantially less than the clock frequency; RF receiver circuitry, coupled to the antenna and driven at the clock frequency to amplify and sample the input signal at the clock frequency, so as to output a train of digital samples indicative of the modulated digital data; an integrator, which is adapted to integrate the samples in the train so as to output the sequence of the digital data at an output frequency that is substantially less than the clock frequency; and a microprocessor, which is driven to operate at the clock frequency and is coupled to receive and process the digital data output by the integrator.

Preferably, the output frequency of the integrator is substantially equal to the modulation frequency of the digital data. There is further provided, in accordance with a preferred embodiment of the present invention, a method for processing radio signals, including: coupling an antenna to a positive feedback loop of a radio frequency (RF) oscillator; driving the RF oscillator with a sequence of pulses at a sampling frequency, the pulses having a smooth rising edge and a fast falling edge, so that a characteristic of oscillation of the RF oscillator, when driven by the pulses, varies responsive to the a RF input signal received by the antenna; and processing -an output of the RF oscillator so as to generate an output signal having a level that varies responsive to the characteristic of the oscillation.

There is moreover provided, in accordance with a preferred embodiment of the present invention, a method for processing radio signals, including: receiving a radio frequency (RF) input signal, which is modulated with a sequence of digital data including first and second binary values at a predetermined modulation frequency; amplifying and sampling the input signal at a sampling frequency, which is substantially greater than the modulation frequency, so as to output a train of digital samples indicative of the modulated digital data; inputting the samples in the train to a shift register; summing the samples in at least a group of the cells in the shift register so as to determine a sum value; and recovering the sequence of the digital data at an output frequency that is substantially less than the sampling frequency by comparing the sum value to a first threshold and to a second threshold, which is substantially less than the first threshold, so as to output the first binary value if the sum value is above the first threshold, and to output the second binary value if the sum value is below the second threshold.

There is furthermore provided, in accordance with a preferred embodiment of the present invention, a method for processing radio signals, including: generating a clock signal at a predetermined clock frequency; receiving a radio frequency (RF) input signal, which is modulated with a sequence of digital data including first and second binary values at a predetermined modulation frequency, which is substantially less than the clock frequency; amplifying and sampling the input signal at the clock frequency, which is substantially greater than the modulation frequency, so as to output a train of digital samples indicative of the modulated digital data; integrating the samples in the train so as to output the sequence of the digital data at an output frequency that is substantially less than the clock frequency; and processing the output sequence of the digital data using a microprocessor, which is driven to operate at the clock frequency.

The present invention will be more fully understood from the following detailed description of the preferred embodiments thereof, taken together with the drawings in which: BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram that schematically illustrates a radio data receiver device, in accordance with a preferred embodiment of the present invention;

Fig. 2 is a block diagram that schematically shows details of a superregenerative receiver, in accordance with a preferred embodiment of the present invention;

Figs. 3A-3C are schematic circuit diagrams of a superregenerative receiver, in accordance with a preferred embodiment of the present invention; Fig. 4 is a timing diagram showing signals generated in the circuits of Figs. 3A-3C; Fig. 5 is a schematic circuit diagram showing a digital preprocessing circuit, in accordance with a preferred embodiment of the present invention; and

Fig. 6 is a schematic circuit diagram showing a digital preprocessing circuit, in accordance with another preferred embodiment of the present invention. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Fig. 1 is a block diagram that schematically illustrates an ultra-low power radio data receiver device 20, in accordance with a preferred embodiment of the present invention. A receiver circuit 22 is coupled to an antenna 24 so as to receive radio frequency (RF) signals transmitted over the air, at a RF carrier frequency. Typically, the carrier frequency is in the range of 300-500 MHz, although the architecture of device 20 is equally applicable to higher or lower frequencies. The RF signals are modulated by a transmitter (not shown) with digital data at a predetermined modulation frequency, which is much lower than the carrier frequency. Typically, the RF signals are amplitude modulated (AM), but other modulation schemes may similarly be used, such as frequency modulation (FM), phase modulation or various types of pulse modulation, as are known in the art.

Receiver circuit 22 amplifies and samples the RF signals so as generate a stream of digital output samples. Preferably, particularly when AM signals are used, the receiver circuit comprises a superregenerative receiver, as described in detail hereinbelow. The output samples are indicative of the modulated data carried by the input signal, but the samples typically also contain noise components. Receiver circuit 22 outputs the samples at a sampling frequency that is determined by a clock circuit 30. Typically, in order to ensure reliable detection of the data, the sampling frequency is considerably greater than the modulation frequency. For example, in applications in which the data modulation frequency is on the order of one to a few kilohertz, the sampling frequency could be in the 30-40 kHz range. These frequencies are typical of low-cost, battery-operated, radio-controlled devices. Other combinations of frequencies may also be used, as will be apparent to those skilled in the art.

An integrator 26 receives the stream of samples output by receiver circuit 22 and sums together groups of samples within a sliding time window. Preferably, for simplicity and low power consumption, the integrator comprises a shift register with an analog summing circuit and comparator logic, as described in detail hereinbelow. Alternatively, other implementations of the integrator may be used. The integrator generates a binary output corresponding to the modulated data carried by the input signal. The output data rate of the integrator is much lower than the sampling frequency at which the integrator receives the samples. Preferably, the output data rate of the integrator is equal to the modulation frequency. Most preferably, the integrator also indicates whether the samples in its current window correspond to valid data (indicated by a sequence of successive ones or successive zeroes in the sample stream), or whether there are no data detectable in the current window, only noise.

The data output from the integrator is received by a microprocessor 28, preferably a microcontroller such as a PIC12C5xx device, which is available from Digi-Key (Thief River Falls, Minnesota) and other suppliers. Due to the operation of integrator 26 in reducing the rate of input data that microprocessor 28 must receive, it is possible to run the microprocessor at a very slow clock rate, which may be on the order of the sampling frequency (30-40 kHz in the present example). The microprocessor analyzes the data received from the RF signals and then, typically, decides on some action to take, such as responding to the input signal or actuating a control. Since the power consumption of the microprocessor is generally proportional to its clock rate, the use of integrator 26 allows very substantial savings in the overall power consumption of device 20. In one design that the inventor developed, whose details are further described below, the estimated power consumption of the components of device 20 in continuous operation was as follows: • Receiver circuit - 15 μA

• Integrator - 8 μA

• Microprocessor- 15 μA

The total power consumption of device 20 was thus less than 40 μA. It may be possible to reduce these figures by further optimization and by using a different microprocessor. The elements of device 20 may be designed and fabricated as a single integrated circuit, using CMOS technology, for example. Alternatively, device 20 may be implemented using a number of chips and discrete components. Device 20 is preferably integrated in a single, encapsulated unit together with a battery (not shown).

The small size and ultra-low power consumption of device 20 make it useful in a wide range of applications, some of which are listed here by way of example: As "smart tags" in storage warehouses and other facilities, for inventory control, location and quality checking.

In postal and parcel forwarding facilities, as smart tags for locating and routing parcels.

As tags for personal items and other products, to assist users in locating their belongings.

In transponders used for locating children, medical patients, prisoners and other persons, as well as pets.

In transponders used to locate and identify stolen vehicles and other goods. • As a remote control actuator for mechanical and electrical devices.

In transponders used to identify individuals, for access control and other security applications.

In wireless smart cards used for electronic payment and other commercial applications. • In remote control of surveillance and eavesdropping systems.

For wireless control of valves in intelligent irrigation systems.

As tags attached to wild animals and birds for research purposes.

In alarm systems for protecting valuable items in museums, stores and other facilities. • For remote testing of fire and intrusion alarm systems.

As receivers for remote calibration of clocks.

In wireless telephones, for extending battery life while on standby.

Preferably, device 20 is configured for continuous operation, i.e., to be capable of receiving radio signals at all times. The power consumption of device 20 is so low that even the very thin types of batteries that are currently used in smart cards and tags should be able to sustain this continuous operation for several years. Alternatively, device 20 may be operated intermittently, so as to extend its useful life even further. Further alternatively or additionally, microprocessor 28 may be programmed, and device 20 may be appropriately designed, so that when the microprocessor receives a certain data code, it increases its clock rate for subsequent data reception and processing. This scheme allows device 20 to work at very low power most of the time, but to increase power on occasion when higher processing speed is needed for some particular task.

Fig. 2 is a block diagram that schematically shows details of receiver circuit 22, in accordance with a preferred embodiment of the present invention. The receiver circuit in this embodiment comprises an ultra-low power, superregenerative receiver. Antenna 24 receives RF signals, which are amplitude-modulated by the transmitter with binary data. The signals received by antenna 24 are processed by an input circuit 40, which typically comprises a high- frequency filter, such as a surface acoustic wave (SAW) device, as is known in the art. Optionally, the input circuit also includes a buffer amplifier. The signals from input circuit 40 are coupled to the positive feedback loop of a high- frequency (HF) oscillator 42, which is preset or tuned to oscillate at the carrier frequency of the RF signals. Oscillator 42 is actuated periodically by a voltage pulse supplied by clock 30, which thus determines the quenching frequency (or sampling frequency) of oscillator 42. Clock 30 preferably puts out narrow pulses, i.e., it operates at a low duty cycle, in order to reduce power consumption by oscillator 42. While the switch is open (non-conducting), the oscillator consumes essentially no power.

In order to prevent ringing of oscillator 42 on the leading edge of the driving pulses from clock 30, the pulses are smoothed by a transient suppressor circuit 46. Typically, circuit 46 comprises a simple RC low-pass filter. Due to the smooth leading edge of the pulses supplied by circuit 46, oscillator 42 enters its oscillatory state smoothly, as it does when driven by a sinusoidal quenching waveform in superregenerative receivers known in the art. As a result of the reduced ringing and the smooth entry into oscillation, the oscillator maintains high sensitivity to RF input signals over a broad band of frequencies.

Oscillator 42 comprises one or more capacitors (shown explicitly in Fig. 3A), which sample and hold the voltage levels reached during each pulse. A sample/hold circuit 47 is driven by clock 30 to disconnect the capacitors in between the driving pulses, in order to save energy and maintain the voltage levels from pulse to pulse.

Oscillator 42 generates a train of pulses at the sampling frequency, whose amplitude is proportional to the modulation of the received RF signal. The pulses are smoothed and amplified by a low-pass filter and amplifier circuit 48. The smoothed output signal is input to a comparator 50, which generates a stream of binary data samples, whose values are determined by whether the output signal is above or below a given binarization threshold. In the embodiment shown in Fig. 1, this sample stream is input to integrator 26 for further processing.

Reference is now made to Figs. 3A-3C and Fig. 4, which schematically illustrate an exemplary design of receiver circuit 22, in accordance with a preferred embodiment of the present invention. Figs. 3A-3C are circuit diagrams showing details of the receiver circuit. Typical component values and part numbers are shown in the figures. Fig. 4 is a timing diagram showing signals appearing at selected points in the circuits of Figs. 3A-3C, which are marked with letters A through E. The implementation illustrated here is shown solely by way of example. Alternative designs of superregenerative receivers based on the principles of the present invention and the functional elements shown in Fig. 2 will be apparent to those skilled in the art.

Referring first to Fig. 3A, signals received by antenna 24 pass through input circuit 40, which in this embodiment comprises a surface acoustic wave (SAW) filter 60, as is known in the art. A buffer amplifier may also be used in the input circuit, although it is not needed in the present embodiment. High-frequency oscillator circuit 42 receives the filtered signals. The oscillator circuit comprises a first transistor 62 with a positive feedback loop 64, coupled to a voltage follower transistor 66 for impedance matching of the oscillator output.

The elements of oscillator 42 are driven by clock circuit 30, shown in Fig. 3C. The clock signal typically has the form of a train of square wave pulses, as shown in trace A of Fig. 4. Alternatively, if microprocessor 28 has its own clock, the microprocessor clock signal can be used to drive the analog switches instead. The driving pulses provided by clock 30 are smoothed by transient suppressor 46, which has the form of a RC smoothing circuit. The pulses are supplied to the oscillator through a diode 61 so as to prevent full discharge of the pulse voltage after the end of the pulse. The smoothed clock signals result in smoothing of the bias level of transistor 62, as shown in trace D in Fig. 4. When the voltage on transistor 62 passes the oscillation threshold, high-frequency oscillation ensues, illustrated by shaded regions 72 in trace C. The point of onset and the amplitude of the oscillations depends on the amplitude of the input radio signal received by antenna 24. As shown by trace C, the oscillation cuts off sharply at the falling edge of the driving signal. The output signal from transistor 66 is shown in trace B in Fig. 4. This output is sampled and held by a capacitor 76. The function of sample/hold circuit 47 is performed by switches 68 and 70, are driven by clock 30 to connect and disconnect capacitors 76 and 77, respectively. As a result capacitors 76 and 77 hold their charge between clock pulses, thereby reducing still further the power consumption of receiver circuit 22. The voltage level on capacitor 76 is shown in trace E in Fig. 4. The operation of switch 70 also causes capacitor 76 to maintain its output data level value from pulse to pulse.

The sampled and held output of oscillator 42 is received by filter and amplifier circuit 48, as shown in Fig. 3B. This signal is smoothed by a low-pass filter 74, producing the low- pass signal shown in trace E. The low-pass signal from filter 74 is amplified by first and second amplification stages 78 and 80. The final amplified signal is input to comparator 50, which serves to digitize the output voltage level of receiver circuit 22. Comparator 50 outputs a voltage corresponding to binary one or zero, depending on whether the output of amplifier circuit 48 is above or below a dynamic threshold determined by the preceding output level of the oscillator.

Fig. 5 is a schematic circuit diagram showing details of integrator 26, in accordance with a preferred embodiment of the present invention. Digital data samples, such as samples of the level output by comparator 50, are input to a shift register 100. The shift register comprises a sequence of cells 102, which are driven to shift their contents in sequence down the register by clock circuit 30. The contents of cells 102 at each clock cycle are summed by a summing circuit 103, made up of a network of resistors 104 and 106. Other implementations of summing circuit 103 are, of course, possible, but the configuration shown in Fig. 5 is particularly simple, inexpensive and low in power consumption. The number of cells summed by the summing circuit is preferably chosen to be n = T/t, wherein T is the period of the modulated data carried by the RF signal received by device 20, and t is the period of the sample clock generated by clock circuit 30.

Summing circuit 103 outputs a voltage that is proportional to the sum of the bits in cells 102. In the embodiment shown here, the output voltage is VoUT ⁼ nVR[/R2, wherein V

is the supply voltage and Rj and R2 are the resistances of resistors 106 and 104, respectively (assuming that all of resistors 104 have the same value). It will be observed that if all, or nearly all, the cells contain ones, then the sum will be maximal, or nearly so; whereas if all, or nearly all, the cells contain zeroes, then the sum will be minimal, or nearly minimal. An intermediate sum, between these near-maximal and near-minimal values, is indicative of a mixture of ones and zeroes in the cells. Assuming that the RF signals received by device 20 are modulated with data at a rate that is considerably slower than the rate of clock 30, a binary one in the modulated data carried by the RF signal will give rise to a string of ones in shift register 100, while a binary zero will give rise to a string of zeroes in the shift register. In the absence of an actual modulated RF signal, or at transitions in the modulated data, the shift register will contain a mixture of ones and zeroes. The sum generated by summing circuit 103 is input to comparators 108 and 110.

Comparator 108 is set to output a one when the sum of cells 102 is above an upper threshold set to the near-maximal value of the sum mentioned above, while comparator 110 is set to output a one when the sum is below a lower threshold set to the near-minimal value of the sum. For intermediate values of the sum, both comparators put out a zero. Combiner logic 112 receive the comparator outputs and generates an integrated square wave signal output corresponding to the modulated data. When a data signal is actually present at receiver circuit 22, the binary output level of the square wave signal changes at a rate that is roughly equal to the modulation frequency of the RF signals. When only noise is present at the receiver circuit, logic 112 gives an invalid or null output. The integrated signal is then input to microprocessor 28.

Fig. 6 is a schematic circuit diagram showing an integrator 126, in accordance with another preferred embodiment of the present invention. Integrator 126 comprises two shift registers 130 and 134, which receive the input stream of data samples in parallel. An inverter 132 flips the values of the samples between one and zero at the input to shift register 134. The values of the group of samples in shift register 130 are then summed with the inverted values of an earlier group of samples that are held in shift register 134. As can be seen in the figure, the shift registers are arranged and synchronized so that a sequential group of samples is summed, wherein the earlier sub-group in the sequence is inverted before summing. The resulting sum is compared to an upper threshold level by comparator 108. (Comparator 110 and logic 112 are omitted from this figure for simplicity of illustration.) The threshold applied to comparator 108 is set so that comparator 108 will output a one only if the sequence of samples consists of a group of zeroes (inverted and entered into shift register 134), followed by a group of ones (in shift register 130). Integrator 126 thus detects a particular transition between the levels of the modulated data. Alternatively, the same effect could be accomplished by combining the functions of shift registers 130 and 134 into a single shift register, with suitable logic at the outputs of the cells to be inverted, or with separate summing circuits for the first and second sub-groups of cells, followed by appropriate combiner logic. The ability to detect the transition in this way is useful, for example, when FM data modulation is applied to the RF signal, since in this case, the high-frequency discriminator used to detect the modulated signal may distort the duty cycle of the modulation waveform. Similar arrangements may be used to provide automatic detection of certain predetermined codes of ones and zeroes in the modulated signal, without requiring microprocessor 28 to analyze the digital data.

Although the preferred embodiments described herein use superregenerative receiver circuit 22 and integrator 26 in combination, each of these elements may also be used individually, without the other. In other words, superregenerative receivers based on the principles of the present invention may be used to process RF signals and detect modulated data in other applications, without necessarily using integrator 26. Similarly, logic circuits based on the principles of integrators 26 and 126 may be used in other sample processing applications, regardless of the type of modulation and the type of receiver that is used to generate the samples.

It will thus -be appreciated that the preferred embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and subcombinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art.

Claims

1. A superregenerative radio receiver, comprising: an antenna, configured to receive a radio frequency (RF) input signal; a pulse generator, adapted to generate a sequence of pulses at a sampling frequency, the pulses having a smooth rising edge and a fast falling edge; a RF oscillator, coupled to be driven by the pulses generated by the pulse generator, and having a positive feedback loop coupled to the antenna, so that a characteristic of oscillation of the RF oscillator, when driven by the pulses, varies responsive to the RF input signal; and amplification circuitry coupled to the RF oscillator so as to generate an output signal having a level that varies responsive to the characteristic of the oscillation.

2. A receiver according to claim 1, wherein the RF input signal comprises data modulated onto a carrier frequency by amplitude modulation (AM), and wherein the RF oscillator is configured to oscillate at the carrier frequency so that an amplitude of the oscillation varies responsive to the modulation of the carrier frequency.

3. A receiver according to claim 1, wherein the pulse generator comprises a RC low-pass filter for smoothing the leading edge of the pulses.

4. A receiver according to any of claims 1-3, wherein the RF oscillator comprises a switch, which is adapted to open and close in synchronization with the sequence of the pulses, so as to sample and hold a voltage level in the oscillator between the pulses in the sequence.

5. A receiver according to claim 4, wherein the RF oscillator comprises a capacitor, which is coupled to the switch so that the capacitor samples and holds the level of the output signal between the pulses that drive the oscillator.

6. A receiver according to claim 5, wherein the RF oscillator further comprises a voltage follower circuit, which is coupled between the oscillator and the capacitor, and which is also driven by the sequence of pulses.

7. A receiver according to claim 4, wherein the RF oscillator comprises a capacitor, which is coupled to the switch so that the capacitor samples and holds a bias level of the oscillator between the pulses that drive the oscillator.

8. A receiver according to any of claims 1-3, wherein the RF input signal comprises binary data modulated onto a carrier frequency, and wherein the receiver comprises a comparator, which is coupled to compare the level of the output signal to a dynamic threshold in order to recover the binary data.

9. A radio data receiver device, comprising: an antenna, configured to receive a radio frequency (RF) input signal, which is modulated with a sequence of digital data comprising first and second binary values at a predetermined modulation frequency;

RF receiver circuitry, coupled to the antenna and adapted to amplify and sample the input signal at a sampling frequency, which is substantially greater than the modulation frequency, so as to output a voltage level indicative of the modulated digital data; a digitizer, which is coupled to generate a train of digital samples based on the voltage level; and an integrator, which is adapted to integrate the samples in the train so as to output the sequence of the digital data at an output frequency that is substantially less than the sampling frequency, the integrator comprising: a shift register, having a plurality of cells, which are coupled to receive the samples in the train; summing circuitry, coupled to sum the samples in at least a group of the cells in the shift register so as to determine a sum value; and comparator logic, adapted to output the first binary value if the sum value is above a first threshold, and to output the second binary value if the sum value is below a second threshold, which is substantially less than the first threshold.

10. A device according to claim 9, wherein the RF receiver circuitry comprises a superregenerative receiver circuit, which is driven to oscillate, responsive to the RF input signal, by driving pulses provided to the receiver circuit at the sampling frequency, the pulses having a smooth rising edge and a fast falling edge.

11. A device according to claim 9, and comprising a microprocessor, which is coupled to receive and process the digital data output by the integrator.

12. A device according to claim 11, and comprising a clock generator, which is adapted to generate a clock signal at the sampling frequency, so as to drive the RF receiver circuit, the integrator and the microprocessor.

13. A device according to any of claims 9-12, wherein the output frequency of the integrator is substantially equal to the modulation frequency of the digital data.

14. A device according to any of claims 9-12, wherein the comparator logic is adapted to output a null value if the sum value is between the first and second thresholds.

15. A device according to any of claims 9-12, wherein the integrator further comprises an inverter, which is operative to invert a sub-group of the samples in the group of the cells, before the samples are summed by the summing circuitry.

16. A device according to any of claims 9-12, wherein the shift register comprises first and second shift registers, and wherein the summing circuitry comprises first and second summing circuits, coupled to sum the samples in first and second groups of the cells to generate first and second sum values, respectively, and wherein the comparator logic is coupled to process the first and second sum values together in order to determine the binary value to output.

17. A radio data receiver device, comprising: a clock generator, which is adapted to generate a clock signal at a clock frequency; an antenna, configured to receive a radio frequency (RF) input signal, which is modulated with a sequence of digital data comprising first and second binary values at a predetermined modulation frequency, which is substantially less than the clock frequency;

RF receiver circuitry, coupled to the antenna and driven at the clock frequency to amplify and sample the input signal at the clock frequency, so as to output a train of digital samples indicative of the modulated digital data; an integrator, which is adapted to integrate the samples in the train so as to output the sequence of the digital data at an output frequency that is substantially less than the clock frequency; and a microprocessor, which is driven to operate at the clock frequency and is coupled to receive and process the digital data output by the integrator.

18. A device according to claim 17, wherein the output frequency of the integrator is substantially equal to the modulation frequency of the digital data.

19. A method for processing radio signals, comprising: coupling an antenna to a positive feedback loop of a radio frequency (RF) oscillator; driving the RF oscillator with a sequence of pulses at a sampling frequency, the pulses having a smooth rising edge and a fast falling edge, so that a characteristic of oscillation of the RF oscillator, when driven by the pulses, varies responsive to the a RF input signal received by the antenna; and processing an output of the RF oscillator so as to generate an output signal having a level that varies responsive to the characteristic of the oscillation.

20. A method according to claim 19, wherein the RF input signal comprises data modulated onto a carrier frequency by amplitude modulation (AM), and driving the RF oscillator comprises causing the RF oscillator to oscillate at the carrier frequency so that an amplitude of the oscillation varies responsive to the modulation of the carrier frequency.

21. A method according to claim 19, wherein driving the RF oscillator comprises switching a current supplied to the oscillator at the sampling frequency so as to sample and hold a voltage level in the oscillator between the pulses that drive the oscillator.

22. A method according to claim 21, wherein the RF oscillator comprises a capacitor, and wherein switching the current comprises switching the current to the capacitor so that the capacitor samples and holds the level of the output signal between the pulses in the sequence.

23. A method according to claim 22, wherein driving the RF oscillator further comprises driving a voltage follower circuit, which is coupled between the oscillator and the capacitor, using the sequence^~of pulses.

24. A method according to claim 21, wherein the RF oscillator comprises a capacitor, and wherein switching the current comprises switching the current to the capacitor so that the capacitor samples and holds a bias level of the oscillator between the pulses in the sequence.

25. A method according to any of claims 19-24, wherein the RF input signal comprises binary data modulated onto a carrier frequency, and comprising comparing the level of the output signal to a dynamic threshold in order to recover the binary data.

26. A method for processing radio signals, comprising: receiving a radio frequency (RF) input signal, which is modulated with a sequence of digital data comprising first and second binary values at a predetermined modulation frequency; amplifying and sampling the input signal at a sampling frequency, which is substantially greater than the modulation frequency, so as to output a train of digital samples indicative of the modulated digital data; inputting the samples in the train to a shift register; summing the samples in at least a group of the cells in the shift register so as to determine a sum value; and recovering the sequence of the digital data at an output frequency that is substantially less than the sampling frequency by comparing the sum value to a first threshold and to a second threshold, which is substantially less than the first threshold, so as to output the first binary value if the sum value is above the first threshold, and to output the second binary value if the sum value is below the second threshold.

27. A method according to claim 26, wherein amplifying the input signal comprises driving a superregenerative receiver circuit to oscillate, responsive to the RF input signal, by applying driving pulses to the receiver circuit at the sampling frequency, the pulses having a smooth rising edge and a fast falling edge.

28. A method according to claim 26, and comprising processing the recovered digital data using a microprocessor driven by a clock signal at the sampling frequency.

29. A method according to any of claims 26-28, wherein the output frequency of the integrator is substantially equal to the modulation frequency of the digital data.

30. A method according to any of claims 26-28, wherein recovering the sequence of the digital data comprises outputting a null value if the sum value is between the first and second thresholds.

31. A method according to any of claims 26-28, wherein summing the samples comprises inverting a sub-group of the samples in the group of the cells.

32. A method for processing radio signals, comprising: generating a clock signal at a predetermined clock frequency; receiving a radio frequency (RF) input signal, which is modulated with a sequence of digital data comprising first and second binary values at a predetermined modulation frequency, which is substantially less than the clock frequency; amplifying and sampling the input signal at the clock frequency, which is substantially greater than the modulation frequency, so as to output a train of digital samples indicative of the modulated digital data; integrating the samples in the train so as to output the sequence of the digital data at an output frequency that is substantially less than the clock frequency; and processing the output sequence of the digital data using a microprocessor, which is driven to operate at the clock frequency.

33. A method according to claim 32, wherein the output frequency of the integrator is substantially equal to the modulation frequency of the digital data.