WO2002103767A1 - Epitaxial siox barrier/insulation layer______________________ - Google Patents
Epitaxial siox barrier/insulation layer______________________ Download PDFInfo
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- WO2002103767A1 WO2002103767A1 PCT/US2001/040970 US0140970W WO02103767A1 WO 2002103767 A1 WO2002103767 A1 WO 2002103767A1 US 0140970 W US0140970 W US 0140970W WO 02103767 A1 WO02103767 A1 WO 02103767A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76248—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using lateral overgrowth techniques, i.e. ELO techniques
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the invention relates to an insulating layer/barrier for deposition on a silicon substrate and/or epitaxial silicon surface, composites and structures comprising said insulating layer/barrier, method of making the composites and structure, as well as use of the insulating layer/barrier, composites and structures in the construction of improved semiconductor devices, including but not limited to quantum well, tunneling, metal oxide, SOI, superlattice, and three dimensional architecture.
- the insulating layer/barrier is formed by combining silicon with one or more elements to form an insulating compound of silicon where one of the possible elements is oxygen, forming a layer of SiO x where 0 ⁇ x ⁇ 2.0.
- the insulating layer structure is produced in such a way to allow for low defect epitaxial silicon to be deposited next to the insulating layer. It further relates to forming a number of such layers sandwiched between epitaxial silicon.
- Silicon dioxide (SiO 2 ) has been used for many years as an insulating material in semiconductors. It has excellent insulating properties and provides a potential barrier typically of 3.2eV. However, when SiO 2 is grown adjacent to silicon, there is a high mismatch between monocrystalline or epitaxial silicon and the layer of SiO 2 resulting in accumulated stress. These stresses, and therefore strains, cause the SiO 2 to become amorphous preventing the subsequent growth of epitaxial layers. Monocrystalline silicon in the semiconductor industry is available in the form of thin round disks called wafers. These single crystal wafers are produced by growing single crystal ingots from molten silicon which are then sliced and polished into a final "wafer" upon which semiconductor devices and integrated circuits are manufactured.
- SILICON ON INSULATOR fSOD Current silicon devices are limited by inherent parasitic circuit elements due primarily to junction capacitance and leakage currents. These problems can be addressed for silicon by fabricating silicon devices in a thin epitaxial layer on top of a buried insulator layer, the so-called silicon on insulator (SOI) approach. This approach allows devices to be isolated from the substrate as well as from each other, eliminating the need for structures such as guard-rings, isolation junctions, etc. (26)
- a number of technologies have been developed to place an insulating layer under a layer of low defect silicon which forms the substrate upon which silicon devices are fabricated.
- This insulating layer reduces the amount of leakage current as well as the junction capacitance thus significantly improving the device performance.
- Advantages include substantially reduced power consumption, more efficient low- voltage operation, significantly improved speed, radiation hardening and reduced integrated circuit manufacturing costs. These characteristics make SOI wafers well-suited for many commercial applications, including cellular phones, wireless communications devices, satellites, portable and desktop computers, automotive electronics, and microwave systems.
- One method of producing SOI wafers is by implanting oxygen ions below the surface of a silicon wafer in sufficient quantity to transform, with proper annealing, a layer of the silicon to silicon dioxide, while maintaining a thin layer of device quality epitaxial silicon at the surface.
- the surface is damaged reducing the quality of the epi-layer upon which devices are fabricated.
- Annealing can reduce the oxygen inclusion, however it is difficult to reduce the [0] to values below 10 17 /cm 3 .
- the thickness of the insulating layer is very difficult to control due to the random nature of scattering arising from ion implantation. Also, the ion implantation equipment costs are expensive.
- a second method of production is silicon-on-sapphire ("SOS"), hi SOS technology, circuitry is constructed in a layer of silicon, which has been deposited on a sapphire substrate.
- SOS silicon-on-sapphire
- This material has been used in the construction of radiation resistant circuits.
- problems with this material including large current conduction in the sapphire when exposed to radiation, brittleness causing breakage during integrated circuit fabrication and large mismatches between sapphire and silicon crystal structures. These problems have led to perfonnance and manufacturability limitations.
- a third method of production involves the bonding of two thin film wafers. In this approach, two bulk silicon wafers, each with a thermally grown oxide layer, are first bonded together to form a silicon/silicon dioxide/silicon wafer.
- Thin-film bonded wafers are constructed by bonding the two wafers and then thinning one of the two layers.
- Several alternatives are currently being explored across the industry to perform the subsequent thinning process ⁇ including mechanical polisliing, chemical etching; plasma assisted chemical etching, bond and selective etching of porous silicon or an implant- enhanced slicing of the wafer.
- the bonded wafer approach has the advantage that the buried oxide can be made very uniform and thick.
- the top silicon layer retains its high quality, achieving uniformity in the thickness of the top silicon layer, however, has proven difficult.
- the requirement to use two silicon wafers with complex processing has, to date, resulted in a relatively high cost structure for bonded wafers.
- p-n homojunction currently widely used in silicon devices has some serious limitations. Typical p-n homojunctions involve long range electrostatic interaction of free charges and are not abrupt. The electrostatic fields are continuous over a distance, which is significantly longer than the DeBroglie wavelength of an electron. It is a scattering dominated structure for electrons. On the other hand heteroj unctions are abrupt and analogous to a waterfall where the change in potential is confined to a very short distance. Heterojunctions are the basis of the barriers formed in GaAs/AlGaAs, GalnAs/AlInAs and other so-called JTI/V compounds from columns 3 and 5 of the periodic chart.
- the barriers of those heterojunctions derive from chemical bonding, and are short ranged.
- the continuous voltage changes occur over a distance of the order of one micron. With a heterojunction this occurs over a distance on the order of 0.5 nanometers, less than one percent the p-n junction distance.
- the heterojunction will be ever more important, particularly for quantum well structures.
- Dr. L. Esaki and Dr. R. Tsu while working jointly at the IBM research center (1 ' 2) , envisioned a new type of man made material which could be used to form what they called superlattice barriers and quantum wells to resolve some of the difficulties of the p- n junction.
- a "barrier" material is necessary that can be stacked between epitaxial device grade silicon. The present invention describes such a material.
- the invention provided a quantum well structure useful for semi-conducting devices, said structure comprising two barrier regions and a thin epitaxially grown monocrystalline semiconductor material quantum well sandwiched between said barrier regions, each barrier region consisting essentially of alternate strain layers forming a superlattice, each of said layers being thinner than said quantum well and being so thin that no defects are generated. Creating SiO 2 in such thin layers is commercially expensive and probably not viable.
- the present patent describes a substitute for SiO 2 in this application, which will be referred to as "said barrier".
- the silicon MOSFET is probably the single most important structure of electronic device.
- a layer of amorphous SiO 2 is typically sandwiched between a metal contact (the gate) and silicon channel region between the source and drain.
- the region of the layer near the silicon is filled with defects, reducing the switching speed of the device, apart from the more obvious problem of building epitaxially grown structure beyond the oxide barrier.
- U.262 (20) R.
- SILICON DIOXIDE AS A DIELECTRIC MATERIAL When SiO 2 is used as an insulating layer in semiconductor devices there is a capacitance and resistance associated with such a layer.
- the capacitance is a function of the area of the contact surface, the thickness of the SiO 2 layer and the dielectric constant of the SiO 2 material.
- the contact area and distance between contacts can be changed affecting the capacitance and hence the RC time constant associated with the SiO 2 insulating layer.
- the SiO 2 dielectric constant is fixed by the properties of SiO 2 and there is virtually no ability to change that property.
- the present invention overcomes the drawbacks and disadvantages of the above-described insulating layers and heterojunctions used in silicon based semiconductor devices.
- the present invention allows control over the dielectric constant, as well as, the thickness of said barrier.
- the invention provides a method for the formation of a Si/adsorbed-monolayer-of- oxygen (Si/O) as the building block of a barrier to form a repeatable system - a superlattice.
- This Si/O building block can be grown on a silicon substrate where silicon layers are grown epitaxially adjacent to each monolayer, or less, of adsorbed oxygen where therein is formed monolayers, or less, of adsorbed oxygen sandwiched between thin epitaxially grown silicon layers.
- barrier width is dictated by the Si-O-Si thickness which cannot be changed
- the formation of a superlattice by repeating the basic building block accomplishes the desired thickness of the barrier.
- a relatively thick barrier is used as an insulating layer for devices such as in the use of SOI, and thin barriers are used for most quantum devices.
- Silicon growth beyond a barrier structure consisting of thin layer (typically, 1-2 nm) of silicon sandwiched between adjacent layers of adsorbed oxygen up to 100 Langmuir of exposure is epitaxial and almost free of stacking faults as determined in high resolution TEM, transmission electron microscopy (reference 22).
- the measured barrier height in the conduction band of a double barrier structure with 1.1 nm silicon layer sandwiched between two adsorbed monolayers of oxygen is 0.5eV.
- the maximum barrier height in the conduction band is probably limited by 1.5eV, half as large as SiO 2 , which is 3.2eV.
- the rationale is that the interface layer consisting of S/O bonds is closer to SiO rather than SiO 2 .
- Si/adsorbed O may be repeated to form a superlattice.
- a superlattice of Si/O up to nine periods shows excellent epitaxial growth of silicon beyond the superlattice structure, indicating that the major objective has already been accomplished.
- the formation of the structure consists of the deposition of silicon by either MBE (Molecular Beam Epitaxy) or CVD (Chemical Vapor Deposition) onto an epitaxial silicon surface with a controlled adsorption of oxygen.
- the deposition temperature is generally kept below 650°C to limit possible subsequent desorption of the adsorbed oxygen.
- the exposure to oxygen is at temperatures generally below 500°C to prevent any migration or re-emission of the adsorbed oxygen.
- silicon capping usually greater than 4nm in thickness, can prevent any degradation. Specifically, the structure measured here is
- the invention also provides a method of introducing oxygen simultaneously during silicon deposition onto a silicon substrate to form a single insulating/barrier layer of silicon and oxygen referred to as EpiSiO x wherein 0 ⁇ x ⁇ 2.0.
- This structure forms an epitaxial system on silicon in which epitaxial silicon, almost free of defects such as stacking faults and dislocations, can be grown beyond this EpiSiO x .
- This system is therefore an ideal replacement of SOI presently available.
- a relatively thick barrier is used as an insulating layer for devices as is done in SOI, and thin barriers are used for most quantum devices.
- a layer of EpiSiO x has been formed with the following steps: • All depositions are below 650°C
- the silicon growth beyond the EpiSiO x of thickness below lOnm may be epitaxial with low defect densities below 10 9 /cm 2 .
- the thinner is the EpiSiO x ; the thinner is the silicon deposition beyond the structure for complete recovery. An example to make the point is for a 2nm EpiSiO x , only 4nm of silicon is needed to recover the surface reconstruction.
- the thicker is the EpiSiO x
- the thicker is the silicon deposition necessary to recover a perfect silicon surface reconstruction - the appearance of surface reconstruction is used as a figure of merit for the recovery of epitaxy.
- the invention includes a method of introducing other elements such as N, C, P, S, Sb, As, H, etc., which serve to replace oxygen for forming a barrier structure with silicon.
- elements such as N, C, P, S, Sb, As, H, etc.
- the Si/O superlattice and EpiSiO x may be reinforced by further diffusion of oxygen through the Si capping layer to be trapped by the barrier layers (Nakashima).
- the cap layer is epitaxial and defect free, serving as an ideal medium for FET devices, and (b) the epitaxial layer may be made thin enough itself to form barriers for quantum wells and for quantum devices such as the RTD, and quantum transistor and the single electron transistor.
- This invention further provides a method to adjust (change) the dielectric constant and barrier height of the barrier layers, both Si/O and EpiSiO x , by controlling the oxygen (or substitute element) content of the barrier.
- This can be accomplished by adjusting the level of oxygen during simultaneous deposition for EpiSiO x and controlling the percentage of monolayer oxygen coverage used in Si/O.
- the oxygen can further be adjusted during deposition to produce a barrier with a controlled gradient of oxygen content across the barrier thickness.
- Si/O this can be accomplished by repeating layers with varying oxygen exposure per layer. As we discussed before that the thicker the layer of epitaxially grown SiO x , the thicker is the subsequent Si growth for full recovery of epitaxy. Therefore, for thicker barrier requirements, we need to repeat the process, to build up the thickness of the barrier for a given application.
- Both Si/O and EpiSiO x can be fabricated using Molecular Beam Epitaxy (MBE), and in some cases with Chemical Vapor Deposition (CVD) or by any other means known to those familiar with the state of the art. Any of the above combinations of Si/O and/or EpiSiO x , either individually or in multiple layers, will from hereon be referred to as said barrier.
- MBE Molecular Beam Epitaxy
- CVD Chemical Vapor Deposition
- This invention further provides a Silicon-on-Insulator (SOI) structure where said barrier is used as the insulator in the SOI with an epitaxial silicon device layer adjacent to this layer.
- SOI Silicon-on-Insulator
- This barrier layer can be used as is or can be enhanced by a high temperature oxidation procedure as described by Nakashima et al. (21)
- the invention provides for quantum devices where said barrier is used as a barrier with silicon to produce Resonant Tunneling Devices (RTD), (Silicon RTD has been experimentally realized by researchers in Inst. Of Semiconductor Physics, Kiev, Ukraine: Preliminary in Litovcheko et al., JVST, B15, 439 (1997) (8) ), quantum well devices, single electron field effect transistors (SEFET), etc. It also provides a metal-oxide-semiconductor field-effect transistor (MOSFET) where the gate "oxide” is replaced completely or partially by said barrier. Additionally, this just described MOSFET can have a layer of said barrier just below the channel region of the device to produce a true two-dimensional electron gas between the source and drain thereby enhancing the mobility and performance of the device.
- RTD Resonant Tunneling Devices
- MOSFET metal-oxide-semiconductor field-effect transistor
- the main advantage of the present invention is that the said barrier allows for the continued epitaxial growth of silicon adjacent to this layer which is substantially defect free. This can be repeated to produce a stack of alternating said barrier and epitaxial device grade silicon in order to form a 3 -dimensional structure for producing the 3- dimensional integrated circuits (3D-IC) of the future in silicon (see figure 7).
- This invention makes it possible to form the active channel, the contacts, and the insulating regions epitaxially.
- the channel is made with epitaxial silicon on top of the EpiSiO x with the source and drain by conventional doping.
- Figure 1A is a diagrammatic illustration of a known CMOS.
- Figure IB is a diagrammatic illustration of a CMOS according to the present invention.
- Figure 2A is a schematic illustration of a known RHET.
- Figure 2B is a schematic illustration of a RHET according to the present invention.
- Figure 2C is a schematic illustration of an energy band diagram for Figs. 2A and
- Fig. 3 A is a schematic illustration of a known (MIS) TETRAN.
- Fig. 3B is a schematic illustration of a known GaAs TETRAN.
- Fig. 3C is a schematic illustration of a TETRAN according to the present invention.
- Fig. 4 is a schematic illustration of a known MOSFET.
- Fig. 5 is a schematic illustration of MOSFET according to the present invention.
- Fig. 6 is a schematic illustration of the gate region of a MOSFET according to the present invention.
- Fig. 7 is a schematic illustration of a portion of an IC according to the present invention.
- Fig. 8 is a schematic illustration of a composite structure according to the present invention.
- Figure 1 A is a typical CMOS structure (26) while figure IB is the same structure utilizing said barrier in an SOI approach.
- the individual devices are isolated from the substrate as well as each other eliminating the need for isolation wells, guard rings, etc.
- Figure 2A is an example of a quantum well structure device called a resonant- tunneling hot-electron transistor (RHET).
- RHET resonant- tunneling hot-electron transistor
- Figure 2 A is a standard RHET device in Gallium Arsenide.
- Figure 2B is the same structure applied to the present said barrier and silicon.
- Figure 2C shows the corresponding energy band diagram for these two structures identifying the quantum well region as part of the emitter for this device. (25)
- Figure 3 A illustrates a tunneling device called a Tui el-emitter Transistor (TETRAN).
- TTRAN Tui el-emitter Transistor
- Figure 3A shows this device as a metal-insulator-semiconductor (MIS) TETRAN where electrons tunnel through the thin SiO 2 layer.
- Figure 3B shows this same structure in GaAs where it would be more precisely referred to as a heterostructure TETRAN.
- figure 3C is this device where said barrier is substituted for the SiO 2 tunneling barrier of fig. 3 A (figs. 3 A & 3B from ref. 25).
- FIG 4 illustrates a conventional MOS structure as can be found in a Metal- oxide-semiconductor field-effect transistor (MOSFET) for example. This is typical of what is found between the gate and channel region of a MOSFET.
- Figure 5 illustrates a metal-said barrier -semiconductor structure. We will call this final device structure a metal-superlattice-semiconductor field-effect transistor (MSLSFET).
- MSLSFET metal-superlattice-semiconductor field-effect transistor
- Figure 6 illustrates a metal — oxide/said barrier — semiconductor interface, as would be used in the gate region of a field-effect transistor. This provides an improved interface between the silicon and the gate insulation layer while allowing for a thick layer of SiO 2 as usually applied.
- Figure 7 illustrates a proposed 3-dimensional chip architecture using said barrier to isolate epitaxial device layers from one another while providing for localized interconnect between layers.
- Figure 8 illustrates a proposed structure for very low defect epitaxial silicon (E) to be grown on top of an insulating layer (B) of the present invention which is in turn grown on a substrate of single crystal silicon (A).
- This approach uses multiple thin layers (B) of said barrier to reduce defect production in the total thickness of the insulating layer as opposed to one thick layer.
- a top "thin” reflection layer (D) of said barrier to further reduce the defects is included (13) .
- Si/O - A Si/absorbed-monolayer of oxygen next to a thin epitaxial layer of silicon is used as the building block of a barrier to form a repeatable system, a superlattice. Since all transport properties depend on both the barrier height and the barrier width, and since the barrier width is dictated by the Si-O-Si thickness which cannot be changed, the formation of a superlattice by repeating the basic building block accomplishes the desired thickness of the barrier. Relatively thick barriers are used as insulating devices including but not limited to SOI and thin barriers can be used in quantum devices.
- EpiSiO y - A relatively thick EpiSiO x layer consisting of SiO x with x being typically approximately 1 but variable from > 0 to 2 depending on application. This layer forms an epitaxial system on silicon on which epitaxial silicon, substantially free of defects such as stacking faults and dislocations can be
- the concentration of oxygen in each of the SiO x layers can be increased by partially replacing oxygen with other elements including but not limited to C, N, P, Sb, or As.
- the elements can be introduced either during the oxygen deposition process, after the oxygen has been deposited, or later during the high temperature oxygen annealing step (described below and in ref. 21) in accordance with methods well understood by those skilled in the art. These elements act as traps, getters or diffusion barriers to trap extra oxygen in the oxide layer.
- epitaxial silicon is deposited on the insulating oxide layer, hi some applications, even when above stated trapping/getting/diffusion elements are not used, after the epitaxial silicon is deposited, the structure can be annealed in an oxygen atmosphere according to Nakashima, allowing additional oxygen to penetrate through the epitaxial silicon into the oxide layer without introducing excess defects in the epitaxial silicon.
- Typical annealing temperatures are 1300°C. (21) (1) Si/O
- the epitaxial silicon sandwiched between two absorbed mono- layers of oxygen forms a unit, which can be repeated to give a superlattice structure.
- the barrier structure shows a barrier height of 0.5 eV, which is more than sufficient for most electronic and optoelectronic devices at room temperature.
- Current voltage measurements show the existence of a barrier
- surface Auger shows the presence of oxygen where expected
- high resolution X-TEM cross section transmission electron microscopy
- a substrate of monocrystalline silicon is heated to a temperature of between 400° and 700°C in a deposition chamber, preferably below 650°C Silicon and an impurity element are simultaneously introduced into the chamber by any method generally known to those skilled in the art.
- the impurity element is oxygen but other elements such as carbon and nitrogen as a pure gas or part of a gaseous compound which form an insulating barrier when combined with Si could be used.
- elements which could be introduced to form such an insulating barrier as well, including but not limited to oxygen and carbon, carbon and hydrogen or oxygen and nitrogen.
- a layer EpiSiO x is deposited on a substrate of silicon (or alternately on epitaxial silicon) and the concentrations of silicon and oxygen adjusted until optimum concentrations allow for the deposition of substantially defect free epitaxial silicon on the layer of EpiSiO x .
- the thickness of the insulating layer can be controlled by the time, deposition rate of silicon and temperature.
- the insulating properties of the barrier can be controlled by adjusting the amount of oxygen exposure.
- epitaxial silicon may be deposited on top of the insulating barrier producing a low defect layer of silicon for use in any of a number of methods used by those skilled in the art.
- Epitaxial silicon with less than 10 11 defects per square centimeter can be grown on top of the insulating barrier, with typical defects of less than 10 10 defects per square centimeter, providing device quality silicon on which to build conventional integrated circuits with significantly reduced leakage current, photoelectric devices of silicon or devices containing quantum wells of silicon.
- the silicon is deposited by electron beam epitaxy and oxygen is simultaneously introduced into the chamber in concentrations high enough to provide a quality insulating layer but low enough to insure that the oxide layer is epitaxially grown.
- This is monitored by using RHEED to insure that the crystalline structure of the silicon substrate is maintained in the oxide layer.
- RHEED is used to adjust the oxygen pressure and the rate of deposition of silicon.
- concentration of oxygen is too high or the deposition rate of silicon too slow, the RHEED pattern changes to indicate a reduction of quality of the subsequent surface from what is necessary to continue high quality epitaxial growth of silicon.
- the rate of silicon deposition can be measured with a 6 megahertz oscillating silicon crystal or any of a number of different methods.
- oxygen pressure is 10 "6 Torr, but it could be done with other higher and lower oxygen pressures.
- Typical electron beam epitaxy silicon deposition rates are 0.4 A/s using molecular beam deposition but these rates will vary depending on the process used.
- Chemical vapor deposition is one of a number of alternative methods of depositing the silicon and oxygen.
- the silicon substrate, on which the barrier is deposited is kept at temperatures of 400° to 700°C in a vacuum chamber typically kept at a pressure of 10 "6 Torr or less background pressure, however depending on the specific element introduced to form the insulating barrier these values will change.
- this invention includes other elements to be bonded with silicon to form said insulating layer.
- this invention includes other methods of depositing silicon with at least one other element in a way to form an insulating barrier.
- a very thin layer of EpiSiO x is deposited on a monocrystalline silicon substrate or on epitaxial silicon.
- a thin layer of epitaxial silicon is deposited next to the first EpiSiO x layer, which forms a building block for generating a superlattice of alternating layers of EpiSiO x and epitaxial silicon.
- the resultant structure has many applications in semiconductor devices.
- Figure 8 shows one of the preferred embodiments of the current invention.
- the thicker the layer of EpiSiO x the higher the number of dislocations in the epitaxial silicon above it. It is therefore another aspect of this invention to decrease the number of defects in the top layer (see Figure 8) of epitaxial silicon by using multiple thin layers of EpiSiO x in place of one thick layer of EpiSiO x .
- the thinner the layer of EpiSiO x the faster that the surface quality can be recovered.
- thicknesses of 25 Angstroms separated by epitaxial layers of 100 Angstroms are shown for the preferred embodiment, but these thicknesses may vary. Thus by using multiple layers, the number of defects in the final top epi-layer can be reduced.
- a quantum well consists of mono- crystalline silicon epitaxially grown between two said barrier sections.
- the barrier section consists of a region of alternate thin layers of Si and an oxygen enriched layer of Si (either EpiSiO x with 0 > x > 2.0 or a monolayer of oxygen). This structure exhibits all of the quantum confinement effects and is fully compatible with silicon technology.
- the quantum well structure for semiconducting devices comprises: first and second barrier regions each consisting of alternate layers of said barrier with thicknesses so thin that no defects can be generated as a result of the release of stored strain energy.
- This thickness is generally in the range of 2 to 4 monolayers.
- a much thicker section of pure silicon is sandwiched between this barrier regions service as quantum confinement of carriers.
- the proposed barriers can also serve to confine the holes in the valence band. Doping either with modulation doping, i.e. only in the silicon layers in the barrier region or involving also the well region may be incorporated to form desired junction characteristics. Hydrogen may also be used to passivate some of the residual defects if necessary.
- 3-dimensional IC devices can be constructed using said barrier between epitaxial layer of device grade silicon.
- IC devices are constructed in the individual silicon layers, which are connected within the layers and between the layers.
- Figure 7 shows a schematic illustration of how an insulating layer so deposited allows for epitaxial silicon to be grown on top of the insulator.
- the epitaxial silicon becomes the substrate for a new layer of IC devices, thus creating a three- dimensional integrated circuit.
- Interconnections between one layer and the next can be done in any of a number of ways which might include appropriate doping, such as n+ , of the epitaxial silicon to form conducting regions from one level of ICs to the next.
- FIG. 1 schematically illustrates how an SOI (said barrier shown as Insulator) layer can be typically used in a CMOS Inverter application.
- SOI semiconductor barrier shown as Insulator
- FIG. 4 The silicon MOSFET (FIG. 4) is probably the most important solid state electronic device.
- the oxide, amorphous SiO 2 is sandwiched between a metal gate contact and silicon channel region of the device. The lower the interface defect density between the SiO 2 and silicon, the faster the switching speed.
- the replacement of the amorphous SiO 2 by said barrier described in this invention can reduce the interface defect density between the silicon and the insulator.
- the amorphous SiO 2 serving as the insulating layer between the metal gate and the silicon is now replaced with said barrier.
- a layer of SiO 2 can be used between the top layer of said barrier and the metal gate. In this configuration there will still be defects at the interface with SiO 2 but now these defects are located away from the silicon, consequently not effecting the switching performance.
- VPE vapor phase epitaxy
- MBE molecular beam epitaxy
- sputtering sputtering
- CBE chemical beam epitaxy
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JP2003505987A JP2004535062A (en) | 2001-06-14 | 2001-06-14 | Epitaxial SiOx barrier / insulating layer |
EP01944705A EP1410427A4 (en) | 2001-06-14 | 2001-06-14 | Epitaxial sio x? barrier/insulation layer---------------------- |
US10/480,403 US7105895B2 (en) | 1997-11-10 | 2001-06-14 | Epitaxial SiOx barrier/insulation layer |
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US09/188,586 US6376337B1 (en) | 1997-11-10 | 1998-11-09 | Epitaxial SiOx barrier/insulation layer |
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Cited By (46)
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US20060003500A1 (en) | 2006-01-05 |
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